GNOME Bugzilla – Bug 656307
Language definition for SystemVerilog
Last modified: 2013-11-15 18:37:33 UTC
Asked in the mailing list: >Hello, > I didn't know where else to send/post this request. I was wondering >if it would be possible for you to add SystemVerilog as a Highlight >Mode option. SystemVerilog has a lot of additions to verilog and some >changes in syntax. Would help us hardware designers out alot. Thanks > >-Andrew J
We are not adding new language files if they are not provided. As it can be understood we don't know all languages. So feel free to provide it.
I don't think I can write out a whole language description in a reasonable amount of time. There are 2 books that describe SystemVerilog in great detail: SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling AND SystemVerilog for Verification: A Guide to Learning the Testbench Language Features Second (2nd) Edition I'm going to quickly tell you the main ideas of the differences, and then provide a link to asic-world's tutorial on system verilog. The main differences are that SystemVerilog allows you to use many constructs that other languages have, such as C++, including structs, classes, and many additional types of variable. On the more hardware side, they add interfaces and new always blocks which are for special purposes: always_ff, always_comb, and always_latch. Also, they add things like 'unique' or 'priority' as keywords in front of cases or if statements. Another new feature is packages, which are like modules, but can contain just about anything in there own scope. They need to be imported into the scope of the module or a higher scope in the SystemVerilog files. There is also new syntax for casting, and several more system calls. Also, there are many new reserved keywords. Here is a link to asic-worlds tutorial: http://www.asic-world.com/systemverilog/tutorial.html. They go over most of the differences and additions to SystemVerilog much more in depth than I can. Thanks
dunno, we are very strict on this. If you feel like providing this lang file at some point feel free to reopen the bug. It is not that we don't want this language in, it is that we don't have experience with it and we would make mistakes. Also we are have a lack of time to write new language files.
I'll try to work on this if I have some time. @AJ: could you attach a sample file containing SystemVerilog code (if possible, code representative of SystemVerilog extensions to Verilog)? So it could be used to test syntax highlighting. Thanks.
I can't attach any of my code for legal reasons. I can point you at free SystemVerilog code, though. Asic-World has dozens of examples using the new extension syntax. The file download links are on the webpages. http://www.asic-world.com/examples/systemverilog/index.html Here is an open source I2C verification SystemVerilog project. http://syswip.com/i2c-verification-ip Both links have good example files (*.sv) of SystemVerilog using new syntax.
Here we can find SystemVerilog syntax highlighting files (under GPL) for Kate, Crimson and SciTE: http://www.intelligentdv.com/downloads/index.html#syntaxfiles The one for Kate was recently added in KDE repository: https://projects.kde.org/projects/kde/kdebase/kate/repository/revisions/master/changes/part/syntax/data/systemverilog.xml I also found another for Kate here: http://lists.kde.org/?l=kwrite-devel&m=118182258108266&w=3 These files may help to write the one for gedit.
Reopening as code has been provided.
GtkSourceView has a SystemVerilog syntax file.