Steps to reproduce:
A file as inserted below lets doxygen run into the assertion posted as stack trace. 
-------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
library test_top;
use test_top.jtag_conf.all;
use test_top.jtag_pkg.all;


entity tb_jtag_gotoBackup is
end tb_jtag_gotoBackup;

architecture rtl of tb_jtag_gotoBackup is

  constant header : string := "tck tdi tms";

begin

  process
    file out_file    : text open write_mode is filename;
    variable outline : line;
    variable Addr    : string_8;
    variable Data    : string_array;
  begin

     tdi_delay       <= 1; 
     wait for 1 us;
    system_dbg;
    system_reset;


    ------------------------------------------------------------------------------------------------
    -- set the sleep register

    Addr    := "FFEC0004";              
    Data(0) := "FFFFFFFF";              
    LoadMultRegister(1, Addr, Data);

    Addr    := "FFEC0018";              
    Data(0) := "00000000";              
    LoadMultRegister(1, Addr, Data);

    Addr    := "FFEC0028";      -- PM register in RTC
    Data(0) := "00000000";      -- LDO2_en = MR_en = sleep_N = 0
    LoadMultRegister(1, Addr, Data);

    file_close(out_file);
    wait;
  end process;


end rtl;

library work;
configuration cfg_tb_jtag_gotoBackup of tb_jtag_gotoBackup is
  for RTL
  end for;
end cfg_tb_jtag_gotoBackup;
-----------------------

Stack trace:
ASSERT: "cd!=0 || nd!=0 || fd!=0 || gd!=0" in vhdldocgen.cpp (1814)

Other information:
I'm not really sure what causes the problem. The following patch solved the issue for me, I don't see any regression - but I don't know what I break with that.
-------------
1720,1721c1720,1721
<   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::LIBRARY,FALSE),0,FALSE,VhdlDocGen::LIBRARY);
<   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::USE,FALSE),0,FALSE,VhdlDocGen::USE);
---
>   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,fd,gd,theTranslator_vhdlType(VhdlDocGen::LIBRARY,FALSE),0,FALSE,VhdlDocGen::LIBRARY);
>   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,fd,gd,theTranslator_vhdlType(VhdlDocGen::USE,FALSE),0,FALSE,VhdlDocGen::USE);
1723c1723
<   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,0,gd,theTranslator_vhdlType(VhdlDocGen::COMPONENT,FALSE),0,FALSE,VhdlDocGen::COMPONENT);
---
>   VhdlDocGen::writeVHDLDeclarations(ml,ol,cd,0,fd,gd,theTranslator_vhdlType(VhdlDocGen::COMPONENT,FALSE),0,FALSE,VhdlDocGen::COMPONENT);
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