Created attachment 193930 [details]
Example vhdl source file, Doxyfile and generated output

In the latest version of the tool (1.7.5) the VHDL design unit hierarchy appears to be broken.  In the attached example, I believe the hierarchy should display as:

    my_top_level
        my_top_level::rtl
            my_low_level_component        
                my_low_level_component::rtl
            my_low_level_component
                my_low_level_component::rtl

instead, however, it appears as

    my_low_level_component        
        my_top_level::rtl
    my_top_level
    my_low_level_component::rtl

the design unit hierarchy is a very useful feature as it allows the design to be navigated very quickly and also provides an invaluable overview of a design's structure.

PS I don't know if the inclusion of the entity name as a prefix to the architecture is the cause of the problem but this is actually quite a nice addition as it prevents a long list of 'rtl's in the class list, for example.