The actual VHDL parser has a problem to parse the following structure (example):

    inst_name : entity work.entity_name
    port map (  clk => clk,
                rst => rst,
                d => d_in,
                q => q_out);

The problem is that it can not find the entity_name. As a result the hierarchy for the project can not be build.

Solution for this problem:

1. Add the following function the file vhdlparser.jj:

// entity name is lib_name.entity_name or only entity_name
QCString name_entity() : {QCString s;}
 {
  (
 <BASIC_IDENTIFIER> <DOT_T> s = name()
 | s = name()
  )
 {return s;}
 }


2. change in vhdlparser.jj the following part
QCString instantiation_unit() :  {QCString s,s1,s2;Token *tok=0;}
{
[ tok=<COMPONENT_T> ] s=identifier() {s1="component"; return s; }
| tok=<ENTITY_T> s2=name() {s=tok->image.c_str()+s2;} [ <LPAREN_T> s1=identifier() <RPAREN_T> {s+="(";s+=s1;s+=")" ;}] { return s;}
| <CONFIGURATION_T> s=name() {s1="configuration ";return s;}
}

to

QCString instantiation_unit() :  {QCString s,s1,s2;Token *tok=0;}
{
[ tok=<COMPONENT_T> ] s=identifier() {s1="component"; return s; }
| tok=<ENTITY_T> s2=name_entity() {s=s2;} [ <LPAREN_T> s1=identifier() <RPAREN_T> {s+="(";s+=s1;s+=")" ;}] { return s;}
| <CONFIGURATION_T> s=name() {s1="configuration ";return s;}
}

Walter