Tracker-Message: Starting tracker-extract 1.2.5
Tracker-Message: General options:
Tracker-Message:   Verbosity  ............................  3
Tracker-Message:   Sched Idle  ...........................  1
Tracker-Message:   Max bytes (per file)  .................  1048576
Tracker-Message: Setting priority nice level to 19
Tracker-Message: Loading extractor rules... (/usr/share/tracker/extract-rules)
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-abw.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-bmp.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-comics.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-dvi.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-ebooks.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-epub.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-flac.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-gif.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-html.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-ico.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-jpeg.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-msoffice.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-oasis.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-pdf.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-png.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-ps.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-svg.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-tiff.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-vorbis.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-xmp.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '10-xps.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '11-iso.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '11-msoffice-xml.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '15-gstreamer-guess.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '15-playlist.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '15-source-code.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '90-gstreamer-audio-generic.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '90-gstreamer-image-generic.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '90-gstreamer-video-generic.rule'
(tracker-extract:16228): Tracker-DEBUG:   Loaded rule '90-text-generic.rule'
Tracker-Message: Extractor rules loaded
(tracker-extract:16228): libmediaart-DEBUG: Initializing media art processing requirements...
(tracker-extract:16228): libmediaart-DEBUG: No mounts found to iterate
Tracker-Message: Initializing Storage...
Tracker-Message: Mount monitors set up for to watch for added, removed and pre-unmounts...
Tracker-Message: No mounts found to iterate
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:37: Waiting for service to become available...
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:45: Service is ready
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:47: Constructing connection
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:203: Using backend = 'AUTO'
(tracker-extract:16228): Tracker-DEBUG: Locale 'TRACKER_LOCALE_LANGUAGE' was set to 'en_GB.utf8'
(tracker-extract:16228): Tracker-DEBUG: Locale 'TRACKER_LOCALE_TIME' was set to 'en_GB.utf8'
(tracker-extract:16228): Tracker-DEBUG: Locale 'TRACKER_LOCALE_COLLATE' was set to 'en_GB.utf8'
(tracker-extract:16228): Tracker-DEBUG: Locale 'TRACKER_LOCALE_NUMERIC' was set to 'en_GB.utf8'
(tracker-extract:16228): Tracker-DEBUG: Locale 'TRACKER_LOCALE_MONETARY' was set to 'en_GB.utf8'
Tracker-Message: Current and DB locales match: 'en_GB.utf8'
Tracker-Message: Setting database locations
Tracker-Message: Checking database files exist
Tracker-Message: Opened sqlite3 database:'/home/zach/.cache/tracker/meta.db'
(tracker-extract:16228): Tracker-DEBUG: Resetting collator in db interface 0x19a70e0
(tracker-extract:16228): Tracker-DEBUG: [ICU collation] Initializing collator for locale 'en_GB.utf8'
(tracker-extract:16228): Tracker-DEBUG: Preparing query: 'PRAGMA journal_mode = WAL;'
Tracker-Message:   Setting page size to 8192
Tracker-Message:   Setting cache size to 250
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:49: Backend is ready
Tracker-Message: Trying to use introspection XML:
<node>  <interface name='org.freedesktop.Tracker1.Miner'>    <method name='Start'>    </method>    <method name='GetStatus'>      <arg type='s' name='status' direction='out' />    </method>    <method name='GetProgress'>      <arg type='d' name='progress' direction='out' />    </method>    <method name='GetRemainingTime'>      <arg type='i' name='remaining_time' direction='out' />    </method>    <method name='GetPauseDetails'>      <arg type='as' name='pause_applications' direction='out' />      <arg type='as' name='pause_reasons' direction='out' />    </method>    <method name='Pause'>      <arg type='s' name='application' direction='in' />      <arg type='s' name='reason' direction='in' />      <arg type='i' name='cookie' direction='out' />    </method>    <method name='PauseForProcess'>      <arg type='s' name='application' direction='in' />      <arg type='s' name='reason' direction='in' />      <arg type='i' name='cookie' direction='out' />    </method>    <method name='Resume'>      <arg type='i' name='cookie' direction='in' />    </method>    <method name='IgnoreNextUpdate'>      <arg type='as' name='urls' direction='in' />    </method>    <signal name='Started' />    <signal name='Stopped' />    <signal name='Paused' />    <signal name='Resumed' />    <signal name='Progress'>      <arg type='s' name='status' />      <arg type='d' name='progress' />      <arg type='i' name='remaining_time' />    </signal>    <!-- Additional introspection data given by other miners -->      </interface></node>

Tracker-Message: Registering D-Bus object...
Tracker-Message:   Path:'/org/freedesktop/Tracker1/Miner/Extract'
Tracker-Message:   Object Type:'TrackerExtractDecorator'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (rdf:type) { }'
(tracker-extract:16228): Tracker-DEBUG: Preparing query: 'SELECT COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0) FROM (SELECT 1)'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nie:dataSource) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (<http://www.tracker-project.org/ontologies/tracker#extractor-data-source>) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nfo:Document) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nfo:Audio) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nfo:Image) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nfo:Video) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:95: Tracker.Sparql.Backend.query(): 'select tracker:id (nfo:FilesystemImage) { }'
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:104: Tracker.Sparql.Backend.query_async(): 'SELECT tracker:id(?urn) tracker:id(?type) {   ?urn a rdfs:Resource ;        a ?type. FILTER (! EXISTS { ?urn nie:dataSource <http://www.tracker-project.org/ontologies/tracker#extractor-data-source> } && ?type IN (nfo:Document,nfo:Audio,nfo:Image,nfo:Video,nfo:FilesystemImage) && BOUND(tracker:available(?urn)))}'
(tracker-extract:16228): Tracker-DEBUG: Preparing query: 'SELECT "1_u", "2_u" FROM (SELECT "rdfs:Resource1"."ID" AS "1_u", "rdfs:Resource_rdf:type2"."rdf:type" AS "2_u" FROM "rdfs:Resource" AS "rdfs:Resource1", "rdfs:Resource_rdf:type" AS "rdfs:Resource_rdf:type2" WHERE "rdfs:Resource1"."ID" = "rdfs:Resource_rdf:type2"."ID" AND ((NOT ((EXISTS (SELECT 1 FROM "nie:DataObject_nie:dataSource" AS "nie:DataObject_nie:dataSource3" WHERE "1_u" = "nie:DataObject_nie:dataSource3"."ID" AND "nie:DataObject_nie:dataSource3"."nie:dataSource" = (SELECT ID FROM Resource WHERE Uri = ?)))) AND "2_u" IN (COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0), COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0), COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0), COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0), COALESCE((SELECT ID FROM Resource WHERE Uri = ?), 0))) AND ((SELECT "tracker:available" FROM "nie:DataObject" WHERE ID = "1_u") IS NOT NULL)))'
Tracker-Message: Starting to process 1 items
(tracker-extract:16228): Tracker-DEBUG: tracker-backend.vala:104: Tracker.Sparql.Backend.query_async(): 'SELECT ?urn       tracker:id(?urn)        nie:url(?urn)        nie:mimeType(?urn) {   ?urn tracker:available true .   FILTER (tracker:id(?urn) IN (100673) &&           ! EXISTS { ?urn nie:dataSource <http://www.tracker-project.org/ontologies/tracker#extractor-data-source> })}'
(tracker-extract:16228): Tracker-DEBUG: Preparing query: 'SELECT (SELECT Uri FROM Resource WHERE ID = "1_u"), "1_u", (SELECT "nie:url" FROM "nie:DataObject" WHERE ID = "1_u") COLLATE TRACKER, (SELECT "nie:mimeType" FROM "nie:InformationElement" WHERE ID = "1_u") COLLATE TRACKER FROM (SELECT "nie:DataObject1"."ID" AS "1_u" FROM "nie:DataObject" AS "nie:DataObject1" WHERE "nie:DataObject1"."tracker:available" = ? AND ("1_u" IN (?) AND NOT ((EXISTS (SELECT 1 FROM "nie:DataObject_nie:dataSource" AS "nie:DataObject_nie:dataSource2" WHERE "1_u" = "nie:DataObject_nie:dataSource2"."ID" AND "nie:DataObject_nie:dataSource2"."nie:dataSource" = (SELECT ID FROM Resource WHERE Uri = ?))))))'
Tracker-Message: Extracting metadata for 'file:///home/zach/Documents/stm32/stm32f10x-reference.pdf'
Tracker-Message: MIME type passed to us as 'application/pdf'
(tracker-extract:16228): Tracker-DEBUG: Miner:'Extract' noticed store availability has changed to AVAILABLE
(tracker-extract:16228): Tracker-DEBUG: Using /usr/lib64/tracker-1.0/extract-modules/libextract-pdf.so...

(tracker-extract:16228): Tracker-CRITICAL **: tracker_xmp_new: assertion 'len > 0' failed
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INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "Technical Literature" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "Technical Literature" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "13902" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "13902" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "Product Development" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "Product Development" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "Specification" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "Specification" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "Reference manual" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "Reference manual" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103ZG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103ZG" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103ZF" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103ZF" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103ZE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103ZE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103ZD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103ZD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103ZC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103ZC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VG" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VF" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VF" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103VB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103VB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103V8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103V8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103TC" }  }
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INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103TB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103TB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103T8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103T8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103T6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103T6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103T4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103T4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103S6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103S6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RG" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RF" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RF" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103RB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103RB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103R8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103R8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103R6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103R6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103R4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103R4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103EDIE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103EDIE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103CB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103CB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103C8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103C8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103C6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103C6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103C4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103C4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F103BDIE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F103BDIE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F1036DIE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F1036DIE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102T8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102T8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102RC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102RC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102RB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102RB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102R8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102R8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102R6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102R6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102R4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102R4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102CB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102CB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102C8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102C8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102C6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102C6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F102C4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F102C4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101ZG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101ZG" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101C4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101C4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101C6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101C6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101C8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101C8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101CB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101CB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101R4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101R4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101R6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101R6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101R8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101R8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101T4" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101T4" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101T6" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101T6" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101T8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101T8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101TB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101TB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101V8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101V8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101ZC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101ZC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101ZD" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101ZD" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101ZE" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101ZE" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F107VC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F107VC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F107VB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F107VB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F107RC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F107RC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F107RB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F107RB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105VC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105VC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105VB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105VB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105V8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105V8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105RC" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105RC" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105RB" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105RB" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F105R8" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F105R8" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RF" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RF" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101RG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101RG" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VF" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VF" }) }
INSERT { GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> { _:tag a nao:Tag ; nao:prefLabel "STM32F101VG" }  }
WHERE { FILTER (NOT EXISTS { ?tag a nao:Tag ; nao:prefLabel "STM32F101VG" }) }

INSERT {
GRAPH <urn:uuid:472ed0cc-40ff-4e37-9c0c-062d78656540> {
<urn:uuid:c76b2bf0-efd6-3d6d-76d2-c0ef00bd7d5a> nie:dataSource <http://www.tracker-project.org/ontologies/tracker#extractor-data-source> .
<urn:uuid:c76b2bf0-efd6-3d6d-76d2-c0ef00bd7d5a> a nfo:PaginatedTextDocument ;
	 nie:title "STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced ARM-based 32-bit MCUs" ;
	 nie:subject "-" ;
	 nco:creator [ a nco:Contact ;
	 nco:fullname "STMICROELECTRONICS"] ;
	 nao:hasTag ?tag1 ;
	 nao:hasTag ?tag2 ;
	 nao:hasTag ?tag3 ;
	 nao:hasTag ?tag4 ;
	 nao:hasTag ?tag5 ;
	 nao:hasTag ?tag6 ;
	 nao:hasTag ?tag7 ;
	 nao:hasTag ?tag8 ;
	 nao:hasTag ?tag9 ;
	 nao:hasTag ?tag10 ;
	 nao:hasTag ?tag11 ;
	 nao:hasTag ?tag12 ;
	 nao:hasTag ?tag13 ;
	 nao:hasTag ?tag14 ;
	 nao:hasTag ?tag15 ;
	 nao:hasTag ?tag16 ;
	 nao:hasTag ?tag17 ;
	 nao:hasTag ?tag18 ;
	 nao:hasTag ?tag19 ;
	 nao:hasTag ?tag20 ;
	 nao:hasTag ?tag21 ;
	 nao:hasTag ?tag22 ;
	 nao:hasTag ?tag23 ;
	 nao:hasTag ?tag24 ;
	 nao:hasTag ?tag25 ;
	 nao:hasTag ?tag26 ;
	 nao:hasTag ?tag27 ;
	 nao:hasTag ?tag28 ;
	 nao:hasTag ?tag29 ;
	 nao:hasTag ?tag30 ;
	 nao:hasTag ?tag31 ;
	 nao:hasTag ?tag32 ;
	 nao:hasTag ?tag33 ;
	 nao:hasTag ?tag34 ;
	 nao:hasTag ?tag35 ;
	 nao:hasTag ?tag36 ;
	 nao:hasTag ?tag37 ;
	 nao:hasTag ?tag38 ;
	 nao:hasTag ?tag39 ;
	 nao:hasTag ?tag40 ;
	 nao:hasTag ?tag41 ;
	 nao:hasTag ?tag42 ;
	 nao:hasTag ?tag43 ;
	 nao:hasTag ?tag44 ;
	 nao:hasTag ?tag45 ;
	 nao:hasTag ?tag46 ;
	 nao:hasTag ?tag47 ;
	 nao:hasTag ?tag48 ;
	 nao:hasTag ?tag49 ;
	 nao:hasTag ?tag50 ;
	 nao:hasTag ?tag51 ;
	 nao:hasTag ?tag52 ;
	 nao:hasTag ?tag53 ;
	 nao:hasTag ?tag54 ;
	 nao:hasTag ?tag55 ;
	 nao:hasTag ?tag56 ;
	 nao:hasTag ?tag57 ;
	 nao:hasTag ?tag58 ;
	 nao:hasTag ?tag59 ;
	 nao:hasTag ?tag60 ;
	 nao:hasTag ?tag61 ;
	 nao:hasTag ?tag62 ;
	 nao:hasTag ?tag63 ;
	 nao:hasTag ?tag64 ;
	 nao:hasTag ?tag65 ;
	 nao:hasTag ?tag66 ;
	 nao:hasTag ?tag67 ;
	 nao:hasTag ?tag68 ;
	 nao:hasTag ?tag69 ;
	 nao:hasTag ?tag70 ;
	 nao:hasTag ?tag71 ;
	 nao:hasTag ?tag72 ;
	 nao:hasTag ?tag73 ;
	 nao:hasTag ?tag74 ;
	 nao:hasTag ?tag75 ;
	 nao:hasTag ?tag76 ;
	 nao:hasTag ?tag77 ;
	 nao:hasTag ?tag78 ;
	 nao:hasTag ?tag79 ;
	 nao:hasTag ?tag80 ;
	 nao:hasTag ?tag81 ;
	 nao:hasTag ?tag82 ;
	 nao:hasTag ?tag83 ;
	 nao:hasTag ?tag84 ;
	 nao:hasTag ?tag85 ;
	 nao:hasTag ?tag86 ;
	 nao:hasTag ?tag87 ;
	 nfo:pageCount 1096 ;
	 nie:plainTextContent "RM0008\nReference manual\nSTM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx\nand STM32F107xx advanced ARM-based 32-bit MCUs\nIntroduction\nThis reference manual targets application developers. It provides complete information on\nhow to use the STM32F101xx, STM32F102xx, STM32F103xx and\nSTM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,\nSTM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as\nSTM32F10xxx throughout the document, unless otherwise specified.\nThe STM32F10xxx is a family of microcontrollers with different memory sizes, packages and\nperipherals.\nFor ordering information, mechanical and electrical device characteristics please refer to the\nlow-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the\nlow- and medium-density STM32F102xx datasheets and to the\nSTM32F105xx/STM32F107xx connectivity line datasheet.\nFor information on programming, erasing and protection of the internal Flash memory\nplease refer to:\n● PM0075, the Flash programming manual for low-, medium- high-density and\nconnectivity line STM32F10xxx devices\n● PM0068, the Flash programming manual for XL-density STM32F10xxx devices.\nFor information on the ARM Cortex™-M3 core, please refer to the STM32F10xxx Cortex™-\nM3 programming manual (PM0056).\nRelated documents\nAvailable from www.st.com:\n■ STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and\ndatasheets\n■ STM32F10xxx Cortex™-M3 programming manual (PM0056)\n■ STM32F10xxx Flash programming manual (PM0075)\n■ STM32F10xxx XL-density Flash programming manual (PM0068)\nOctober 2011\nDoc ID 13902 Rev 14\n1/1096\nwww.st.com Contents\nRM0008\nContents\n1 Overview of the manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40\n2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46\n3\n2.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46\n2.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46\n2.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46\nMemory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47\n3.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47\n3.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49\n3.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50\n3.4\n4\n5\n3.3.1 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53\n3.3.2 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53\n3.3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54\nBoot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60\nCRC calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n4.1 CRC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\n4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n4.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n4.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63\n4.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . . 63\n4.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\n4.4.4 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\nPower control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65\n5.1\n5.2\nPower supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65\n5.1.1 Independent A/D and D/A converter supply and reference voltage . . . . 66\n5.1.2 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67\n5.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\nPower supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\n5.2.1\n2/1096\nPower on reset (POR)/power down reset (PDR) . . . . . . . . . . . . . . . . . . 68\nDoc ID 13902 Rev 14 RM0008\nContents\n5.2.2\n5.3\n5.4\n6\nLow-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70\n5.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70\n5.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\n5.3.3 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71\n5.3.4 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72\n5.3.5 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\n5.3.6 Auto-wakeup (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . . 75\nPower control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75\n5.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75\n5.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 77\n5.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nBackup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79\n6.1 BKP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79\n6.2 BKP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79\n6.3 BKP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\n6.4\n7\nProgrammable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 68\n6.3.1 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\n6.3.2 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80\nBKP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81\n6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) . . . . . . . . . . . . . . . . . . . 81\n6.4.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . . 81\n6.4.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82\n6.4.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . . 82\n6.4.5 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83\nLow-, medium-, high- and XL-density reset and clock\ncontrol (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87\n7.1\n7.2\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87\n7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87\n7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\n7.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89\n7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91\n7.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92\n7.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93\nDoc ID 13902 Rev 14\n3/1096 Contents\nRM0008\n7.3\n8\nLSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93\n7.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93\n7.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94\n7.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94\n7.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\n7.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\n7.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96\n7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96\n7.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 98\n7.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101\n7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 103\n7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 106\n7.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 108\n7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 109\n7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 111\n7.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 115\n7.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 117\n7.3.11 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119\nConnectivity line devices: reset and clock control (RCC) . . . . . . . . . 120\n8.1\n8.2\n8.3\n4/1096\n7.2.4\nReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120\n8.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120\n8.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121\n8.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122\nClocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122\n8.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124\n8.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\n8.2.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\n8.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126\n8.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\n8.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127\n8.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128\n8.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128\n8.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128\n8.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\nRCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\nDoc ID 13902 Rev 14 RM0008\n9\nContents\n8.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129\n8.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 131\n8.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 134\n8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 137\n8.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 138\n8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . 141\n8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 142\n8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 144\n8.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . 146\n8.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 148\n8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) . . . . . . . . . . . . 149\n8.3.12 Clock configuration register2 (RCC_CFGR2) . . . . . . . . . . . . . . . . . . . 150\n8.3.13 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs) . . 154\n9.1\n9.2\n9.3\nGPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154\n9.1.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\n9.1.2 Atomic bit set or reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\n9.1.3 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n9.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n9.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . 157\n9.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157\n9.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n9.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\n9.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\n9.1.10 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\n9.1.11 GPIO configurations for device peripherals . . . . . . . . . . . . . . . . . . . . . 161\nGPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166\n9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . . . . . . . . 166\n9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . . . . . . . 167\n9.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . . . . . . . . . . . . . . 167\n9.2.4 Port output data register (GPIOx_ODR) (x=A..G) . . . . . . . . . . . . . . . . 168\n9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . . . . . . . . . . . . 168\n9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) . . . . . . . . . . . . . . . . . . . 169\n9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . . . . . . . 169\nAlternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . 170\n9.3.1\nUsing OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . 170\nDoc ID 13902 Rev 14\n5/1096 Contents\nRM0008\n9.4\n9.5\n10\nUsing OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . 170\n9.3.3 CAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\n9.3.4 CAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\n9.3.5 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . 171\n9.3.6 ADC alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172\n9.3.7 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 173\n9.3.8 USART alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . 175\n9.3.9 I2C1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\n9.3.10 SPI1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\n9.3.11 SPI3/I2S3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 176\n9.3.12 Ethernet alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . 176\nAFIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177\n9.4.1 Event control register (AFIO_EVCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 178\n9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . 179\n9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . 185\n9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . 185\n9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . 186\n9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . 186\n9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . . 187\nGPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188\nInterrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190\n10.1\n10.2\n10.3\n6/1096\n9.3.2\nNested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 190\n10.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190\n10.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190\nExternal interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 198\n10.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198\n10.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198\n10.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199\n10.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199\n10.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 200\nEXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202\n10.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 202\n10.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202\n10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 203\n10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 203\n10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 204\nDoc ID 13902 Rev 14 RM0008\n11\nContents\n10.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204\n10.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205\nAnalog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206\n11.1 ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206\n11.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207\n11.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207\n11.3.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210\n11.3.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210\n11.3.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210\n11.3.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210\n11.3.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211\n11.3.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211\n11.3.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\n11.3.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\n11.3.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213\n11.3.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214\n11.4 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214\n11.5 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\n11.6 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 216\n11.7 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216\n11.8 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218\n11.9 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219\n11.9.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n11.9.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\n11.9.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n11.9.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\n11.9.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\n11.9.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224\n11.9.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 224\n11.9.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 224\n11.9.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 225\n11.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226\n11.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227\n11.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228\n11.12.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228\nDoc ID 13902 Rev 14\n7/1096 Contents\nRM0008\n11.12.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229\n11.12.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 231\n11.12.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 235\n11.12.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 236\n11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 236\n11.12.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 237\n11.12.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 237\n11.12.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 238\n11.12.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 239\n11.12.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 240\n11.12.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 241\n11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 242\n11.12.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 242\n11.12.15 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243\n12\nDigital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245\n12.1 DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245\n12.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245\n12.3 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n12.4\n8/1096\n12.3.1 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n12.3.2 DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n12.3.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247\n12.3.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248\n12.3.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249\n12.3.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249\n12.3.7 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250\n12.3.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250\n12.3.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251\nDual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252\n12.4.1 Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 252\n12.4.2 Independent trigger with same LFSR generation . . . . . . . . . . . . . . . . 253\n12.4.3 Independent trigger with different LFSR generation . . . . . . . . . . . . . . 253\n12.4.4 Independent trigger with same triangle generation . . . . . . . . . . . . . . . 253\n12.4.5 Independent trigger with different triangle generation . . . . . . . . . . . . . 254\n12.4.6 Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254\n12.4.7 Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 254\n12.4.8 Simultaneous trigger with same LFSR generation . . . . . . . . . . . . . . . 255\nDoc ID 13902 Rev 14 RM0008\nContents\n12.4.9\nSimultaneous trigger with different LFSR generation . . . . . . . . . . . . . 255\n12.4.10 Simultaneous trigger with same triangle generation . . . . . . . . . . . . . . 255\n12.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 256\n12.5\nDAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256\n12.5.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256\n12.5.2 DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 259\n12.5.3 DAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260\n12.5.4 DAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260\n12.5.5 DAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260\n12.5.6 DAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261\n12.5.7 DAC channel2 12-bit left aligned data holding register\n(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261\n12.5.8 DAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261\n12.5.9 Dual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262\n12.5.10 DUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262\n12.5.11 DUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263\n12.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 263\n12.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 263\n12.5.14 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264\n13\nDirect memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 265\n13.1 DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265\n13.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265\n13.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\n13.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267\n13.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268\n13.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268\n13.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 270\n13.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\n13.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\n13.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272\nDoc ID 13902 Rev 14\n9/1096 Contents\nRM0008\n13.4\n14\nDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275\n13.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 275\n13.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 276\n13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7,\nwhere x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277\n13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7),\nwhere x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278\n13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7),\nwhere x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\n13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7),\nwhere x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279\n13.4.7 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nAdvanced-control timers (TIM1&TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 282\n14.1 TIM1&TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282\n14.2 TIM1&TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283\n14.3 TIM1&TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n14.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285\n14.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286\n14.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294\n14.3.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296\n14.3.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298\n14.3.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300\n14.3.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301\n14.3.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302\n14.3.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303\n14.3.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304\n14.3.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 307\n14.3.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308\n14.3.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 311\n14.3.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\n14.3.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313\n14.3.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314\n14.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317\n14.3.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317\n14.3.19 TIMx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 319\n14.3.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322\n14.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322\n10/1096\nDoc ID 13902 Rev 14 RM0008\nContents\n14.4\nTIM1&TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323\n14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 323\n14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 324\n14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 327\n14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . 329\n14.4.5 TIM1&TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 331\n14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 332\n14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 334\n14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . 337\n14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . 338\n14.4.10 TIM1&TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341\n14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 341\n14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 341\n14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 342\n14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 342\n14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 343\n14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 343\n14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 344\n14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . 344\n14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 346\n14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . 347\n14.4.21 TIM1&TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\n15\nGeneral-purpose timers (TIM2 to TIM5) . . . . . . . . . . . . . . . . . . . . . . . . 350\n15.1 TIM2 to TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350\n15.2 TIMx main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351\n15.3 TIMx functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352\n15.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352\n15.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354\n15.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363\n15.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366\n15.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367\n15.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368\n15.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369\n15.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370\n15.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371\n15.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\nDoc ID 13902 Rev 14\n11/1096 Contents\nRM0008\n15.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 375\n15.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376\n15.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378\n15.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 378\n15.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382\n15.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\n15.4\nTIMx2 to TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388\n15.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 388\n15.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 390\n15.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 391\n15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 393\n15.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394\n15.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 396\n15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 397\n15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 400\n15.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 401\n15.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\n15.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\n15.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 403\n15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 404\n15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 404\n15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 405\n15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 405\n15.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 406\n15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 406\n15.4.19 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\n16\nGeneral-purpose timers (TIM9 to TIM14) . . . . . . . . . . . . . . . . . . . . . . . 410\n16.1 TIM9 to TIM14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410\n16.2 TIM9 to TIM14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411\n16.2.1\n12/1096\nTIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411\n16.3 TIM10/TIM11 and TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . 412\n16.4 TIM9 to TIM14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 413\n16.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413\n16.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414\n16.4.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\n16.4.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\nDoc ID 13902 Rev 14 RM0008\nContents\n16.4.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420\n16.4.6 PWM input mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 421\n16.4.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422\n16.4.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423\n16.4.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424\n16.4.10 One-pulse mode (only for TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 425\n16.4.11 TIM9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 426\n16.4.12 Timer synchronization (TIM9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429\n16.4.13 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429\n16.5\nTIM9 and TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430\n16.5.1 TIM9/12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 430\n16.5.2 TIM9/12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . 431\n16.5.3 TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . 432\n16.5.4 TIM9/12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 433\n16.5.5 TIM9/12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . 434\n16.5.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . 435\n16.5.7 TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . . . . . . 438\n16.5.8 TIM9/12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\n16.5.9 TIM9/12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\n16.5.10 TIM9/12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 439\n16.5.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 440\n16.5.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 440\n16.5.13 TIM9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\n16.6\nTIM10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442\n16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . 442\n16.6.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 443\n16.6.3 TIM10/11/13/14 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . 443\n16.6.4 TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . . . . . . . 444\n16.6.5 TIM10/11/13/14 capture/compare mode register 1\n(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445\n16.6.6 TIM10/11/13/14 capture/compare enable register\n(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447\n16.6.7 TIM10/11/13/14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 448\n16.6.8 TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . 448\n16.6.9 TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . 448\n16.6.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . . . . 449\n16.6.11 TIM10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449\nDoc ID 13902 Rev 14\n13/1096 Contents\n17\nRM0008\nBasic timers (TIM6&TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n17.1 TIM6&TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n17.2 TIM6&TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451\n17.3 TIM6&TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n17.4\n18\nTime-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\n17.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\n17.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\n17.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457\nTIM6&TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457\n17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 457\n17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . 459\n17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . 459\n17.4.4 TIM6&TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 460\n17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 460\n17.4.6 TIM6&TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460\n17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 461\n17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 461\n17.4.9 TIM6&TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462\nReal-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\n18.1 RTC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463\n18.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464\n18.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n18.4\n14/1096\n17.3.1 18.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\n18.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n18.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n18.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466\n18.3.5 RTC flag assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nRTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468\n18.4.1 RTC control register high (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 468\n18.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 469\n18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 470\n18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 471\n18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 472\n18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 473\n18.4.7 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\nDoc ID 13902 Rev 14 RM0008\n19\nContents\nIndependent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n19.1 IWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n19.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n19.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475\n19.4\n20\n21\n19.3.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\n19.3.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\n19.3.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\nIWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n19.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477\n19.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478\n19.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478\n19.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\n19.4.5 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\nWindow watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n20.1 WWDG introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n20.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n20.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480\n20.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 482\n20.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\n20.6 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n20.6.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484\n20.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 485\n20.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485\n20.6.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\nFlexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 487\n21.1 FSMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487\n21.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488\n21.3 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489\n21.3.1\n21.4\n21.5\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 490\nExternal device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491\n21.4.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491\n21.4.2 NAND/PC Card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492\nNOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\nDoc ID 13902 Rev 14\n15/1096 Contents\nRM0008\n21.6\n22\n21.5.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\n21.5.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 496\n21.5.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497\n21.5.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 497\n21.5.5 Synchronous burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513\n21.5.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519\nNAND Flash/PC Card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524\n21.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525\n21.6.2 NAND Flash / PC Card supported memories and transactions . . . . . . 527\n21.6.3 Timing diagrams for NAND and PC Card . . . . . . . . . . . . . . . . . . . . . . 527\n21.6.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528\n21.6.5 NAND Flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529\n21.6.6 Error correction code computation ECC (NAND Flash) . . . . . . . . . . . . 530\n21.6.7 PC Card/CompactFlash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 530\n21.6.8 NAND Flash/PC Card controller registers . . . . . . . . . . . . . . . . . . . . . . 533\n21.6.9 FSMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539\nSecure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . 541\n22.1 SDIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541\n22.2 SDIO bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\n22.3 SDIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\n22.4\n22.3.1 SDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545\n22.3.2 SDIO AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555\nCard functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\n22.4.1 Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\n22.4.2 Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\n22.4.3 Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 556\n22.4.4 Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557\n22.4.5 Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n22.4.6 Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558\n22.4.7 Stream access, stream write and stream read (MultiMediaCard only) 559\n22.4.8 Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 560\n22.4.9 Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561\n22.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561\n22.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564\n22.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567\n22.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571\n16/1096\nDoc ID 13902 Rev 14 RM0008\nContents\n22.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572\n22.5\n22.6\n22.7\nResponse formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575\n22.5.1 R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n22.5.2 R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n22.5.3 R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n22.5.4 R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\n22.5.5 R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\n22.5.6 R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\n22.5.7 R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\n22.5.8 R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\nSDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579\n22.6.1 SDIO I/O read wait operation by SDIO_D2 signalling . . . . . . . . . . . . . 579\n22.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . . . . . . . . . . . . 579\n22.6.3 SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580\n22.6.4 SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580\nCE-ATA specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580\n22.7.1 Command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 580\n22.7.2 Command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 580\n22.7.3 CE-ATA interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581\n22.7.4 Aborting CMD61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581\n22.8 HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581\n22.9 SDIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581\n22.9.1 SDIO power control register (SDIO_POWER) . . . . . . . . . . . . . . . . . . . 582\n22.9.2 SDI clock control register (SDIO_CLKCR) . . . . . . . . . . . . . . . . . . . . . . 582\n22.9.3 SDIO argument register (SDIO_ARG) . . . . . . . . . . . . . . . . . . . . . . . . . 583\n22.9.4 SDIO command register (SDIO_CMD) . . . . . . . . . . . . . . . . . . . . . . . . 584\n22.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . . . . . . . 585\n22.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . . . . . . . . . . . . . . . 585\n22.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . . . . . . . . . . . . . . . . . 586\n22.9.8 SDIO data length register (SDIO_DLEN) . . . . . . . . . . . . . . . . . . . . . . 586\n22.9.9 SDIO data control register (SDIO_DCTRL) . . . . . . . . . . . . . . . . . . . . . 587\n22.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 588\n22.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589\n22.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 590\n22.9.13 SDIO mask register (SDIO_MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 592\n22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . . . . . . . . . . . . . . 594\nDoc ID 13902 Rev 14\n17/1096 Contents\nRM0008\n22.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . . . . . . . . . . . . . . . . . . . . 595\n22.9.16 SDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595\n23\nUniversal serial bus full-speed device interface (USB) . . . . . . . . . . . 597\n23.1 USB introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\n23.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\n23.3 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597\n23.3.1\n23.4\n23.5\n24\nProgramming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\n23.4.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 600\n23.4.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601\n23.4.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605\n23.4.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609\n23.4.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610\nUSB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n23.5.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612\n23.5.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619\n23.5.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623\n23.5.4 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626\nController area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628\n24.1 bxCAN introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628\n24.2 bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628\n24.3 bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\n24.4\n24.5\n18/1096\nDescription of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599\n24.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n24.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 630\n24.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630\n24.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630\nbxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631\n24.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632\n24.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632\n24.4.3 Sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632\nTest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633\n24.5.1 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633\n24.5.2 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634\n24.5.3 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 634\nDoc ID 13902 Rev 14 RM0008\n25\nContents\n24.6 STM32F10xxx in Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\n24.7 bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\n24.7.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\n24.7.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 637\n24.7.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637\n24.7.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638\n24.7.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642\n24.7.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644\n24.7.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644\n24.8 bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647\n24.9 CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648\n24.9.1 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648\n24.9.2 CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648\n24.9.3 CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658\n24.9.4 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665\n24.9.5 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\nSerial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672\n25.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672\n25.2 SPI and I 2 S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\n25.3\n25.2.1 SPI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673\n25.2.2 I 2 S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674\nSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675\n25.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675\n25.3.2 Configuring the SPI in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678\n25.3.3 Configuring the SPI in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 680\n25.3.4 Configuring the SPI for simplex communication . . . . . . . . . . . . . . . . . 681\n25.3.5 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 681\n25.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688\n25.3.7 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690\n25.3.8 Disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691\n25.3.9 SPI communication using DMA (direct memory addressing) . . . . . . . 692\n25.3.10 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693\n25.3.11 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694\n25.4\nI 2 S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695\nDoc ID 13902 Rev 14\n19/1096 Contents\nRM0008\n25.5\n25.4.1 The I 2 S audio protocol is not available in low- and medium-density\ndevices. This section concerns only high-density, XL-density and\nconnectivity line devices. I 2 S general description 695\n25.4.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696\n25.4.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\n25.4.4 I 2 S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708\n25.4.5 I 2 S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709\n25.4.6 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711\n25.4.7 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\n25.4.8 I 2 S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712\n25.4.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\nSPI and I 2 S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714\n25.5.1 SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . . . . . . . 714\n25.5.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716\n25.5.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717\n25.5.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718\n25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S\nmode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718\n25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . . . 719\n25.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . . . 719\n25.5.8 SPI_I 2 S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 720\n25.5.9 SPI_I 2 S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 721\n25.5.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\n26\nInter-integrated circuit (I 2 C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 723\n26.1 I 2 C introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n26.2 I 2 C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723\n26.3 I 2 C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724\n26.4\n20/1096\n26.3.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724\n26.3.2 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\n26.3.3 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\n26.3.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736\n26.3.5 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737\n26.3.6 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738\n26.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740\n26.3.8 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742\n2\nI C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742\nDoc ID 13902 Rev 14 RM0008\nContents\n26.5 I 2 C debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744\n26.6 I 2 C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744\n26.6.1 I 2 C Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744\n26.6.2 I 2 C Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746\n26.6.3 I 2 C Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 748\n26.6.4 I 2 C Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 748\n26.6.5 I 2 C Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749\n26.6.6 I 2 C Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749\n26.6.7 I 2 C Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753\n26.6.8 I 2 C Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . 754\n26.6.9 I 2 C TRISE register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755\n26.6.10 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\n27\nUniversal synchronous asynchronous receiver\ntransmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757\n27.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757\n27.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758\n27.3 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759\n27.3.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762\n27.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763\n27.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766\n27.3.4 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770\n27.3.5 USART receiver’s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 772\n27.3.6 Multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\n27.3.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\n27.3.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 775\n27.3.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777\n27.3.10 Single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 779\n27.3.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780\n27.3.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\n27.3.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 784\n27.3.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787\n27.4 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788\n27.5 USART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789\n27.6 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789\n27.6.1\nStatus register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790\nDoc ID 13902 Rev 14\n21/1096 Contents\n28\nRM0008\n27.6.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792\n27.6.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792\n27.6.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793\n27.6.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795\n27.6.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796\n27.6.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 798\n27.6.8 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799\nUSB on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . . . . . . . . . . . 800\n28.1 OTG_FS introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800\n28.2 OTG_FS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n28.3\n28.4\n28.5\n28.6\n28.7\n28.2.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801\n28.2.2 Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802\n28.2.3 Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802\nOTG_FS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\n28.3.1 OTG full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\n28.3.2 Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\nOTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\n28.4.1 ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n28.4.2 HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\n28.4.3 SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805\nUSB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806\n28.5.1 SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806\n28.5.2 Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807\n28.5.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808\nUSB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810\n28.6.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811\n28.6.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811\n28.6.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812\n28.6.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814\nSOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815\n28.7.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815\n28.7.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815\n28.8 Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816\n28.9 Dynamic update of the OTG_FS_HFIR register . . . . . . . . . . . . . . . . . . . 817\n28.10 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\n22/1096\nDoc ID 13902 Rev 14 RM0008\nContents\n28.11 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818\n28.11.1 Peripheral Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818\n28.11.2 Peripheral Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n28.12 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n28.12.1 Host Rx FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819\n28.12.2 Host Tx FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\n28.13 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\n28.13.1 Device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820\n28.13.2 Host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\n28.14 USB system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821\n28.15 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822\n28.16 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 824\n28.16.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825\n28.16.2 OTG_FS global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829\n28.16.3 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850\n28.16.4 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861\n28.16.5 OTG_FS power and clock gating control register\n(OTG_FS_PCGCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883\n28.16.6 OTG_FS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884\n28.17 OTG_FS programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890\n28.17.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890\n28.17.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\n28.17.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892\n28.17.4 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893\n28.17.5 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910\n28.17.6 Operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912\n28.17.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929\n28.17.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930\n29\nEthernet (ETH): media access control (MAC) with\nDMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937\n29.1 Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937\n29.2 Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937\n29.2.1 MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938\n29.2.2 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\n29.2.3 PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939\nDoc ID 13902 Rev 14\n23/1096 Contents\nRM0008\n29.3 Ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940\n29.4 Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . . 941\n29.5\n29.6\n30\nStation management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . . 941\n29.4.2 Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944\n29.4.3 Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . . 947\n29.4.4 MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948\nEthernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . . 949\n29.5.1 MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949\n29.5.2 MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953\n29.5.3 MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960\n29.5.4 MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965\n29.5.5 MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965\n29.5.6 MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n29.5.7 MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\n29.5.8 Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969\n29.5.9 Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . . 972\nEthernet functional description: DMA controller operation . . . . . . . . . . . 978\n29.6.1 Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 979\n29.6.2 Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979\n29.6.3 Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\n29.6.4 Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980\n29.6.5 DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981\n29.6.6 Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981\n29.6.7 Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981\n29.6.8 Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990\n29.6.9 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999\n29.7 Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\n29.8 Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001\n29.8.1 MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001\n29.8.2 MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018\n29.8.3 IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022\n29.8.4 DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027\n29.8.5 Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\nDevice electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044\n30.1\n24/1096\n29.4.1\nMemory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044\nDoc ID 13902 Rev 14 RM0008\nContents\n30.1.1\n30.2\n31\nFlash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1044\nUnique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045\nDebug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047\n31.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047\n31.2 Reference ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049\n31.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1049\n31.3.1\n31.4\nMechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1049\nPinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050\n31.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\n31.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\n31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1052\n31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . 1053\n31.5 STM32F10xxx JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . 1053\n31.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054\n31.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054\n31.6.2 Boundary scan TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055\n31.6.3 Cortex™-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\n31.6.4 Cortex™-M3 JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\n31.7 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\n31.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.9\n31.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\n31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1059\n31.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\n31.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\n31.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\nAHB-AP (AHB access port) - valid for both JTAG-DP\nand SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\n31.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\n31.11 Capability of the debugger host to connect under system reset . . . . . 1062\n31.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063\n31.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064\n31.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1064\n31.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064\n31.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1064\nDoc ID 13902 Rev 14\n25/1096 Contents\nRM0008\n31.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066\n31.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066\n31.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066\n31.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\n31.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\n31.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\n31.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1067\n31.16.2 Debug support for timers, watchdog, bxCAN and I 2 C . . . . . . . . . . . . 1068\n31.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068\n31.17 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070\n31.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070\n31.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\n31.17.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073\n31.17.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1073\n31.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1073\n31.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074\n31.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074\n31.17.8 TRACECLKIN connection inside the STM32F10xxx . . . . . . . . . . . . . 1074\n31.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075\n31.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076\n31.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076\n32\n26/1096\nRevision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nDoc ID 13902 Rev 14 RM0008\nList of tables\nList of tables\nTable 1.\nTable 2.\nTable 3.\nTable 4.\nTable 5.\nTable 6.\nTable 7.\nTable 8.\nTable 9.\nTable 10.\nTable 11.\nTable 12.\nTable 13.\nTable 14.\nTable 15.\nTable 16.\nTable 17.\nTable 18.\nTable 19.\nTable 20.\nTable 21.\nTable 22.\nTable 23.\nTable 24.\nTable 25.\nTable 26.\nTable 27.\nTable 28.\nTable 29.\nTable 30.\nTable 31.\nTable 32.\nTable 33.\nTable 34.\nTable 35.\nTable 36.\nTable 37.\nTable 38.\nTable 39.\nTable 40.\nTable 41.\nTable 42.\nTable 43.\nTable 44.\nTable 45.\nTable 46.\nTable 47.\nTable 48.\nSections related to each STM32F10xxx product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40\nSections related to each peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43\nRegister boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50\nFlash module organization (low-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54\nFlash module organization (medium-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55\nFlash module organization (high-density devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56\nFlash module organization (connectivity line devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\nXL-density Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57\nBoot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60\nCRC calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64\nLow-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70\nSleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72\nSleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72\nStop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73\nStandby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74\nPWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78\nBKP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83\nRCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119\nRCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152\nPort bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\nOutput MODE bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156\nAdvanced timers TIM1/TIM8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161\nGeneral-purpose timers TIM2/3/4/5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161\nUSARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161\nSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162\nI2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162\nI2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\nBxCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\nUSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\nOTG_FS pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163\nSDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164\nFSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164\nOther IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165\nCAN1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\nCAN2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\nDebug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171\nDebug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172\nADC1 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 172\nADC1 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 172\nADC2 external trigger injected conversion alternate function remapping . . . . . . . . . . . . . 172\nADC2 external trigger regular conversion alternate function remapping . . . . . . . . . . . . . 173\nTIM5 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173\nTIM4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173\nTIM3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173\nTIM2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174\nTIM1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174\nTIM9 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174\nTIM10 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174\nDoc ID 13902 Rev 14\n27/1096 List of tables\nTable 49.\nTable 50.\nTable 51.\nTable 52.\nTable 53.\nTable 54.\nTable 55.\nTable 56.\nTable 57.\nTable 58.\nTable 59.\nTable 60.\nTable 61.\nTable 62.\nTable 63.\nTable 64.\nTable 65.\nTable 66.\nTable 67.\nTable 68.\nTable 69.\nTable 70.\nTable 71.\nTable 72.\nTable 73.\nTable 74.\nTable 75.\nTable 76.\nTable 77.\nTable 78.\nTable 79.\nTable 80.\nTable 81.\nTable 82.\nTable 83.\nTable 84.\nTable 85.\nTable 86.\nTable 87.\nTable 88.\nTable 89.\nTable 90.\nTable 91.\nTable 92.\nTable 93.\nTable 94.\nTable 95.\nTable 96.\nTable 97.\nTable 98.\nTable 99.\n28/1096\nRM0008\nTIM11 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175\nTIM13 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175\nTIM14 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175\nUSART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175\nUSART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175\nUSART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\nI2C1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\nSPI1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\nSPI3/I2S3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176\nETH remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177\nGPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188\nAFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188\nVector table for connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190\nVector table for XL-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193\nVector table for other STM32F10xxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196\nExternal interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 205\nADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209\nAnalog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\nExternal trigger for regular channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . . 216\nExternal trigger for injected channels for ADC1 and ADC2 . . . . . . . . . . . . . . . . . . . . . . . 217\nExternal trigger for regular channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217\nExternal trigger for injected channels for ADC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217\nADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227\nADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243\nDAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246\nExternal triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249\nDAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264\nProgrammable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 270\nDMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271\nSummary of DMA1 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273\nSummary of DMA2 requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274\nDMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315\nTIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329\nOutput control bits for complementary OCx and OCxN channels with\nbreak feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340\nTIM1&TIM8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348\nCounting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377\nTIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402\nTIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407\nTIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439\nTIM9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440\nOutput control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447\nTIM10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449\nTIM6&TIM7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462\nRTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474\nMin/max IWDG timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\nIWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479\nMin-max timeout value @36 MHz (f PCLK1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483\nWWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486\nDoc ID 13902 Rev 14 RM0008\nTable 100.\nTable 101.\nTable 102.\nTable 103.\nTable 104.\nTable 105.\nTable 106.\nTable 107.\nTable 108.\nTable 109.\nTable 110.\nTable 111.\nTable 112.\nTable 113.\nTable 114.\nTable 115.\nTable 116.\nTable 117.\nTable 118.\nTable 119.\nTable 120.\nTable 121.\nTable 122.\nTable 123.\nTable 124.\nTable 125.\nTable 126.\nTable 127.\nTable 128.\nTable 129.\nTable 130.\nTable 131.\nTable 132.\nTable 133.\nTable 134.\nTable 135.\nTable 136.\nTable 137.\nTable 138.\nTable 139.\nTable 140.\nTable 141.\nTable 142.\nTable 143.\nTable 144.\nTable 145.\nTable 146.\nTable 147.\nTable 148.\nTable 149.\nTable 150.\nTable 151.\nList of tables\nNOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491\nExternal memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492\nMemory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492\nNAND bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492\nProgrammable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493\nNonmultipled I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nMultiplexed I/O NOR Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494\nNonmultiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495\nNOR Flash/PSRAM supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 496\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\nFSMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516\nFSMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518\nFSMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518\nProgrammable NAND/PC Card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525\n8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525\n16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526\n16-bit PC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526\nSupported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527\n16-bit PC-Card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531\nECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538\nFSMC register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539\nSDIO I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545\nCommand format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549\nShort response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550\nLong response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550\nCommand path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550\nData token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553\nTransmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554\nReceive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555\nCard status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565\nSD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567\nSpeed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569\nPerformance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569\nAU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569\nMaximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\nErase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\nDoc ID 13902 Rev 14\n29/1096 List of tables\nTable 152.\nTable 153.\nTable 154.\nTable 155.\nTable 156.\nTable 157.\nTable 158.\nTable 159.\nTable 160.\nTable 161.\nTable 162.\nTable 163.\nTable 164.\nTable 165.\nTable 166.\nTable 167.\nTable 168.\nTable 169.\nTable 170.\nTable 171.\nTable 172.\nTable 173.\nTable 174.\nTable 175.\nTable 176.\nTable 177.\nTable 178.\nTable 179.\nTable 180.\nTable 181.\nTable 182.\nTable 183.\nTable 184.\nTable 185.\nTable 186.\nTable 187.\nTable 188.\nTable 189.\nTable 190.\nTable 191.\nTable 192.\nTable 193.\nTable 194.\nTable 195.\nTable 196.\nTable 197.\nTable 198.\nTable 199.\nTable 200.\n30/1096\nRM0008\nErase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570\nErase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571\nBlock-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573\nBlock-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574\nErase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574\nI/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574\nLock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575\nApplication-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575\nR1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\nR2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576\nR3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\nR4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\nR4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577\nR5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\nR6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578\nResponse type and SDIO_RESPx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585\nSDIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595\nDouble-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607\nBulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608\nIsochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609\nResume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611\nReception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nEndpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nEndpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nTransmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622\nDefinition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626\nUSB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626\nTransmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643\nReceive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643\nbxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669\nSPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694\nAudio-frequency precision using standard 8 MHz HSE (high-density and XL-density\ndevices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705\nAudio-frequency precision using standard 25 MHz and PLL3\n(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706\nAudio-frequency precision using standard 14.7456 MHz and PLL3\n(connectivity line devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707\nI 2 S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713\nSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722\nSMBus vs. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738\nI2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742\nI2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756\nNoise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769\nError calculation for programmed baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771\nUSART receiver’s tolerance when DIV_Fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772\nUSART receiver’s tolerance when DIV_Fraction is different from 0 . . . . . . . . . . . . . . . . . 772\nFrame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\nUSART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788\nUSART mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789\nUSART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799\nCore global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825\nHost-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826\nDoc ID 13902 Rev 14 RM0008\nTable 201.\nTable 202.\nTable 203.\nTable 204.\nTable 205.\nTable 206.\nTable 207.\nTable 208.\nTable 209.\nTable 210.\nTable 211.\nTable 212.\nTable 213.\nTable 214.\nTable 215.\nTable 216.\nTable 217.\nTable 218.\nTable 219.\nTable 220.\nTable 221.\nTable 222.\nTable 223.\nTable 224.\nTable 225.\nTable 226.\nTable 227.\nTable 228.\nTable 229.\nTable 230.\nTable 231.\nTable 232.\nTable 233.\nList of tables\nDevice-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827\nData FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829\nPower and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829\nMinimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863\nOTG_FS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884\nEthernet pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940\nManagement frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\nClock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944\nTX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946\nRX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946\nFrame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962\nDestination address filtering table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967\nSource address filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968\nReceive descriptor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996\nEthernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040\nSWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051\nFlexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052\nJTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056\n32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1057\nPacket request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058\nACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\nDATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059\nSW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060\nCortex™-M3 AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061\nCore debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062\nMain ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065\nMain ETM registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067\nAsynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\nSynchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\nFlexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072\nImportant TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075\nDBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076\nDocument revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077\nDoc ID 13902 Rev 14\n31/1096 List of figures\nRM0008\nList of figures\nFigure 1.\nFigure 2.\nFigure 3.\nFigure 4.\nFigure 5.\nFigure 6.\nFigure 7.\nFigure 8.\nFigure 9.\nFigure 10.\nFigure 11.\nFigure 12.\nFigure 13.\nFigure 14.\nFigure 15.\nFigure 16.\nFigure 17.\nFigure 18.\nFigure 19.\nFigure 20.\nFigure 21.\nFigure 22.\nFigure 23.\nFigure 24.\nFigure 25.\nFigure 26.\nFigure 27.\nFigure 28.\nFigure 29.\nFigure 30.\nFigure 31.\nFigure 32.\nFigure 33.\nFigure 34.\nFigure 35.\nFigure 36.\nFigure 37.\nFigure 38.\nFigure 39.\nFigure 40.\nFigure 41.\nFigure 42.\nFigure 43.\nFigure 44.\nFigure 45.\nFigure 46.\nFigure 47.\nFigure 48.\n32/1096\nSystem architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47\nSystem architecture in connectivity line devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48\nCRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62\nPower supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66\nPower on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68\nPVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69\nSimplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90\nHSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91\nSimplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121\nClock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123\nHSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125\nBasic structure of a standard I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155\nBasic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155\nInput floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158\nOutput configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159\nAlternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160\nHigh impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161\nADC / DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164\nExternal interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199\nExternal interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201\nSingle ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208\nTiming diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211\nAnalog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212\nInjected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213\nCalibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\nRight alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\nLeft alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215\nDual ADC block diagram (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220\nInjected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221\nRegular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222\nFast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 222\nSlow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223\nAlternate trigger: injected channel group of each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . 223\nAlternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 224\nAlternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225\nCase of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225\nInterleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 225\nTemperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 226\nDAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246\nData registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248\nData registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248\nTiming diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 249\nDAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250\nDAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 251\nDAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251\nDAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 252\nDMA block diagram in connectivity line devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266\nDoc ID 13902 Rev 14 RM0008\nFigure 49.\nFigure 50.\nFigure 51.\nFigure 52.\nFigure 53.\nFigure 54.\nFigure 55.\nFigure 56.\nFigure 57.\nFigure 58.\nFigure 59.\nFigure 60.\nFigure 61.\nFigure 62.\nFigure 63.\nFigure 64.\nFigure 65.\nFigure 66.\nFigure 67.\nFigure 68.\nFigure 69.\nFigure 70.\nFigure 71.\nFigure 72.\nFigure 73.\nFigure 74.\nFigure 75.\nFigure 76.\nFigure 77.\nFigure 78.\nFigure 79.\nFigure 80.\nFigure 81.\nFigure 82.\nFigure 83.\nFigure 84.\nFigure 85.\nFigure 86.\nFigure 87.\nFigure 88.\nFigure 89.\nFigure 90.\nFigure 91.\nFigure 92.\nFigure 93.\nFigure 94.\nFigure 95.\nFigure 96.\nFigure 97.\nFigure 98.\nList of figures\nDMA block diagram in low-, medium- high- and XL-density devices . . . . . . . . . . . . . . . . 267\nDMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272\nDMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274\nAdvanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 286\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 286\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288\nCounter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 288\nCounter timing diagram, update event when ARPE=1\n(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291\nCounter timing diagram, update event when repetition counter\nis not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291\nCounter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 292\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293\nCounter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 293\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293\nCounter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 294\nCounter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 294\nUpdate rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 295\nControl circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 296\nTI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296\nControl circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297\nExternal trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297\nControl circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298\nCapture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 299\nCapture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299\nOutput stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 300\nOutput stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 300\nPWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302\nOutput compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304\nEdge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305\nCenter-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306\nComplementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307\nDead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 307\nDead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 308\nOutput behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310\nClearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311\n6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312\nExample of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313\nExample of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 316\nExample of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 316\nExample of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318\nControl circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319\nControl circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320\nControl circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321\nDoc ID 13902 Rev 14\n33/1096 List of figures\nFigure 99.\nFigure 100.\nFigure 101.\nFigure 102.\nFigure 103.\nFigure 104.\nFigure 105.\nFigure 106.\nFigure 107.\nFigure 108.\nFigure 109.\nFigure 110.\nFigure 111.\nFigure 112.\nFigure 113.\nFigure 114.\nFigure 115.\nFigure 116.\nFigure 117.\nFigure 118.\nFigure 119.\nFigure 120.\nFigure 121.\nFigure 122.\nFigure 123.\nFigure 124.\nFigure 125.\nFigure 126.\nFigure 127.\nFigure 128.\nFigure 129.\nFigure 130.\nFigure 131.\nFigure 132.\nFigure 133.\nFigure 134.\nFigure 135.\nFigure 136.\nFigure 137.\nFigure 138.\nFigure 139.\nFigure 140.\nFigure 141.\nFigure 142.\nFigure 143.\nFigure 144.\nFigure 145.\nFigure 146.\nFigure 147.\nFigure 148.\nFigure 149.\n34/1096\nRM0008\nControl circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 322\nGeneral-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 353\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 354\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356\nCounter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 356\nCounter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 357\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359\nCounter timing diagram, Update event when repetition counter\nis not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359\nCounter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 360\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361\nCounter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 361\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361\nCounter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 362\nCounter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 362\nControl circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 363\nTI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364\nControl circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364\nExternal trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365\nControl circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365\nCapture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 366\nCapture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366\nOutput stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 367\nPWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369\nOutput compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371\nEdge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372\nCenter-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373\nExample of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374\nClearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376\nExample of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 377\nExample of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 378\nControl circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379\nControl circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380\nControl circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380\nControl circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 381\nMaster/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382\nGating timer 2 with OC1REF of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383\nGating timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384\nTriggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385\nTriggering timer 2 with Enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385\nTriggering timer 1 and 2 with timer 1 TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387\nGeneral-purpose timer block diagram (TIM9 and TIM12) . . . . . . . . . . . . . . . . . . . . . . . . 411\nGeneral-purpose timer block diagram (TIM10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . 412\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 414\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 414\nDoc ID 13902 Rev 14 RM0008\nFigure 150.\nFigure 151.\nFigure 152.\nFigure 153.\nFigure 154.\nFigure 155.\nFigure 156.\nFigure 157.\nFigure 158.\nFigure 159.\nFigure 160.\nFigure 161.\nFigure 162.\nFigure 163.\nFigure 164.\nFigure 165.\nFigure 166.\nFigure 167.\nFigure 168.\nFigure 169.\nFigure 170.\nFigure 171.\nFigure 172.\nFigure 173.\nFigure 174.\nFigure 175.\nFigure 176.\nFigure 177.\nFigure 178.\nFigure 179.\nFigure 180.\nFigure 181.\nFigure 182.\nFigure 183.\nFigure 184.\nFigure 185.\nFigure 186.\nFigure 187.\nFigure 188.\nFigure 189.\nFigure 190.\nFigure 191.\nFigure 192.\nFigure 193.\nFigure 194.\nFigure 195.\nFigure 196.\nFigure 197.\nList of figures\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416\nCounter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416\nCounter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417\nControl circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 418\nTI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418\nControl circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419\nCapture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 419\nCapture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420\nOutput stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 420\nPWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422\nOutput compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424\nEdge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425\nExample of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425\nControl circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427\nControl circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428\nControl circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428\nBasic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452\nCounter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 453\nCounter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 453\nCounter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454\nCounter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nCounter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nCounter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455\nCounter timing diagram, update event when ARPE = 0 (TIMx_ARR not\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nCounter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456\nControl circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 457\nRTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465\nRTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 467\nRTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467\nIndependent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476\nWatchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481\nWindow watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482\nFSMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489\nFSMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491\nMode1 read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498\nMode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498\nModeA read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500\nModeA write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500\nMode2/B read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502\nMode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503\nModeB write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503\nModeC read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505\nModeC write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505\nModeD read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507\nMultiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\nDoc ID 13902 Rev 14\n35/1096 List of figures\nFigure 198.\nFigure 199.\nFigure 200.\nFigure 201.\nFigure 202.\nFigure 203.\nFigure 204.\nFigure 205.\nFigure 206.\nFigure 207.\nFigure 208.\nFigure 209.\nFigure 210.\nFigure 211.\nFigure 212.\nFigure 213.\nFigure 214.\nFigure 215.\nFigure 216.\nFigure 217.\nFigure 218.\nFigure 219.\nFigure 220.\nFigure 221.\nFigure 222.\nFigure 223.\nFigure 224.\nFigure 225.\nFigure 226.\nFigure 227.\nFigure 228.\nFigure 229.\nFigure 230.\nFigure 231.\nFigure 232.\nFigure 233.\nFigure 234.\nFigure 235.\nFigure 236.\nFigure 237.\nFigure 238.\nFigure 239.\nFigure 240.\nFigure 241.\nFigure 242.\nFigure 243.\nFigure 244.\n36/1096\nRM0008\nMultiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509\nAsynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511\nAsynchronous wait during a write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512\nWait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514\nSynchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . 515\nSynchronous multiplexed write mode - PSRAM (CRAM) . . . . . . . . . . . . . . . . . . . . . . . . . 517\nNAND/PC Card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 528\nAccess to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529\nSDIO “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\nSDIO (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542\nSDIO (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543\nSDIO sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543\nSDIO sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543\nSDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544\nSDIO adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545\nControl unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546\nSDIO adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547\nCommand path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548\nSDIO command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549\nData path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551\nData path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552\nUSB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598\nPacket buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 602\nCAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629\nDual CAN block diagram (connectivity devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631\nbxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633\nbxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634\nbxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634\nbxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635\nTransmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636\nReceive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637\nFilter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 640\nExample of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641\nFiltering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642\nCAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643\nBit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645\nCAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646\nEvent flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647\nSPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675\nSingle master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676\nData clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678\nTXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0)\nin the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684\nTXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the\ncase of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684\nTXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in the\ncase of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685\nTXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of\ncontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686\nRXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of\ncontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687\nTXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of\nDoc ID 13902 Rev 14 RM0008\nFigure 245.\nFigure 246.\nFigure 247.\nFigure 248.\nFigure 249.\nFigure 250.\nFigure 251.\nFigure 252.\nFigure 253.\nFigure 254.\nFigure 255.\nFigure 256.\nFigure 257.\nFigure 258.\nFigure 259.\nFigure 260.\nFigure 261.\nFigure 262.\nFigure 263.\nFigure 264.\nFigure 265.\nFigure 266.\nFigure 267.\nFigure 268.\nFigure 269.\nFigure 270.\nFigure 271.\nFigure 272.\nFigure 273.\nFigure 274.\nFigure 275.\nFigure 276.\nFigure 277.\nFigure 278.\nFigure 279.\nFigure 280.\nFigure 281.\nFigure 282.\nFigure 283.\nFigure 284.\nFigure 285.\nFigure 286.\nFigure 287.\nFigure 288.\nFigure 289.\nFigure 290.\nFigure 291.\nFigure 292.\nFigure 293.\nFigure 294.\nFigure 295.\nList of figures\ndiscontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688\nTransmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692\nReception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693\nI 2 S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695\nI 2 S Phillips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . . . . . . . . . . . . 697\nI 2 S Phillips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . 697\nTransmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698\nReceiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698\nI 2 S Phillips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 698\nExample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699\nMSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 699\nMSB Justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700\nMSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . 700\nLSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 700\nLSB Justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701\nOperations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701\nOperations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701\nLSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 702\nExample of LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . 702\nPCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703\nPCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 703\nAudio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nI 2 S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704\nI2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725\nI2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726\nTransfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727\nTransfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728\nTransfer sequence diagram for master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731\nMethod 1: transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . 733\nMethod 2: transfer sequence diagram for master receiver when N>2 . . . . . . . . . . . . . . . 734\nMethod 2: transfer sequence diagram for master receiver when N=2 . . . . . . . . . . . . . . . 735\nMethod 2: transfer sequence diagram for master receiver when N=1 . . . . . . . . . . . . . . . 736\nI2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743\nUSART block diagram\n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761\nWord length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762\nConfigurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764\nTC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765\nStart bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766\nData sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768\nMute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773\nMute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774\nBreak detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 776\nBreak detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 777\nUSART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\nUSART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778\nUSART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779\nRX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779\nISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780\nParity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782\nIrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784\nIrDA data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784\nTransmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785\nDoc ID 13902 Rev 14\n37/1096 List of figures\nFigure 296.\nFigure 297.\nFigure 298.\nFigure 299.\nFigure 300.\nFigure 301.\nFigure 302.\nFigure 303.\nFigure 304.\nFigure 305.\nFigure 306.\nFigure 307.\nFigure 308.\nFigure 309.\nFigure 310.\nFigure 311.\nFigure 312.\nFigure 313.\nFigure 314.\nFigure 315.\nFigure 316.\nFigure 317.\nFigure 318.\nFigure 319.\nFigure 320.\nFigure 321.\nFigure 322.\nFigure 323.\nFigure 324.\nFigure 325.\nFigure 326.\nFigure 327.\nFigure 328.\nFigure 329.\nFigure 330.\nFigure 331.\nFigure 332.\nFigure 333.\nFigure 334.\nFigure 335.\nFigure 336.\nFigure 337.\nFigure 338.\nFigure 339.\nFigure 340.\nFigure 341.\nFigure 342.\nFigure 343.\nFigure 344.\nFigure 345.\nFigure 346.\nFigure 347.\n38/1096\nRM0008\nReception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786\nHardware flow control between two USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787\nRTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787\nCTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788\nUSART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789\nBlock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803\nOTG A-B device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804\nUSB peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806\nUSB host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811\nSOF connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815\nUpdating OTG_FS_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817\nDevice-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . 818\nHost-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . . 819\nInterrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823\nCSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825\nTransmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894\nReceive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895\nNormal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . . . . . . . . . . . . . 897\nBulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900\nNormal interrupt OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902\nNormal isochronous OUT/IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907\nReceive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913\nProcessing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915\nBulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921\nTRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930\nA-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931\nB-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932\nA-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 933\nB-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935\nETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941\nSMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942\nMDIO timing and frame structure - Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943\nMDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944\nMedia independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945\nMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\nReduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947\nRMII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948\nClock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948\nAddress field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950\nMAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952\nTagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952\nTransmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958\nTransmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959\nTransmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959\nFrame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960\nReceive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964\nReception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964\nReception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964\nReception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965\nMAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965\nWakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970\nNetworked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973\nDoc ID 13902 Rev 14 RM0008\nFigure 348.\nFigure 349.\nFigure 350.\nFigure 351.\nFigure 352.\nFigure 353.\nFigure 354.\nFigure 355.\nFigure 356.\nFigure 357.\nFigure 358.\nFigure 359.\nFigure 360.\nFigure 361.\nFigure 362.\nList of figures\nSystem time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 975\nPTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977\nPPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978\nDescriptor ring and chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979\nTxDMA operation in Default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983\nTxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985\nransmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986\nReceive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992\nRx DMA descriptor structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994\nInterrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000\nEthernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . 1010\nBlock diagram of STM32 MCU and Cortex™-M3-level debug support . . . . . . . . . . . . . 1048\nSWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049\nJTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054\nTPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071\nDoc ID 13902 Rev 14\n39/1096 Overview of the manual\n1\nRM0008\nOverview of the manual\nLegend for Table 1:\nThe section in each row applies to products in columns marked with “ • \"\nSTM32F101xx XL-density Low-density\nSections related to each STM32F10xxx product\nTable 1.\nSection 2:\nDocumentation\nconventions • • • • • • • • • •\nSection 3: Memory and\nbus architecture • • • • • • • • • •\nSection 4: CRC\ncalculation unit • • • • • • • • • •\nSection 5: Power\ncontrol (PWR) • • • • • • • • • •\nSection 6: Backup\nregisters (BKP) • • • • • • • • • •\nSection 7: Low-,\nmedium-, high- and XL-\ndensity reset and clock\ncontrol (RCC) • • • • • • • • • •\nSection 8: Connectivity\nline devices: reset and\nclock control (RCC)\nSection 9: General-\npurpose and alternate-\nfunction I/Os (GPIOs\nand AFIOs) • • • • • • • • • •\nSection 10: Interrupts\nand events • • • • • • • • • •\nSection 13: Direct\nmemory access\ncontroller (DMA) • • • • • • • • • •\n40/1096\nDoc ID 13902 Rev 14 RM0008\nSection 11: Analog-to-\ndigital converter (ADC)\nMedium-density\nSections related to each STM32F10xxx product (continued)\nLow-density\nTable 1.\nOverview of the manual\n• • • • • • • • • •\n•\nSection 12: Digital-to-\nanalog converter (DAC)\nSection 14: Advanced-\ncontrol timers\n(TIM1&TIM8)\nSection 15: General-\npurpose timers (TIM2 to\nTIM5)\n•\n•\n•\nSection 16: General-\npurpose timers (TIM9 to\nTIM14)\nSection 17: Basic\ntimers (TIM6&TIM7)\n•\n•\n•\n• • •\n• • • • •\n• • • • •\n• (1) • (1) • • • •\nSection 18: Real-time\nclock (RTC) • • • • • • • • • •\nSection 19:\nIndependent watchdog\n(IWDG) • • • • • • • • • •\nSection 20: Window\nwatchdog (WWDG) • • • • • • • • • •\n• •\nSection 21: Flexible\nstatic memory\ncontroller (FSMC) • •\nSection 26: Secure\ndigital input/output\ninterface (SDIO) • •\nSection 23: Universal\nserial bus full-speed\ndevice interface (USB)\n•\n•\nSection 24: Controller\narea network (bxCAN)\nDoc ID 13902 Rev 14\n• • •\n• • •\n41/1096 Overview of the manual\nMedium-density\nSections related to each STM32F10xxx product (continued)\nLow-density\nTable 1.\nRM0008\nSection 25: Serial\nperipheral interface\n(SPI) • • • • • • • • • •\nSection 26: Inter-\nintegrated circuit (I2C)\ninterface • • • • • • • • • •\nSection 27: Universal\nsynchronous\nasynchronous receiver\ntransmitter (USART) • • • • • • • • • •\n• •\nSection 28: USB on-\nthe-go full-speed\n(OTG_FS)\nSection 29: Ethernet\n(ETH): media access\ncontrol (MAC) with\nDMA controller\n•\nSection 30: Device\nelectronic signature •\nSection 31: Debug\nsupport (DBG) •\nNote:\n42/1096\n•\n•\n•\n•\n•\n•\n•\n•\n1) Available only on XL-density devices\nDoc ID 13902 Rev 14\n•\n•\n•\n•\n•\n•\n•\n•\n•\n• RM0008\nOverview of the manual\nLegend for Table 2:\nThe section in this row must be read when using the peripherals in columns\nmarked with “ • \"\n◊ The section in this row can optionally be read when using the peripherals in\ncolumns marked with “ ◊ \"\n(DAC) (TIM1&TIM8) timers timers Real-time Independent • • • • • • • • • • • • • • • • • • • •\nSection 3: Memory and\nbus architecture • • • • • • • • • • • • • • • • • • • •\nSection 5: Power\ncontrol (PWR) • • • • • • • • • • • • • • • • • • • •\nSection 6: Backup\nregisters (BKP) • Section 7: Low-,\nmedium-, high- and XL-\ndensity reset and clock\ncontrol (RCC) • • • • • • • • • • • • • • • • • • • •\nSection 8: Connectivity\nline devices: reset and\nclock control (RCC) • • • • • • • • • • • • • • • • • • • •\nSection 9: General-\npurpose and alternate-\nfunction I/Os (GPIOs\nand AFIOs) ◊ • • • • • • ◊ • • • • • • • • • • •\nSection 2:\nDocumentation\nconventions\n(TIM2\nSections related to each peripheral\nTable 2.\n•\nSection 4: CRC\ncalculation unit\nSection 10: Interrupts\nand events\n◊\n◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊\nDoc ID 13902 Rev 14\n◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊\n43/1096 Overview of the manual\nSection 13: Direct\nmemory access\ncontroller (DMA) ◊ ◊ ◊ ◊\nSection 11: Analog-to-\ndigital converter (ADC) •\nSection 12: Digital-to-\nanalog converter (DAC) •\nSection 14: Advanced-\ncontrol timers\n(TIM1&TIM8) ◊ ◊\nSection 15: General-\npurpose timers (TIM2 to\nTIM5) ◊ ◊\nSection 16: General-\npurpose timers (TIM9 to\nTIM14)\nSection 19:\nIndependent watchdog\n(IWDG)\n•\n•\n◊\n•\n•\n•\n•\n•\nSection 21: Flexible\nstatic memory\ncontroller (FSMC)\n•\nSection 26: Secure\ndigital input/output\ninterface (SDIO)\n•\nDoc ID 13902 Rev 14\n◊ ◊ ◊\n◊ ◊\nSection 20: Window\nwatchdog (WWDG)\n44/1096\n◊ ◊\n•\nSection 17: Basic\ntimers (TIM6&TIM7)\nSection 18: Real-time\nclock (RTC)\nGeneral-purpose\nAdvanced-control\nDigital-to-analog\nAnalog-to-digital\nGeneral-purpose\nSections related to each peripheral\nregisters\nTable 2.\nRM0008 RM0008\nSection 23: Universal\nserial bus full-speed\ndevice interface (USB)\nGeneral-purpose\nAdvanced-control\nDigital-to-analog\nAnalog-to-digital\nGeneral-purpose\nSections related to each peripheral\nregisters\nTable 2.\nOverview of the manual\n•\nSection 24: Controller\narea network (bxCAN)\n•\nSection 25: Serial\nperipheral interface\n(SPI)\n•\nSection 26: Inter-\nintegrated circuit (I2C)\ninterface\n•\nSection 27: Universal\nsynchronous\nasynchronous receiver\ntransmitter (USART)\n•\nSection 28: USB on-\nthe-go full-speed\n(OTG_FS)\n•\nSection 29: Ethernet\n(ETH): media access\ncontrol (MAC) with\nDMA controller\n•\nSection 30: Device\nelectronic signature\nSection 31: Debug\nsupport (DBG)\n◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊ ◊\nDoc ID 13902 Rev 14\n45/1096 Documentation conventions\nRM0008\n2 Documentation conventions\n2.1 List of abbreviations for registers\nThe following abbreviations are used in register descriptions:\nread/write (rw) Software can read and write to these bits.\nread-only (r) Software can only read these bits.\nwrite-only (w) Software can only write to this bit. Reading the bit returns the reset value.\nread/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on\nthe bit value.\nread/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on\nthe bit value.\nread/clear by read\n(rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’\nhas no effect on the bit value.\nread/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.\nread-only write\ntrigger (rt_w) Software can read this bit. Writing ‘0’ or ‘1’ triggers an event but has no effect on\nthe bit value.\ntoggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.\nReserved (Res.) Reserved bit, must be kept at reset value.\n2.2\n2.3\nGlossary\n● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\n● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\n● High-density devices are STM32F101xx and STM32F103xx microcontrollers where\nthe Flash memory density ranges between 256 and 512 Kbytes.\n● XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\n● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\n● Word: data of 32-bit length.\n● Half-word: data of 16-bit length.\n● Byte: data of 8-bit length.\nPeripheral availability\nFor peripheral availability and number across all STM32F10xxx sales types, please refer to\nthe low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to\nthe low- and medium-density STM32F102xx datasheets and to the connectivity line devices,\nSTM32F105xx/STM32F107xx.\n46/1096\nDoc ID 13902 Rev 14 RM0008\nMemory and bus architecture\n3 Memory and bus architecture\n3.1 System architecture\nIn low-, medium-, high- and XL-density devices, the main system consists of:\n●\n●\nFour masters:\n– Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)\n– GP-DMA1 & 2 (general-purpose DMA)\nFour slaves:\n–\nInternal SRAM\n– Internal Flash memory\n– FSMC\n– AHB to APBx (APB1 or APB2), which connect all the APB peripherals\nThese are interconnected using a multilayer AHB bus architecture as shown in Figure 1:\nFigure 1.\nSystem architecture\nICode\nFlash\nFLITF\nDCode\nCortex-M3\nDMA1\nDMA\nSys tem\nSRAM\nFSMC\nSDIO\nCh.1\nAHB system bus\nCh.2\nBridge 2\nCh.7\nBridge 1\nReset & clock\ncontrol (RCC)\nDMA Request\nDMA2\nAPB2\nGPIOC\nADC1\nADC2\nGPIOD\nADC3\nGPIOE\nUSART1 GPIOF\nSPI1\nGPIOG\nTIM1\nEXTI\nTIM8\nAFIO\nGPIOA\nGPIOB\nCh.1\nAPB 1\nDAC SPI3/I2S\nPWR SPI2/I2S\nIWDG\nBKP\nbxCAN WWDG\nRTC\nUSB\nTIM7\nI2C2\nTIM6\nI2C1\nTIM5\nUART5\nTIM4\nUART4\nUSART3 TIM3\nUSART2 TIM2\nCh.2\nCh.5\nDMA request\nai14800c\nDoc ID 13902 Rev 14\n47/1096 Memory and bus architecture\nRM0008\nIn connectivity line devices the main system consists of:\n●\n●\nFive masters:\n– Cortex-M3 core DCode bus (D-bus) and System bus (S-bus)\n– GP-DMA1 & 2 (general-purpose DMA)\n– Ethernet DMA\nThree slaves:\n–\nInternal SRAM\n– Internal Flash memory\n– AHB to APB bridges (AHB to APBx), which connect all the APB peripherals\nThese are interconnected using a multilayer AHB bus architecture as shown in Figure 2:\nFigure 2.\nSystem architecture in connectivity line devices\nICode\nFlash\nFLITF\nDCode\nCortex-M3\nDMA1\nDMA\nSys tem\nSRAM\nReset & clock\ncontrol (RCC)\nCh.1\nAHB system bus\nCh.2\nBridge 2\nBridge 1\nAPB2\nAPB 1\nCh.7\nADC1\nADC2\nDMA request\nCh.1\nDMA2\nUSART1\nSPI1\nTIM1\nGPIOA\nGPIOB\nGPIOC\nGPIOD\nGPIOE\nEXTI\nAFIO\nDAC SPI3/I2S\nPWR SPI2/I2S\nIWDG\nBKP\nCAN1 WWDG\nCAN2\nRTC\nI2C2\nTIM7\nI2C1\nTIM6\nUART5\nTIM5\nUART4\nTIM4\nUSART3 TIM3\nUSART2 TIM2\nCh.2\nDMA request\nCh.5\nEthernet MAC\nUSB OTG FS\nai15810\nICode bus\nThis bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory\ninstruction interface. Prefetching is performed on this bus.\n48/1096\nDoc ID 13902 Rev 14 RM0008\nMemory and bus architecture\nDCode bus\nThis bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core\nto the Flash memory Data interface.\nSystem bus\nThis bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix\nwhich manages the arbitration between the core and the DMA.\nDMA bus\nThis bus connects the AHB master interface of the DMA to the BusMatrix which manages\nthe access of CPU DCode and DMA to SRAM, Flash memory and peripherals.\nBusMatrix\nThe BusMatrix manages the access arbitration between the core system bus and the DMA\nmaster bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the\nBusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1\nand DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices,\nthe BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and\nDMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).\nAHB peripherals are connected on system bus through a BusMatrix to allow DMA access.\nAHB/APB bridges (APB)\nThe two AHB/APB bridges provide full synchronous connections between the AHB and the\n2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz\ndepending on the device).\nRefer to Table 3 on page 50 for the address mapping of the peripherals connected to each\nbridge.\nAfter each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF).\nBefore using a peripheral you have to enable its clock in the RCC_AHBENR,\nRCC_APB2ENR or RCC_APB1ENR register.\nNote: When a 16- or 8-bit access is performed on an APB register, the access is transformed into\na 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.\n3.2 Memory organization\nProgram memory, data memory, registers and I/O ports are organized within the same linear\n4-Gbyte address space.\nThe bytes are coded in memory in Little Endian format. The lowest numbered byte in a word\nis considered the word’s least significant byte and the highest numbered byte the most\nsignificant.\nFor the detailed mapping of peripheral registers, please refer to the related chapters.\nThe addressable memory space is divided into 8 main blocks, each of 512 MB.\nAll the memory areas that are not allocated to on-chip memories and peripherals are\nconsidered “Reserved”). Refer to the Memory map figure in the corresponding product\ndatasheet.\nDoc ID 13902 Rev 14\n49/1096 Memory and bus architecture\n3.3\nRM0008\nMemory map\nSee the datasheet corresponding to your device for a comprehensive diagram of the\nmemory map. Table 3 gives the boundary addresses of the peripherals available in all\nSTM32F10xxx devices.\nTable 3.\nRegister boundary addresses\nBoundary address\nPeripheral\nBus\nRegister map\n0xA000 0000 - 0xA000 0FFF FSMC Section 21.6.9 on page 539\n0x5000 0000 - 0x5003 FFFF USB OTG FS Section 28.16.6 on page 884\n0x4003 0000 - 0x4FFF FFFF Reserved 0x4002 8000 - 0x4002 9FFF Ethernet 0x4002 3400 - 0x4002 7FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2000 - 0x4002 23FF Flash memory interface 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF Reset and clock control RCC 0x4002 0800 - 0x4002 0FFF Reserved 0x4002 0400 - 0x4002 07FF DMA2 Section 13.4.7 on page 280\n0x4002 0000 - 0x4002 03FF DMA1 Section 13.4.7 on page 280\n0x4001 8400 - 0x4001 7FFF Reserved 0x4001 8000 - 0x4001 83FF SDIO\nSection 29.8.5 on page 1040\nSection 4.4.4 on page 64\nAHB\n50/1096\nSection 7.3.11 on page 119\nSection 26.9.16 on page 764\nDoc ID 13902 Rev 14 RM0008\nTable 3.\nMemory and bus architecture\nRegister boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n0x4001 5800 - 0x4001 7FFF Reserved 0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.6.11 on page 449\n0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.6.11 on page 449\n0x4001 4C00 - 0x4001 4FFF TIM9 timer Section 16.5.13 on page 440\n0x4001 4000 - 0x4001 4BFF Reserved 0x4001 3C00 - 0x4001 3FFF ADC3 Section 11.12.15 on page 243\n0x4001 3800 - 0x4001 3BFF USART1 Section 27.6.8 on page 799\n0x4001 3400 - 0x4001 37FF TIM8 timer Section 14.4.21 on page 348\n0x4001 3000 - 0x4001 33FF SPI1 Section 25.5 on page 714\n0x4001 2C00 - 0x4001 2FFF TIM1 timer Section 14.4.21 on page 348\n0x4001 2800 - 0x4001 2BFF ADC2 0x4001 2400 - 0x4001 27FF ADC1 Section 11.12.15 on page 243\n0x4001 2000 - 0x4001 23FF GPIO Port G Section 9.5 on page 188\n0x4001 1C00 - 0x4001 1FFF GPIO Port F Section 9.5 on page 188\n0x4001 1800 - 0x4001 1BFF GPIO Port E Section 9.5 on page 188\n0x4001 1400 - 0x4001 17FF GPIO Port D Section 9.5 on page 188\n0x4001 1000 - 0x4001 13FF GPIO Port C Section 9.5 on page 188\n0x4001 0C00 - 0x4001 0FFF GPIO Port B Section 9.5 on page 188\n0x4001 0800 - 0x4001 0BFF GPIO Port A Section 9.5 on page 188\n0x4001 0400 - 0x4001 07FF EXTI Section 10.3.7 on page 205\n0x4001 0000 - 0x4001 03FF AFIO Section 9.5 on page 188\nAPB2\nDoc ID 13902 Rev 14\nSection 11.12.15 on page 243\n51/1096 Memory and bus architecture\nTable 3.\nRM0008\nRegister boundary addresses (continued)\nBoundary address\nPeripheral\nBus\nRegister map\n0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF DAC Section 12.5.14 on page 264\n0x4000 7000 - 0x4000 73FF Power control PWR Section 5.4.3 on page 78\n0x4000 6C00 - 0x4000 6FFF Backup registers (BKP) Section 6.4.5 on page 83\n0x4000 6800 - 0x4000 6BFF Reserved 0x4000 6400 - 0x4000 67FF bxCAN1 Section 24.9.5 on page 669\n0x4000 6800 - 0x4000 6BFF bxCAN2 Section 24.9.5 on page 669\n(1)\n0x4000 6000\n- 0x4000 63FF Shared USB/CAN SRAM 512 bytes\n0x4000 5C00 - 0x4000 5FFF USB device FS registers Section 23.5.4 on page 626\n0x4000 5800 - 0x4000 5BFF I2C2 Section 26.6.10 on page 756\n0x4000 5400 - 0x4000 57FF I2C1 Section 26.6.10 on page 756\n0x4000 5000 - 0x4000 53FF UART5 Section 27.6.8 on page 799\n0x4000 4C00 - 0x4000 4FFF UART4 Section 27.6.8 on page 799\n0x4000 4800 - 0x4000 4BFF USART3 Section 27.6.8 on page 799\n0x4000 4400 - 0x4000 47FF USART2 Section 27.6.8 on page 799\n0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI3/I2S Section 25.5 on page 714\n0x4000 3800 - 0x4000 3BFF SPI2/I2S Section 25.5 on page 714\n0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG) Section 19.4.5 on page 479\n0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG) Section 20.6.4 on page 486\n0x4000 2800 - 0x4000 2BFF RTC Section 18.4.7 on page 474\n0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 timer Section 16.6.11 on page 449\n0x4000 1C00 - 0x4000 1FFF TIM13 timer Section 16.6.11 on page 449\n0x4000 1800 - 0x4000 1BFF TIM12 timer Section 16.5.13 on page 440\n0x4000 1400 - 0x4000 17FF TIM7 timer Section 17.4.9 on page 462\n0x4000 1000 - 0x4000 13FF TIM6 timer Section 17.4.9 on page 462\n0x4000 0C00 - 0x4000 0FFF TIM5 timer Section 15.4.19 on page 407\n0x4000 0800 - 0x4000 0BFF TIM4 timer Section 15.4.19 on page 407\n0x4000 0400 - 0x4000 07FF TIM3 timer Section 15.4.19 on page 407\n0x4000 0000 - 0x4000 03FF TIM2 timer Section 15.4.19 on page 407\nAPB1\n1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line\ndevices.\n52/1096\nDoc ID 13902 Rev 14 RM0008\n3.3.1\nMemory and bus architecture\nEmbedded SRAM\nThe STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes,\nhalf-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.\n3.3.2\nBit banding\nThe Cortex™-M3 memory map includes two bit-band regions. These regions map each\nword in an alias region of memory to a bit in a bit-band region of memory. Writing to a word\nin the alias region has the same effect as a read-modify-write operation on the targeted bit in\nthe bit-band region.\nIn the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region.\nThis allows single bit-band write and read operations to be performed. The operations are\nonly available for Cortex-M3 accesses, not from other bus masters (e.g. DMA).\nA mapping formula shows how to reference each word in the alias region to a corresponding\nbit in the bit-band region. The mapping formula is:\nbit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)\nwhere:\nbit_word_addr is the address of the word in the alias memory region that maps to the\ntargeted bit.\nbit_band_base is the starting address of the alias region\nbyte_offset is the number of the byte in the bit-band region that contains the targeted bit\nbit_number is the bit position (0-7) of the targeted bit.\nExample:\nThe following example shows how to map bit 2 of the byte located at SRAM address\n0x20000300 in the alias region:\n0x22006008 = 0x22000000 + (0x300*32) + (2*4).\nWriting to address 0x22006008 has the same effect as a read-modify-write operation on bit\n2 of the byte at SRAM address 0x20000300.\nReading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM\naddress 0x20000300 (0x01: bit set; 0x00: bit reset).\nFor more information on Bit-Banding, please refer to the Cortex™-M3 Technical Reference\nManual.\nDoc ID 13902 Rev 14\n53/1096 Memory and bus architecture\n3.3.3\nRM0008\nEmbedded Flash memory\nThe high-performance Flash memory module has the following key features:\n●\nFor XL-density devices: density of up to 1 Mbyte with dual bank architecture for read-\nwhile-write (RWW) capability:\n– bank 1: fixed size of 512 Kbytes\n– bank 2: up to 512 Kbytes\n● For other devices: density of up to 512 Kbytes\n● Memory organization: the Flash memory is organized as a main block and an\ninformation block:\n–\nMain memory block of size:\nup to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Table 8)\nfor XL-density devices\nup to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices\n(see Table 4)\nup to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density\ndevices (see Table 5)\nup to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6) for\nhigh-density devices\nup to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 7) for\nconnectivity line devices\n–\nInformation block of size:\n770 × 64 bits for XL-density devices (see Table 8)\n2360 × 64 bits for connectivity line devices (see Table 7)\n258 × 64 bits for other devices (see Table 4, Table 5 and Table 6)\nThe Flash memory interface (FLITF) features:\n● Read interface with prefetch buffer (2x64-bit words)\n● Option byte Loader\n● Flash Program / Erase operation\n● Read / Write protection\nTable 4.\nFlash module organization (low-density devices)\nBlock\nMain memory\n54/1096\nName Base addresses Size (bytes)\nPage 0 0x0800 0000 - 0x0800 03FF 1 Kbyte\nPage 1 0x0800 0400 - 0x0800 07FF 1 Kbyte\nPage 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte\nPage 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte\nPage 4 0x0800 1000 - 0x0800 13FF 1 Kbyte\n.\n.\n. .\n.\n. .\n.\n.\nPage 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte\nDoc ID 13902 Rev 14 RM0008\nMemory and bus architecture\nTable 4.\nFlash module organization (low-density devices) (continued)\nBlock\nName Base addresses Size (bytes)\nSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes\nOption Bytes 0x1FFF F800 - 0x1FFF F80F 16\nFLASH_ACR 0x4002 2000 - 0x4002 2003 4\nFLASH_KEYR 0x4002 2004 - 0x4002 2007 4\nFLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4\nFLASH_SR 0x4002 200C - 0x4002 200F 4\nFLASH_CR 0x4002 2010 - 0x4002 2013 4\nFLASH_AR 0x4002 2014 - 0x4002 2017 4\nReserved 0x4002 2018 - 0x4002 201B 4\nFLASH_OBR 0x4002 201C - 0x4002 201F 4\nFLASH_WRPR 0x4002 2020 - 0x4002 2023 4\nInformation block\nFlash memory\ninterface\nregisters\nTable 5.\nFlash module organization (medium-density devices)\nBlock\nMain memory\nName Base addresses Size (bytes)\nPage 0 0x0800 0000 - 0x0800 03FF 1 Kbyte\nPage 1 0x0800 0400 - 0x0800 07FF 1 Kbyte\nPage 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte\nPage 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte\nPage 4 0x0800 1000 - 0x0800 13FF 1 Kbyte\n.\n.\n. .\n.\n. .\n.\n.\nPage 127 0x0801 FC00 - 0x0801 FFFF 1 Kbyte\nSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes\nOption Bytes 0x1FFF F800 - 0x1FFF F80F 16\nFLASH_ACR 0x4002 2000 - 0x4002 2003 4\nFLASH_KEYR 0x4002 2004 - 0x4002 2007 4\nFLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4\nFLASH_SR 0x4002 200C - 0x4002 200F 4\nFLASH_CR 0x4002 2010 - 0x4002 2013 4\nFLASH_AR 0x4002 2014 - 0x4002 2017 4\nReserved 0x4002 2018 - 0x4002 201B 4\nFLASH_OBR 0x4002 201C - 0x4002 201F 4\nFLASH_WRPR 0x4002 2020 - 0x4002 2023 4\nInformation block\nFlash memory\ninterface\nregisters\nDoc ID 13902 Rev 14\n55/1096 Memory and bus architecture\nTable 6.\nRM0008\nFlash module organization (high-density devices)\nBlock\nMain memory\nName Base addresses Size (bytes)\nPage 0 0x0800 0000 - 0x0800 07FF 2 Kbytes\nPage 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes\nPage 2 0x0800 1000 - 0x0800 17FF 2 Kbytes\nPage 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes\n.\n.\n. .\n.\n. .\n.\n.\nPage 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes\nSystem memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes\nOption Bytes 0x1FFF F800 - 0x1FFF F80F 16\nFLASH_ACR 0x4002 2000 - 0x4002 2003 4\nFLASH_KEYR 0x4002 2004 - 0x4002 2007 4\nFLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4\nFLASH_SR 0x4002 200C - 0x4002 200F 4\nFLASH_CR 0x4002 2010 - 0x4002 2013 4\nFLASH_AR 0x4002 2014 - 0x4002 2017 4\nReserved 0x4002 2018 - 0x4002 201B 4\nFLASH_OBR 0x4002 201C - 0x4002 201F 4\nFLASH_WRPR 0x4002 2020 - 0x4002 2023 4\nInformation block\nFlash memory\ninterface\nregisters\n56/1096\nDoc ID 13902 Rev 14 RM0008\nMemory and bus architecture\nTable 7.\nFlash module organization (connectivity line devices)\nBlock\nMain memory\nName Base addresses Size (bytes)\nPage 0 0x0800 0000 - 0x0800 07FF 2 Kbytes\nPage 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes\nPage 2 0x0800 1000 - 0x0800 17FF 2 Kbytes\nPage 3 0x0800 1800 - 0x0800 1FFF 2 Kbytes\n.\n.\n. .\n.\n. .\n.\n.\nPage 127 0x0803 F800 - 0x0803 FFFF 2 Kbytes\nSystem memory 0x1FFF B000 - 0x1FFF F7FF 18 Kbytes\nOption Bytes 0x1FFF F800 - 0x1FFF F80F 16\nFLASH_ACR 0x4002 2000 - 0x4002 2003 4\nFLASH_KEYR 0x4002 2004 - 0x4002 2007 4\nFLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4\nFLASH_SR 0x4002 200C - 0x4002 200F 4\nFLASH_CR 0x4002 2010 - 0x4002 2013 4\nFLASH_AR 0x4002 2014 - 0x4002 2017 4\nReserved 0x4002 2018 - 0x4002 201B 4\nFLASH_OBR 0x4002 201C - 0x4002 201F 4\nFLASH_WRPR 0x4002 2020 - 0x4002 2023 4\nInformation block\nFlash memory\ninterface\nregisters\nTable 8.\nXL-density Flash module organization\nBlock\nName Base addresses Size (bytes)\nPage 0 0x0800 0000 - 0x0800 07FF 2 Kbytes\nPage 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes\n... ... ...\nPage 255 0x0807 F800 - 0x0807 FFFF 2 Kbytes\nPage 256 0x0808 0000 - 0x0808 07FF 2 Kbytes\nPage 257 0x0808 0800 - 0x0808 0FFF 2 Kbytes\n.\n.\n. .\n.\n. .\n.\n.\nPage 511 0x080F F800 - 0x080F FFFF 2 Kbytes\nSystem memory 0x1FFF E000 - 0x1FFF F7FF 6 Kbytes\nOption bytes 0x1FFF F800 - 0x1FFF F80F 16\nBank 1\nMain memory\nBank 2\nInformation block\nDoc ID 13902 Rev 14\n57/1096 Memory and bus architecture\nTable 8.\nRM0008\nXL-density Flash module organization (continued)\nBlock\nFlash memory interface\nregisters\nNote:\nName Base addresses Size (bytes)\nFLASH_ACR 0x4002 2000 - 0x4002 2003 4\nFLASH_KEYR 0x4002 2004 - 0x4002 2007 4\nFLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4\nFLASH_SR 0x4002 200C - 0x4002 200F 4\nFLASH_CR 0x4002 2010 - 0x4002 2013 4\nFLASH_AR 0x4002 2014 - 0x4002 2017 4\nReserved 0x4002 2018 - 0x4002 201B 4\nFLASH_OBR 0x4002 201C - 0x4002 201F 4\nFLASH_WRPR 0x4002 2020 - 0x4002 2023 4\nReserved 0x4002 2024 - 0x4002 2043 32\nFLASH_KEYR2 0x4002 2044 - 0x4002 2047 4\nReserved 0x4002 2048 - 0x4002 204B 4\nFLASH_SR2 0x4002 204C - 0x4002 204F 4\nFLASH_CR2 0x4002 2050 - 0x4002 2053 4\nFLASH_AR2 0x4002 2054 - 0x4002 2057 4\nFor further information on the Flash memory interface registers, please refer to the:\n● “STM32F10xxx XL-density Flash programming manual” (PM0068) for XL-density\ndevices\n● “STM32F10xxx Flash programming manual” (PM0075) for other devices\nReading the Flash memory\nFlash memory instructions and data access are performed through the AHB bus. The\nprefetch block is used for instruction fetches through the ICode bus. Arbitration is performed\nin the Flash memory interface, and priority is given to data access on the DCode bus.\nRead accesses can be performed with the following configuration options:\n58/1096\n● Latency: number of wait states for a read operation programmed on-the-fly\n● Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be\nreplaced with a single read from the Flash memory as the size of the block matches the\nbandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is\npossible as the CPU fetches one word at a time with the next word readily available in\nthe prefetch buffer\n● Half cycle: for power optimization\nDoc ID 13902 Rev 14 RM0008\nNote:\nMemory and bus architecture\n1 These options should be used in accordance with the Flash memory access time. The wait\nstates represent the ratio of the SYSCLK (system clock) period to the Flash memory access\ntime:\nzero wait state, if 0 < SYSCLK ≤ 24 MHz\none wait state, if 24 MHz < SYSCLK ≤ 48 MHz\ntwo wait states, if 48 MHz < SYSCLK ≤ 72 MHz\n2 Half cycle configuration is not available in combination with a prescaler on the AHB. The\nsystem clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be\nused only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or\nthe HSE but not from the PLL.\n3 The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB\nclock.\n4 The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and\nno prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch\nbuffer is usually switched on/off during the initialization routine, while the microcontroller is\nrunning on the internal 8 MHz RC (HSI) oscillator.\n5 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode\ninstructions. The DMA provides one free cycle after each transfer. Some instructions can be\nperformed together with DMA transfer.\nProgramming and erasing the Flash memory\nThe Flash memory can be programmed 16 bits (half words) at a time.\nFor write and erase operations on the Flash memory (write/erase), the internal RC oscillator\n(HSI) must be ON.\nThe Flash memory erase operation can be performed at page level or on the whole Flash\narea (mass-erase). The mass-erase does not affect the information blocks.\nTo ensure that there is no over-programming, the Flash Programming and Erase Controller\nblocks are clocked by a fixed clock.\nThe End of write operation (programming or erasing) can trigger an interrupt. This interrupt\ncan be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the\ninterrupt is served only after an exit from WFI.\nThe FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to\ncontrol the Flash memory access time according to the CPU frequency. The tables below\nprovide the bit map and bit descriptions for this register.\nFor complete information on Flash memory operations and register configurations, please\nrefer to the STM32F10xxx Flash programming manual (PM0075) or to the XL\nSTM32F10xxx Flash programming manual (PM0068).\nDoc ID 13902 Rev 14\n59/1096 Memory and bus architecture\nRM0008\nFlash access control register (FLASH_ACR)\nAddress offset: 0x00\nReset value: 0x0000 0030\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nPRFTBS PRFTBE HLFCYA\nLATENCY\nReserved\nr\nrw\nrw\nrw\nrw\nrw\nBits 31:6 Reserved, must be kept at reset value.\nBit 5 PRFTBS: Prefetch buffer status\nThis bit provides the status of the prefetch buffer.\n0: Prefetch buffer is disabled\n1: Prefetch buffer is enabled\nBit 4 PRFTBE: Prefetch buffer enable\n0: Prefetch is disabled\n1: Prefetch is enabled\nBit 3 HLFCYA: Flash half cycle access enable\n0: Half cycle is disabled\n1: Half cycle is enabled\nBits 2:0 LATENCY: Latency\nThese bits represent the ratio of the SYSCLK (system clock) period to the Flash access\ntime.\n000 Zero wait state, if 0 < SYSCLK≤ 24 MHz\n001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz\n010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz\n3.4\nBoot configuration\nIn the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as\nshown in Table 9.\nTable 9.\nBoot modes\nBoot mode selection pins\nBoot mode Aliasing\n0 Main Flash memory Main Flash memory is selected as boot space\n0 1 System memory System memory is selected as boot space\n1 1 Embedded SRAM Embedded SRAM is selected as boot space\nBOOT1 BOOT0\nx\nThe values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It\nis up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot\nmode.\nThe BOOT pins are also re-sampled when exiting from Standby mode. Consequently they\nmust be kept in the required Boot mode configuration in Standby mode. After this startup\n60/1096\nDoc ID 13902 Rev 14 RM0008\nMemory and bus architecture\ndelay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then\nstarts code execution from the boot memory starting from 0x0000 0004.\nDue to its fixed memory map, the code area starts from address 0x0000 0000 (accessed\nthrough the ICode/DCode buses) while the data area (SRAM) starts from address\n0x2000 0000 (accessed through the system bus). The Cortex-M3 CPU always fetches the\nreset vector on the ICode bus, which implies to have the boot space available only in the\ncode area (typically, Flash memory). STM32F10xxx microcontrollers implement a special\nmechanism to be able to boot also from SRAM and not only from main Flash memory and\nSystem memory.\nDepending on the selected boot mode, main Flash memory, system memory or SRAM is\naccessible as follows:\nNote:\n● Boot from main Flash memory: the main Flash memory is aliased in the boot memory\nspace (0x0000 0000), but still accessible from its original memory space (0x800 0000).\nIn other words, the Flash memory contents can be accessed starting from address\n0x0000 0000 or 0x800 0000.\n● Boot from system memory: the system memory is aliased in the boot memory space\n(0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in\nconnectivity line devices, 0x1FFF F000 in other devices).\n● Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.\nWhen booting from SRAM, in the application initialization code, you have to relocate the\nvector table in SRAM using the NVIC exception table and offset register.\nFor XL-density devices, when booting from the main Flash memory, you have an option to\nboot from any of two memory banks. By default, boot from Flash memory bank 1 is selected.\nYou can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user\noption bytes. When this bit is cleared and the boot pins are in the boot from main Flash\nmemory configuration, the device boots from system memory, and the boot loader jumps to\nexecute the user application programmed in Flash memory bank 2. For further details,\nplease refer to AN2606.\nNote:\nWhen booting from Bank2, in the applications initialization code, you have to relocate the\nvector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and\noffset register.\nEmbedded boot loader\nThe embedded boot loader is located in the System memory, programmed by ST during\nproduction. It is used to reprogram the Flash memory with one of the available serial\ninterfaces:\nNote:\n● In low-, medium- and high-density devices the bootoader is activated through the\nUSART1 interface.\n● In XL-density devices the boot loader is activated through the following interfaces:\nUSART1 or USART2 (remapped).\n● In connectivity line devices the boot loader can be activated through one of the\nfollowing interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG\nFS in Device mode (DFU: device firmware upgrade).\nThe USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and\nUSB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or\n25 MHz clock (HSE) is present.\nFor further details, please refer to AN2606.\nDoc ID 13902 Rev 14\n61/1096 CRC calculation unit\n4\nRM0008\nCRC calculation unit\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\n4.1\nCRC introduction\nThe CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit\ndata word and a fixed generator polynomial.\nAmong other applications, CRC-based techniques are used to verify data transmission or\nstorage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of\nverifying the Flash memory integrity. The CRC calculation unit helps compute a signature of\nthe software during runtime, to be compared with a reference signature generated at link-\ntime and stored at a given memory location.\n4.2\nCRC main features\n●\nUses CRC-32 (Ethernet) polynomial: 0x4C11DB7\n–\nX 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 +X 8 + X 7 + X 5 + X 4 + X 2 + X +1\n● Single input/output 32-bit data register\n● CRC computation done in 4 AHB clock cycles (HCLK)\n● General-purpose 8-bit register (can be used for temporary storage)\nThe block diagram is shown in Figure 3.\nFigure 3.\nCRC calculation unit block diagram\nAHB bus\n32-bit (read access)\nData register (output)\nCRC computation (polynomial: 0x4C11DB7)\n32-bit (write access)\nData register (input)\nai14968\n62/1096\nDoc ID 13902 Rev 14 RM0008\nCRC calculation unit\n4.3\nCRC functional description\nThe CRC calculation unit mainly consists of a single 32-bit data register, which:\n● is used as an input register to enter new data in the CRC calculator (when writing into\nthe register)\n● holds the result of the previous CRC calculation (when reading the register)\nEach write operation into the data register creates a combination of the previous CRC value\nand the new one (CRC computation is done on the whole 32-bit data word, and not byte per\nbyte).\nThe write operation is stalled until the end of the CRC computation, thus allowing back-to-\nback write accesses or consecutive write and read accesses.\nThe CRC calculator can be reset to 0xFFFF FFFF with the RESET control bit in the\nCRC_CR register. This operation does not affect the contents of the CRC_IDR register.\n4.4\nCRC registers\nThe CRC calculation unit contains two data registers and a control register.\n4.4.1\nData register (CRC_DR)\nAddress offset: 0x00\nReset value: 0xFFFF FFFF\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\nDR [31:16]\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nDR [15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 Data register bits\nUsed as an input register when writing new data into the CRC calculator.\nHolds the previous CRC calculation result when it is read.\n4.4.2\nIndependent data register (CRC_IDR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nIDR[7:0]\nReserved\nrw\nrw\nDoc ID 13902 Rev 14\nrw\nrw\nrw\n63/1096 CRC calculation unit\nRM0008\nBits 31:8 Reserved, must be kept at reset value.\nBits 7:0 General-purpose 8-bit data register bits\nCan be used as a temporary storage location for one byte.\nThis register is not affected by CRC resets generated by the RESET bit in the CRC_CR\nregister.\n4.4.3\nControl register (CRC_CR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17\n6 5 4 3 2 1\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n0\nRESET\nReserved\nw\nBits 31:1 Reserved, must be kept at reset value.\nBit 0 RESET bit\nResets the CRC calculation unit and sets the data register to 0xFFFF FFFF.\nThis bit can only be set, it is automatically cleared by hardware.\n4.4.4\nCRC register map\nThe following table provides the CRC register map and reset values.\nTable 10.\n64/1096\nCRC calculation unit register map and reset values\nOffset Register\n0x00 CRC_DR\nReset value\n0x04 CRC_IDR\nReset value\n0x08 CRC_CR\nReset value\n31-24\n23-16\n15-8\n7\n6\n5\n4\n3\n2\n1\n0\nData register\n0xFFFF FFFF\nIndependent data register\n0x00\nReserved\nReserved\nDoc ID 13902 Rev 14\nRESET\n0 RM0008\n5\nPower control (PWR)\nPower control (PWR)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F101xx family, unless otherwise specified.\n5.1\nPower supplies\nThe device requires a 2.0-to-3.6 V operating voltage supply (V DD ). An embedded regulator\nis used to supply the internal 1.8 V digital power.\nThe real-time clock (RTC) and backup registers can be powered from the V BAT voltage when\nthe main V DD supply is powered off.\nDoc ID 13902 Rev 14\n65/1096 Power control (PWR)\nFigure 4.\nRM0008\nPower supply overview\nV DDA domain\n(V SSA ) V REF-\n(from 2.4 V up to V DDA ) V REF+\nA/D converter\nD/A converter\nTemp. sensor\nReset block\nPLL\n(V DD ) V DDA\n(V SS ) V SSA\nV DD domain\n1.8 V domain\nI/O Ring\nV SS\nStandby circuitry\n(Wakeup logic,\nIWDG)\nV DD\nCore\nMemories\ndigital\nperipherals\nVoltage Regulator\nLow voltage detector\nBackup domain\nV BAT\nNote:\n5.1.1\n1\nLSE crystal 32K osc\nBKP registers\nRCC BDCR register\nRTC\nV DDA and V SSA must be connected to V DD and V SS , respectively.\nIndependent A/D and D/A converter supply and reference voltage\nTo improve conversion accuracy, the ADC and the DAC have an independent power supply\nwhich can be separately filtered and shielded from noise on the PCB.\n● The ADC and DAC voltage supply input is available on a separate V DDA pin.\n● An isolated supply ground connection is provided on pin V SSA .\nWhen available (according to package), V REF- must be tied to V SSA .\nOn 100-pin and 144-pin packages\nTo ensure a better accuracy on low-voltage inputs and outputs, the user can connect a\nseparate external reference voltage on V REF+ . V REF+ is the highest voltage, represented by\nthe full scale value, for an analog input (ADC) or output (DAC) signal. The voltage on V REF+\ncan range from 2.4 V to V DDA .\nOn 64-pin packages and packages with less pins\nThe V REF+ and V REF- pins are not available, they are internally connected to the ADC\nvoltage supply (V DDA ) and ground (V SSA ).\n66/1096\nDoc ID 13902 Rev 14 RM0008\n5.1.2\nPower control (PWR)\nBattery backup domain\nTo retain the content of the Backup registers and supply the RTC function when V DD is\nturned off, V BAT pin can be connected to an optional standby voltage supplied by a battery or\nby another source.\nThe V BAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing\nthe RTC to operate even when the main digital supply (V DD ) is turned off. The switch to the\nV BAT supply is controlled by the Power Down Reset embedded in the Reset block.\nWarning:\nDuring t RSTTEMPO (temporization at V DD startup) or after a PDR\nis detected, the power switch between V BAT and V DD remains\nconnected to V BAT .\nDuring the startup phase, if V DD is established in less than\nt RSTTEMPO (Refer to the datasheet for the value of t RSTTEMPO )\nand V DD > V BAT + 0.6 V, a current may be injected into V BAT\nthrough an internal diode connected between V DD and the\npower switch (V BAT ).\nIf the power supply/battery connected to the V BAT pin cannot\nsupport this current injection, it is strongly recommended to\nconnect an external low-drop diode between this power\nsupply and the V BAT pin.\nIf no external battery is used in the application, it is recommended to connect V BAT\nexternally to V DD with a 100 nF external ceramic decoupling capacitor (for more details refer\nto AN2586).\nWhen the backup domain is supplied by V DD (analog switch connected to V DD ), the\nfollowing functions are available:\nNote:\n● PC14 and PC15 can be used as either GPIO or LSE pins\n● PC13 can be used as GPIO, TAMPER pin, RTC Calibration Clock, RTC Alarm or\nsecond output (refer to Section 6: Backup registers (BKP) on page 79)\nDue to the fact that the switch only sinks a limited amount of current (3 mA), the use of\nGPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with\na maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive\nan LED).\nWhen the backup domain is supplied by V BAT (analog switch connected to V BAT because\nV DD is not present), the following functions are available:\n● PC14 and PC15 can be used as LSE pins only\n● PC13 can be used as TAMPER pin, RTC Alarm or Second output (refer to section\nSection 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 81).\nDoc ID 13902 Rev 14\n67/1096 Power control (PWR)\n5.1.3\nRM0008\nVoltage regulator\nThe voltage regulator is always enabled after Reset. It works in three different modes\ndepending on the application modes.\n● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories\nand digital peripherals).\n● In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving\ncontents of registers and SRAM\n● In Standby Mode, the regulator is powered off. The contents of the registers and SRAM\nare lost except for the Standby circuitry and the Backup Domain.\n5.2 Power supply supervisor\n5.2.1 Power on reset (POR)/power down reset (PDR)\nThe device has an integrated POR/PDR circuitry that allows proper operation starting\nfrom/down to 2 V.\nThe device remains in Reset mode when V DD /V DDA is below a specified threshold,\nV POR/PDR , without the need for an external reset circuit. For more details concerning the\npower on/power down reset threshold, refer to the electrical characteristics of the datasheet.\nFigure 5.\nPower on reset/power down reset waveform\nV DD /V DDA\nPOR\n40 mV\nhysteresis\nPDR\nTemporization\nt RSTTEMPO\nReset\n5.2.2\nProgrammable voltage detector (PVD)\nYou can use the PVD to monitor the V DD /V DDA power supply by comparing it to a threshold\nselected by the PLS[2:0] bits in the Power control register (PWR_CR).\nThe PVD is enabled by setting the PVDE bit.\nA PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if\nV DD /V DDA is higher or lower than the PVD threshold. This event is internally connected to\nthe EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The\n68/1096\nDoc ID 13902 Rev 14 RM0008\nPower control (PWR)\nPVD output interrupt can be generated when V DD /V DDA drops below the PVD threshold\nand/or when V DD /V DDA rises above the PVD threshold depending on EXTI line16\nrising/falling edge configuration. As an example the service routine could perform\nemergency shutdown tasks.\nFigure 6.\nPVD thresholds\nV DD /V DDA\nPVD threshold\n100 mV\nhysteresis\nPVD output\nDoc ID 13902 Rev 14\n69/1096 Power control (PWR)\n5.3\nRM0008\nLow-power modes\nBy default, the microcontroller is in Run mode after a system or a power Reset. Several low-\npower modes are available to save power when the CPU does not need to be kept running,\nfor example when waiting for an external event. It is up to the user to select the mode that\ngives the best compromise between low-power consumption, short startup time and\navailable wakeup sources.\nThe STM32F10xxx devices feature three low-power modes:\n● Sleep mode (CPU clock off, all peripherals including Cortex-M3 core peripherals like\nNVIC, SysTick, etc. are kept running)\n● Stop mode (all clocks are stopped)\n● Standby mode (1.8V domain powered-off)\nIn addition, the power consumption in Run mode can be reduce by one of the following\nmeans:\n● Slowing down the system clocks\n● Gating the clocks to the APB and AHB peripherals when they are unused.\nTable 11.\nLow-power mode summary\nMode name\nEntry\nSleep\nWFI\n(Sleep now or\nSleep-on -\nWFE\nexit)\nStop\nwakeup\nAny interrupt\nWakeup event\nEffect on 1.8V\ndomain clocks\nCPU clock OFF\nno effect on other None\nclocks or analog\nclock sources\nPDDS and LPDS\nAny EXTI line\nbits +\n(configured in the\nSLEEPDEEP bit\nEXTI registers)\n+ WFI or WFE\nAll 1.8V domain\nclocks OFF\nStandby\n5.3.1\nPDDS bit +\nSLEEPDEEP bit\n+ WFI or WFE\nWKUP pin rising\nedge, RTC alarm,\nexternal reset in\nNRST pin,\nIWDG reset\nEffect on\nV DD\ndomain\nclocks\nHSI and\nHSE\noscillators\nOFF\nVoltage\nregulator\nON\nON or in low-\npower mode\n(depends on\nPower control\nregister\n(PWR_CR))\nOFF\nSlowing down system clocks\nIn Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be\nreduced by programming the prescaler registers. These prescalers can also be used to slow\ndown peripherals before entering Sleep mode.\nFor more details refer to Section 7.3.2: Clock configuration register (RCC_CFGR).\n70/1096\nDoc ID 13902 Rev 14 RM0008\n5.3.2\nPower control (PWR)\nPeripheral clock gating\nIn Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped\nat any time to reduce power consumption.\nTo further reduce power consumption in Sleep mode the peripheral clocks can be disabled\nprior to executing the WFI or WFE instructions.\nPeripheral clock gating is controlled by the AHB peripheral clock enable register\n(RCC_AHBENR), APB1 peripheral clock enable register (RCC_APB1ENR) and APB2\nperipheral clock enable register (RCC_APB2ENR).\n5.3.3\nSleep mode\nEntering Sleep mode\nThe Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for\nEvent) instructions. Two options are available to select the Sleep mode entry mechanism,\ndepending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:\n● Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon\nas WFI or WFE instruction is executed.\n● Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as\nit exits the lowest priority ISR.\nIn the Sleep mode, all I/O pins keep the same state as in the Run mode.\nRefer to Table 12 and Table 13 for details on how to enter Sleep mode.\nExiting Sleep mode\nIf the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by\nthe nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.\nIf the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as\nan event occurs. The wakeup event can be generated either by:\n● enabling an interrupt in the peripheral control register but not in the NVIC, and enabling\nthe SEVONPEND bit in the Cortex-M3 System Control register. When the MCU\nresumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ\nchannel pending bit (in the NVIC interrupt clear pending register) have to be cleared.\n● or configuring an external or internal EXTI line in event mode. When the CPU resumes\nfrom WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC\nIRQ channel pending bit as the pending bit corresponding to the event line is not set.\nThis mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.\nRefer to Table 12 and Table 13 for more details on how to exit Sleep mode.\nDoc ID 13902 Rev 14\n71/1096 Power control (PWR)\nTable 12.\nRM0008\nSleep-now\nSleep-now mode\nDescription\nMode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– SLEEPDEEP = 0 and\n– SLEEPONEXIT = 0\nRefer to the Cortex™-M3 System Control register.\nMode exit If WFI was used for entry:\nInterrupt: Refer to Section 10.1.2: Interrupt and exception vectors on\npage 190\nIf WFE was used for entry\nWakeup event: Refer to Section 10.2.3: Wakeup event management\nWakeup latency None\nTable 13.\nSleep-on-exit\nSleep-on-exit\n5.3.4\nDescription\nMode entry WFI (wait for interrupt) while:\n– SLEEPDEEP = 0 and\n– SLEEPONEXIT = 1\nRefer to the Cortex™-M3 System Control register.\nMode exit Interrupt: refer to Section 10.1.2: Interrupt and exception vectors on\npage 190.\nWakeup latency None\nStop mode\nThe Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock\ngating. The voltage regulator can be configured either in normal or low-power mode. In Stop\nmode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC\noscillators are disabled. SRAM and register contents are preserved.\nIn the Stop mode, all I/O pins keep the same state as in the Run mode.\nEntering Stop mode\nRefer to Table 14 for details on how to enter the Stop mode.\nTo further reduce power consumption in Stop mode, the internal voltage regulator can be\nput in low-power mode. This is configured by the LPDS bit of the Power control register\n(PWR_CR).\nIf Flash memory programming is ongoing, the Stop mode entry is delayed until the memory\naccess is finished.\nIf an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB\naccess is finished.\nIn Stop mode, the following features can be selected by programming individual control bits:\n●\n72/1096\nIndependent watchdog (IWDG): the IWDG is started by writing to its Key register or by\nhardware option. Once started it cannot be stopped except by a Reset. See\nDoc ID 13902 Rev 14 RM0008\nPower control (PWR)\nSection 19.3: IWDG functional description in Section 19: Independent watchdog\n(IWDG).\n● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control\nregister (RCC_BDCR)\n● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status\nregister (RCC_CSR).\n● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the\nBackup domain control register (RCC_BDCR).\nThe ADC or DAC can also consume power during the Stop mode, unless they are disabled\nbefore entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit\nin the DAC_CR register must both be written to 0.\nExiting Stop mode\nRefer to Table 14 for more details on how to exit Stop mode.\nWhen exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is\nselected as system clock.\nWhen the voltage regulator operates in low-power mode, an additional startup delay is\nincurred when waking up from Stop mode. By keeping the internal regulator ON during Stop\nmode, the consumption is higher although the startup time is reduced.\nTable 14.\nStop mode\nStop mode\nMode entry\nDescription\nWFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– Set SLEEPDEEP bit in Cortex™-M3 System Control register\n– Clear PDDS bit in Power Control register (PWR_CR)\n– Select the voltage regulator mode by configuring LPDS bit in PWR_CR\nNote: To enter Stop mode, all EXTI Line pending bits (in Pending register\n(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the Stop mode\nentry procedure is ignored and program execution continues.\n5.3.5\nMode exit If WFI was used for entry:\nAny EXTI Line configured in Interrupt mode (the corresponding EXTI\nInterrupt vector must be enabled in the NVIC). Refer to Section 10.1.2:\nInterrupt and exception vectors on page 190.\nIf WFE was used for entry:\nAny EXTI Line configured in event mode. Refer to Section 10.2.3:\nWakeup event management on page 199\nWakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode\nStandby mode\nThe Standby mode allows to achieve the lowest power consumption. It is based on the\nCortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is\nconsequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also\nswitched off. SRAM and register contents are lost except for registers in the Backup domain\nand Standby circuitry (see Figure 4).\nDoc ID 13902 Rev 14\n73/1096 Power control (PWR)\nRM0008\nEntering Standby mode\nRefer to Table 15 for more details on how to enter Standby mode.\nIn Standby mode, the following features can be selected by programming individual control\nbits:\n● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by\nhardware option. Once started it cannot be stopped except by a reset. See\nSection 19.3: IWDG functional description in Section 19: Independent watchdog\n(IWDG).\n● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control\nregister (RCC_BDCR)\n● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status\nregister (RCC_CSR).\n● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the\nBackup domain control register (RCC_BDCR)\nExiting Standby mode\nThe microcontroller exits the Standby mode when an external reset (NRST pin), an IWDG\nreset, a rising edge on the WKUP pin or the rising edge of an RTC alarm occurs (see\nFigure 179: RTC simplified block diagram). All registers are reset after wakeup from\nStandby except for Power control/status register (PWR_CSR).\nAfter waking up from Standby mode, program execution restarts in the same way as after a\nReset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power\ncontrol/status register (PWR_CSR) indicates that the MCU was in Standby mode.\nRefer to Table 15 for more details on how to exit Standby mode.\nTable 15.\nStandby mode\nStandby mode\nDescription\nMode entry WFI (Wait for Interrupt) or WFE (Wait for Event) while:\n– Set SLEEPDEEP in Cortex™-M3 System Control register\n– Set PDDS bit in Power Control register (PWR_CR)\n– Clear WUF bit in Power Control/Status register (PWR_CSR)\nMode exit WKUP pin rising edge, RTC alarm event’s rising edge, external Reset in\nNRST pin, IWDG Reset.\nWakeup latency Reset phase\nI/O states in Standby mode\nIn Standby mode, all I/O pins are high impedance except:\n74/1096\n● Reset pad (still available)\n● TAMPER pin if configured for tamper or calibration out\n● WKUP pin, if enabled\nDoc ID 13902 Rev 14 RM0008\nPower control (PWR)\nDebug mode\nBy default, the debug connection is lost if the application puts the MCU in Stop or Standby\nmode while the debug features are used. This is due to the fact that the Cortex™-M3 core is\nno longer clocked.\nHowever, by setting some configuration bits in the DBGMCU_CR register, the software can\nbe debugged even when using the low-power modes extensively. For more details, refer to\nSection 31.16.1: Debug support for low-power modes.\n5.3.6\nAuto-wakeup (AWU) from low-power mode\nThe RTC can be used to wakeup the MCU from low-power mode without depending on an\nexternal interrupt (Auto-wakeup mode). The RTC provides a programmable time base for\nwaking up from Stop or Standby mode at regular intervals. For this purpose, two of the three\nalternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the\nBackup domain control register (RCC_BDCR):\n● Low-power 32.768 kHz external crystal oscillator (LSE OSC).\nThis clock source provides a precise time base with very low-power consumption (less\nthan 1µA added consumption in typical conditions)\n● Low-power internal RC Oscillator (LSI RC)\nThis clock source has the advantage of saving the cost of the 32.768 kHz crystal. This\ninternal RC Oscillator is designed to add minimum power consumption.\nTo wakeup from Stop mode with an RTC alarm event, it is necessary to:\n● Configure the EXTI Line 17 to be sensitive to rising edge\n● Configure the RTC to generate the RTC alarm\nTo wakeup from Standby mode, there is no need to configure the EXTI Line 17.\n5.4\nPower control registers\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n5.4.1\nPower control register (PWR_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000 (reset by wakeup from Standby mode)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nPVDE CSBF CWUF PDDS LPDS\nrw rc_w1 rc_w1 rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nDBP\nPLS[2:0]\nReserved\nrw\nBits 31:9\nrw\nrw\nrw\nReserved, must be kept at reset value..\nDoc ID 13902 Rev 14\n75/1096 Power control (PWR)\nRM0008\nBit 8 DBP: Disable backup domain write protection.\nIn reset state, the RTC and backup registers are protected against parasitic write access.\nThis bit must be set to enable write access to these registers.\n0: Access to RTC and Backup registers disabled\n1: Access to RTC and Backup registers enabled\nNote: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.\nBits 7:5 PLS[2:0]: PVD level selection.\nThese bits are written by software to select the voltage threshold detected by the Power\nVoltage Detector\n000: 2.2V\n001: 2.3V\n010: 2.4V\n011: 2.5V\n100: 2.6V\n101: 2.7V\n110: 2.8V\n111: 2.9V\nNote: Refer to the electrical characteristics of the datasheet for more details.\nBit 4 PVDE: Power voltage detector enable.\nThis bit is set and cleared by software.\n0: PVD disabled\n1: PVD enabled\nBit 3 CSBF: Clear standby flag.\nThis bit is always read as 0.\n0: No effect\n1: Clear the SBF Standby Flag (write).\nBit 2 CWUF: Clear wakeup flag.\nThis bit is always read as 0.\n0: No effect\n1: Clear the WUF Wakeup Flag after 2 System clock cycles. (write)\nBit 1 PDDS: Power down deepsleep.\nThis bit is set and cleared by software. It works together with the LPDS bit.\n0: Enter Stop mode when the CPU enters Deepsleep. The regulator status depends on the\nLPDS bit.\n1: Enter Standby mode when the CPU enters Deepsleep.\nBit 0 LPDS: Low-power deepsleep.\nThis bit is set and cleared by software. It works together with the PDDS bit.\n0: Voltage regulator on during Stop mode\n1: Voltage regulator in low-power mode during Stop mode\n76/1096\nDoc ID 13902 Rev 14 RM0008\nPower control (PWR)\n5.4.2\nPower control/status register (PWR_CSR)\nAddress offset: 0x04\nReset value: 0x0000 0000 (not reset by wakeup from Standby mode)\nAdditional APB cycles are needed to read this register versus a standard APB read.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nPVDO SBF WUF\nr r r\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nEWUP\nReserved\nReserved\nrw\nBits 31:9 Reserved, must be kept at reset value.\nBit 8 EWUP: Enable WKUP pin\nThis bit is set and cleared by software.\n0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup\nthe device from Standby mode.\n1: WKUP pin is used for wakeup from Standby mode and forced in input pull down\nconfiguration (rising edge on WKUP pin wakes-up the system from Standby mode).\nNote: This bit is reset by a system Reset.\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 PVDO: PVD output\nThis bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.\n0: V DD /V DDA is higher than the PVD threshold selected with the PLS[2:0] bits.\n1: V DD /V DDA is lower than the PVD threshold selected with the PLS[2:0] bits.\nNote: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after\nStandby or reset until the PVDE bit is set.\nBit 1 SBF: Standby flag\nThis bit is set by hardware and cleared only by a POR/PDR (power on reset/power down reset)\nor by setting the CSBF bit in the Power control register (PWR_CR)\n0: Device has not been in Standby mode\n1: Device has been in Standby mode\nBit 0 WUF: Wakeup flag\nThis bit is set by hardware and cleared only by a POR/PDR (power on reset/power down\nreset) or by setting the CWUF bit in the Power control register (PWR_CR)\n0: No wakeup event occurred\n1: A wakeup event was received from the WKUP pin or from the RTC alarm\nNote: An additional wakeup event is detected if the WKUP pin is enabled (by setting the\nEWUP bit) when the WKUP pin level is already high.\nDoc ID 13902 Rev 14\n77/1096 Power control (PWR)\n5.4.3\nRM0008\nPWR register map\nThe following table summarizes the PWR registers.\nRefer to Table 3 on page 50 for the register boundary addresses.\n78/1096\nDoc ID 13902 Rev 14\nReserved\n0\n0\n0 0 0 0\nReserved\nReset value\n0\n0\nPWR_CSR\n0\n0x004\n0\nReset value\nPLS[2:0]\nReserved\nPWR_CR\n0x000\nPWR register map and reset values\nRegister\nOffset\n31\nTable 16.\n0 0 0 RM0008\n6\nBackup registers (BKP)\nBackup registers (BKP)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F101xx family, unless otherwise specified.\n6.1\nBKP introduction\nThe backup registers are forty two 16-bit registers for storing 84 bytes of user application\ndata.\nThey are implemented in the backup domain that remains powered on by V BAT when the\nV DD power is switched off. They are not reset when the device wakes up from Standby\nmode or by a system reset or power reset.\nIn addition, the BKP control registers are used to manage the Tamper detection feature and\nRTC calibration.\nAfter reset, access to the Backup registers and RTC is disabled and the Backup domain\n(BKP) is protected against possible parasitic write access. To enable access to the Backup\nregisters and the RTC, proceed as follows:\n6.2\n● enable the power and backup interface clocks by setting the PWREN and BKPEN bits\nin the RCC_APB1ENR register\n● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup\nregisters and RTC.\nBKP main features\n● 20-byte data registers (in medium-density and low-density devices) or 84-byte data\nregisters (in high-density, XL-density and connectivity line devices)\n● Status/control register for managing tamper detection with interrupt capability\n● Calibration register for storing the RTC calibration value\n● Possibility to output the RTC Calibration Clock, RTC Alarm pulse or Second pulse on\nTAMPER pin PC13 (when this pin is not used for tamper detection)\nDoc ID 13902 Rev 14\n79/1096 Backup registers (BKP)\nRM0008\n6.3 BKP functional description\n6.3.1 Tamper detection\nThe TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or\nfrom 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper\ndetection event resets all data backup registers.\nHowever to avoid losing Tamper events, the signal used for edge detection is logically\nANDed with the Tamper enable in order to detect a Tamper event in case it occurs before\nthe TAMPER pin is enabled.\n● When TPAL=0: If the TAMPER pin is already high before it is enabled (by setting TPE\nbit), an extra Tamper event is detected as soon as the TAMPER pin is enabled (while\nthere was no rising edge on the TAMPER pin after TPE was set)\n● When TPAL=1: If the TAMPER pin is already low before it is enabled (by setting the\nTPE bit), an extra Tamper event is detected as soon as the TAMPER pin is enabled\n(while there was no falling edge on the TAMPER pin after TPE was set)\nBy setting the TPIE bit in the BKP_CSR register, an interrupt is generated when a Tamper\ndetection event occurs.\nAfter a Tamper event has been detected and cleared, the TAMPER pin should be disabled\nand then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.\nThis prevents software from writing to the backup data registers (BKP_DRx), while the\nTAMPER pin value still indicates a Tamper detection. This is equivalent to a level detection\non the TAMPER pin.\nNote: Tamper detection is still active when V DD power is switched off. To avoid unwanted resetting\nof the data backup registers, the TAMPER pin should be externally tied to the correct level.\n6.3.2 RTC calibration\nFor measurement purposes, the RTC clock with a frequency divided by 64 can be output on\nthe TAMPER pin. This is enabled by setting the CCO bit in the RTC clock calibration register\n(BKP_RTCCR).\nThe clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.\nFor more details about RTC calibration and how to use it to improve timekeeping accuracy,\nplease refer to AN2604 \"STM32F101xx and STM32F103xx RTC calibration”.\n80/1096\nDoc ID 13902 Rev 14 RM0008\nBackup registers (BKP)\n6.4\nBKP registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n6.4.1\nBackup data register x (BKP_DRx) (x = 1 ..42)\nAddress offset: 0x04 to 0x28, 0x40 to 0xBC\nReset value: 0x0000 0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw rw\nD[15:0]\nBits 15:0 D[15:0] Backup data\nThese bits can be written with user data.\nNote: The BKP_DRx registers are not reset by a System reset or Power reset or when the\ndevice wakes up from Standby mode.\nThey are reset by a Backup Domain reset or by a TAMPER pin event (if the TAMPER\npin function is activated).\n6.4.2\nRTC clock calibration register (BKP_RTCCR)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n15\n14\n13\n12\n11\n10\n9 8 7\nASOS ASOE CCO\nrw rw rw\n6\n5\n4\n3\n2 1 0\nrw rw rw\nCAL[6:0]\nReserved\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 ASOS: Alarm or second output selection\nWhen the ASOE bit is set, the ASOS bit can be used to select whether the signal output on\nthe TAMPER pin is the RTC Second pulse signal or the Alarm pulse signal:\n0: RTC Alarm pulse output selected\n1: RTC Second pulse output selected\nNote: This bit is reset only by a Backup domain reset.\nBit 8 ASOE: Alarm or second output enable\nSetting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the\nTAMPER pin depending on the ASOS bit.\nThe output pulse duration is one RTC clock period. The TAMPER pin must not be enabled\nwhile the ASOE bit is set.\nNote: This bit is reset only by a Backup domain reset.\nBit 7 CCO: Calibration clock output\n0: No effect\n1: Setting this bit outputs the RTC clock with a frequency divided by 64 on the TAMPER pin.\nThe TAMPER pin must not be enabled while the CCO bit is set in order to avoid unwanted\nTamper detection.\nNote: This bit is reset when the V DD supply is powered off.\nDoc ID 13902 Rev 14\n81/1096 Backup registers (BKP)\nRM0008\nBit 6:0 CAL[6:0]: Calibration value\nThis value indicates the number of clock pulses that will be ignored every 2^20 clock pulses.\nThis allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20\nPPM.\nThe clock of the RTC can be slowed down from 0 to 121PPM.\n6.4.3\nBackup control register (BKP_CR)\nAddress offset: 0x30\nReset value: 0x0000 0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1 0\nTPAL TPE\nrw rw\nReserved\nBits 15:2 Reserved, must be kept at reset value.\nBit 1 TPAL: TAMPER pin active level\n0: A high level on the TAMPER pin resets all data backup registers (if TPE bit is set).\n1: A low level on the TAMPER pin resets all data backup registers (if TPE bit is set).\nBit 0 TPE: TAMPER pin enable\n0: The TAMPER pin is free for general purpose I/O\n1: Tamper alternate I/O function is activated.\nNote: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at\nthe same time can generate a spurious Tamper event. For this reason it is recommended to\nchange the TPAL bit only when the TPE bit is reset.\n6.4.4 Backup control/status register (BKP_CSR)\nAddress offset: 0x34\nReset value: 0x0000 0000\n15\n14\n13\n12\n11\n10\n9 8\nTIF TEF\nr r\n7\n6\nReserved\n5\n4\n3\n2 1 0\nTPIE CTI CTE\nrw w w\nReserved\nBits 15:10 Reserved, must be kept at reset value.\nBit 9 TIF: Tamper interrupt flag\nThis bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is\ncleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is\nreset.\n0: No Tamper interrupt\n1: A Tamper interrupt occurred\nNote: This bit is reset only by a system reset and wakeup from Standby mode.\n82/1096\nDoc ID 13902 Rev 14 RM0008\nBackup registers (BKP)\nBit 8 TEF: Tamper event flag\nThis bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the\nCTE bit.\n0: No Tamper event\n1: A Tamper event occurred\nNote: A Tamper event resets all the BKP_DRx registers. They are held in reset as long as the\nTEF bit is set. If a write to the BKP_DRx registers is performed while this bit is set, the\nvalue will not be stored.\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 TPIE: TAMPER pin interrupt enable\n0: Tamper interrupt disabled\n1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register\nNote: 1: A Tamper interrupt does not wake up the core from low-power modes.\n2: This bit is reset only by a system reset and wakeup from Standby mode.\nBit 1 CTI: Clear tamper interrupt\nThis bit is write only, and is always read as 0.\n0: No effect\n1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.\nBit 0 CTE: Clear tamper event\nThis bit is write only, and is always read as 0.\n0: No effect\n1: Reset the TEF Tamper event flag (and the Tamper detector)\n6.4.5\nBKP register map\nBKP registers are mapped as 16-bit addressable registers as described in the table below:\nOffset\nBKP register map and reset values\nRegister\nTable 17.\n0x00\n0x04\nReserved\nBKP_DR1\nReset value\n0x08\nBKP_DR2\n0\nBKP_DR3\nBKP_DR4\nBKP_DR5\nBKP_DR6\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\nDoc ID 13902 Rev 14\n0\nD[15:0]\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x18\n0\nReserved\nReset value\n0x14\n0\nD[15:0]\n0\nReset value\n0x10\n0\nReserved\nReset value\n0x0C\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n83/1096 Backup registers (BKP)\nD[15:0]\nReserved\nReset value\nBKP_DR9\nBKP_DR10\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0\nD[15:0]\nReserved\n0\nBKP_RTCCR\n0\nD[15:0]\n0\n0\n0\n0\n0\nReserved\nReset value\n0x30\n0\nReserved\nReset value\n0x2\n0\nD[15:0]\nReset value\n0x28\n0\nReserved\nReset value\n0x24\n0\nBKP_CR\n0 0 0\n0 0 0\nCAL[6:0]\n0\n0\n0\n0\n0\nReserved\n0x38 Reserved\n0x3C Reserved\n0x40\nBKP_DR11\nBKP_DR12\nBKP_DR13\n0x4C\nBKP_DR14\nBKP_DR15\n0x54\nBKP_DR16\nBKP_DR17\n0x5C\nBKP_DR18\nBKP_DR19\n84/1096\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\nDoc ID 13902 Rev 14\n0\nD[15:0]\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x60\n0\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x58\n0\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x50\n0\nReserved\nReset value\nReserved\nD[15:0]\n0\nReset value\n0x48\n0\nReserved\nReset value\n0x44\n0 0\nReserved\nReset value\n0\nBKP_CSR\n0x34\nReset value\nBKP_DR8\n0\n0x20\n0\nBKP_DR7\n0x1C\nRegister\nOffset\nBKP register map and reset values (continued)\nTable 17.\nRM0008\n0\n0\n0\n0\n0\n0\n0\n0 RM0008\nBackup registers (BKP)\nOffset\n0x64\nBKP register map and reset values (continued)\nRegister\nBKP_DR20\nTable 17.\nReset value\n0x68\nBKP_DR21\n0\nBKP_DR22\nBKP_DR23\nBKP_DR24\nBKP_DR25\nBKP_DR26\nBKP_DR27\nBKP_DR28\nBKP_DR29\n0x8C\nBKP_DR30\nBKP_DR31\n0x94\nBKP_DR32\nBKP_DR33\n0x9C\nBKP_DR34\nBKP_DR35\n0xA4\nBKP_DR36\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\nDoc ID 13902 Rev 14\n0\nD[15:0]\nReserved\nReset value\n0\nD[15:0]\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0xA0\n0\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x98\n0\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x90\n0\nReserved\nReset value\n0\nD[15:0]\n0\nReset value\n0x88\n0\nReserved\nReset value\n0x84\n0\nD[15:0]\n0\nReset value\n0x80\n0\nReserved\nReset value\n0x7C\n0\nD[15:0]\n0\nReset value\n0x78\n0\nReserved\nReset value\n0x74\n0\nD[15:0]\n0\nReset value\n0x70\n0\nReserved\nReset value\n0x6C\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n85/1096 Backup registers (BKP)\nOffset\n0xA8\nBKP register map and reset values (continued)\nRegister\nBKP_DR37\nTable 17.\nRM0008\nReset value\n0xAC\nBKP_DR38\n0\nBKP_DR39\nBKP_DR40\nBKP_DR41\nBKP_DR42\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\nD[15:0]\nReserved\n0\n0\n0\n0\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n0\nD[15:0]\nReserved\nReset value\n86/1096\n0\nD[15:0]\n0\nReset value\n0xBC\n0\nReserved\nReset value\n0xB8\n0\nD[15:0]\n0\nReset value\n0xB4\n0\nReserved\nReset value\n0xB0\nD[15:0]\nReserved\n0\n0\n0 RM0008\n7\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nLow-, medium-, high- and XL-density reset and clock\ncontrol (RCC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis Section applies to low-, medium-, high- and XL-density STM32F10xxx devices.\nConnectivity line devices are discussed in a separate section (refer to Connectivity line\ndevices: reset and clock control (RCC) on page 120).\n7.1\nReset\nThere are three types of reset, defined as system reset, power reset and backup domain\nreset.\n7.1.1\nSystem reset\nA system reset sets all registers to their reset values except the reset flags in the clock\ncontroller CSR register and the registers in the Backup domain (see Figure 4).\nA system reset is generated when one of the following events occurs:\n1. A low level on the NRST pin (external reset)\n2. Window watchdog end of count condition (WWDG reset)\n3. Independent watchdog end of count condition (IWDG reset)\n4. A software reset (SW reset) (see Software reset)\n5. Low-power management reset (see Low-power management reset)\nThe reset source can be identified by checking the reset flags in the Control/Status register,\nRCC_CSR (see Section 7.3.10: Control/status register (RCC_CSR)).\nSoftware reset\nThe SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register\nmust be set to force a software reset on the device. Refer to the STM32F10xxx Cortex-M3\nprogramming manual (see Related documents on page 1) for more details.\nLow-power management reset\nThere are two ways to generate a low-power management reset:\nDoc ID 13902 Rev 14\n87/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\n1.\nRM0008\nReset generated when entering Standby mode:\nThis type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this\ncase, whenever a Standby mode entry sequence is successfully executed, the device\nis reset instead of entering Standby mode.\n2.\nReset when entering Stop mode:\nThis type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this\ncase, whenever a Stop mode entry sequence is successfully executed, the device is\nreset instead of entering Stop mode.\nFor further information on the User Option Bytes, refer to the STM32F10xxx Flash\nprogramming manual.\n7.1.2\nPower reset\nA power reset is generated when one of the following events occurs:\n1. Power-on/power-down reset (POR/PDR reset)\n2. When exiting Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see\nFigure 4)\nThese sources act on the NRST pin and it is always kept low during the delay phase. The\nRESET service routine vector is fixed at address 0x0000_0004 in the memory map.\nThe system reset signal provided to the device is output on the NRST pin. The pulse\ngenerator guarantees a minimum reset pulse duration of 20 µs for each reset source\n(external or internal reset). In case of an external reset, the reset pulse is generated while\nthe NRST pin is asserted low.\nFigure 7.\nSimplified diagram of the reset circuit\n6 $$ \u000f6 $$!\n2 05\n%XTERNAL\nRESET\n&ILTER\n3YSTEM RM0008\n7.2\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n● HSI oscillator clock\n● HSE oscillator clock\n● PLL clock\nThe devices have the following two secondary clock sources:\n● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and\noptionally the RTC used for Auto-wakeup from Stop/Standby mode.\n● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-\ntime clock (RTCCLK)\nEach clock source can be switched on or off independently when it is not used, to optimize\npower consumption.\nDoc ID 13902 Rev 14\n89/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nFigure 8.\nRM0008\nClock tree\n&,)4&#,+\nTO RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nThe timer clock frequencies are automatically fixed by hardware. There are two cases:\n1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as\nthat of the APB domain to which the timers are connected.\n2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the\ntimers are connected.\nFCLK acts as Cortex™-M3’s free-running clock. For more details refer to the ARM Cortex™-\nM3 r1p1 Technical Reference Manual (TRM).\n7.2.1\nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock\nsources:\n● HSE external crystal/ceramic resonator\n● HSE user external clock\nThe resonator and the load capacitors have to be placed as close as possible to the\noscillator pins in order to minimize output distortion and startup stabilization time. The\nloading capacitance values must be adjusted according to the selected oscillator.\nFigure 9.\nHSE/ LSE clock sources\nClock source\nHardware configuration\nOSC_OUT\nExternal clock\n(HiZ)\nExternal\nsource\nOSC_IN OSC_OUT\nCrystal/Ceramic\nresonators\nC L1\nDoc ID 13902 Rev 14\nLoad\ncapacitors\nC L2\n91/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. It can have a frequency of up to\n25 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control\nregister (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty\ncycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 9.\nExternal crystal/ceramic resonator (HSE crystal)\nThe 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on\nthe main clock.\nThe associated hardware configuration is shown in Figure 9. Refer to the electrical\ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed\nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by\nhardware. An interrupt can be generated if enabled in the Clock interrupt register\n(RCC_CIR).\nThe HSE Crystal can be switched on and off using the HSEON bit in the Clock control\nregister (RCC_CR).\n7.2.2\nHSI clock\nThe HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used\ndirectly as a system clock or divided by 2 to be used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external\ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even\nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic\nresonator.\nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process\nvariations, this is why each device is factory calibrated by ST for 1% accuracy at T A =25°C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control\nregister (RCC_CR).\nIf the application is subject to voltage or temperature variations this may affect the RC\noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]\nbits in the Clock control register (RCC_CR).\nThe HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or\nnot. At startup, the HSI RC output clock is not released until this bit is set by hardware.\nThe HSI RC can be switched on and off using the HSION bit in the Clock control register\n(RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal\noscillator fails. Refer to Section 7.2.7: Clock security system (CSS) on page 94.\n92/1096\nDoc ID 13902 Rev 14 RM0008\n7.2.3\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nPLL\nThe internal PLL can be used to multiply the HSI RC output or HSE crystal output clock\nfrequency. Refer to Figure 8 and Clock control register (RCC_CR).\nThe PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL\ninput clock, and multiplication factor) must be done before enabling the PLL. Once the PLL\nenabled, these parameters cannot be changed.\nAn interrupt can be generated when the PLL is ready if enabled in the Clock interrupt\nregister (RCC_CIR).\nIf the USB interface is used in the application, the PLL must be programmed to output 48 or\n72 MHz. This is needed to provide a 48 MHz USBCLK.\n7.2.4\nLSE clock\nThe LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the\nadvantage providing a low-power but highly accurate clock source to the real-time clock\nperipheral (RTC) for clock/calendar or other timing functions.\nThe LSE crystal is switched on and off using the LSEON bit in Backup domain control\nregister (RCC_BDCR).\nThe LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE\ncrystal is stable or not. At startup, the LSE crystal output clock signal is not released until\nthis bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt\nregister (RCC_CIR).\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It can have a frequency of up to\n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain\ncontrol register (RCC_BDCR). The external clock signal (square, sinus or triangle) with\n~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left\nHi-Z. See Figure 9.\n7.2.5\nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and\nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The\nclock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to\nthe electrical characteristics section of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the Control/status register\n(RCC_CSR).\nThe LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed\ninternal oscillator is stable or not. At startup, the clock is not released until this bit is set by\nhardware. An interrupt can be generated if enabled in the Clock interrupt register\n(RCC_CIR).\nNote:\nLSI calibration is only available on high-density, XL-density and connectivity line devices.\nDoc ID 13902 Rev 14\n93/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nLSI calibration\nThe frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to\nhave accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for\nthese peripherals) with an acceptable accuracy.\nThis calibration is performed by measuring the LSI clock frequency with respect to TIM5\ninput clock (TIM5CLK). According to this measurement done at the precision of the HSE\noscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an\naccurate time base or can compute accurate IWDG timeout.\nUse the following procedure to calibrate the LSI:\n7.2.6\n1. Enable TIM5 timer and configure channel4 in input capture mode\n2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock\ninternally to TIM5 channel4 input capture for calibration purpose.\n3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or\ninterrupt.\n4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending\non the desired time base and/or to compute the IWDG timeout.\nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as system clock. When a clock source is\nused directly or through the PLL as system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready\n(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is\nselected, the switch will occur when the clock source will be ready. Status bits in the Clock\ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently\nused as system clock.\n7.2.7\nClock security system (CSS)\nClock Security System can be activated by software. In this case, the clock detector is\nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\nIf a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock\nfailure event is sent to the break input of the advanced-control timers (TIM1 and TIM8) and\nan interrupt is generated to inform the software about the failure (Clock Security System\nInterrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the\nCortex™-M3 NMI (Non-Maskable Interrupt) exception vector.\nNote:\nOnce the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is\nautomatically generated. The NMI will be executed indefinitely unless the CSS interrupt\npending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt\nby setting the CSSC bit in the Clock interrupt register (RCC_CIR).\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is\nused as PLL input clock, and the PLL clock is used as system clock), a detected failure\ncauses a switch of the system clock to the HSI oscillator and the disabling of the HSE\noscillator. If the HSE clock (divided or not) is the clock entry of the PLL used as system clock\nwhen the failure occurs, the PLL is disabled too.\n94/1096\nDoc ID 13902 Rev 14 RM0008\n7.2.8\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nRTC clock\nThe RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected\nby programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).\nThis selection cannot be modified without resetting the Backup domain.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.\nConsequently:\n●\nIf LSE is selected as RTC clock:\n–\n●\nIf LSI is selected as Auto-Wakeup unit (AWU) clock:\n–\n●\n7.2.9\nThe RTC continues to work even if the V DD supply is switched off, provided the\nV BAT supply is maintained.\nThe AWU state is not guaranteed if the V DD supply is powered off. Refer to\nSection 7.2.5: LSI clock on page 93 for more details on LSI calibration.\nIf the HSE clock divided by 128 is used as the RTC clock:\n– The RTC state is not guaranteed if the V DD supply is powered off or if the internal\nvoltage regulator is powered off (removing power from the 1.8 V domain).\n– The DPB bit (disable backup domain write protection) in the Power controller\nregister must be set to 1 (refer to Section 5.4.1: Power control register\n(PWR_CR)).\nWatchdog clock\nIf the Independent watchdog (IWDG) is started by either hardware option or software\naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator\ntemporization, the clock is provided to the IWDG.\n7.2.10\nClock-out capability\nThe microcontroller clock output (MCO) capability allows the clock to be output onto the\nexternal MCO pin. The configuration registers of the corresponding GPIO port must be\nprogrammed in alternate function mode. One of 4 clock signals can be selected as the MCO\nclock.\n● SYSCLK\n● HSI\n● HSE\n● PLL clock divided by 2\nThe selection is controlled by the MCO[2:0] bits of the Clock configuration register\n(RCC_CFGR).\nDoc ID 13902 Rev 14\n95/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\n7.3\nRM0008\nRCC registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\n7.3.1\nClock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\nReserved\n15\n14\n13\n12\n11\n10\n25\n24\nPLL\nRDY PLLON\nr rw\n9 8\n23\n22\n21\n20\nReserved\n7\n6\nHSICAL[7:0]\n5\n4\n19 18 17 16\nCSS\nON HSE\nBYP HSE\nRDY HSE\nON\nrw rw r rw\n3 2 1 0\nHSI\nRDY HSION\nr rw\nHSITRIM[4:0]\nRes.\nr\nr\nr\nBits 31:26\nr\nr\nr\nr\nr\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBit 25 PLLRDY: PLL clock ready flag\nSet by hardware to indicate that the PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: PLL enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit can not be reset if the\nPLL clock is used as system clock or is selected to become the system clock.\n0: PLL OFF\n1: PLL ON\nBits 23:20\nReserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the\nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by\nhardware if a HSE clock failure is detected.\n0: Clock detector OFF\n1: Clock detector ON (Clock detector ON if the HSE oscillator is ready , OFF if not).\nBit 18 HSEBYP: External high-speed clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external\nclock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit\ncan be written only if the HSE oscillator is disabled.\n0: external 4-16 MHz oscillator not bypassed\n1: external 4-16 MHz oscillator bypassed with external clock\n96/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 17 HSERDY: External high-speed clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the\nHSE oscillator clock to fall down after HSEON reset.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This\nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the\nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature\nthat influence the frequency of the internal HSI RC.\nThe default value is 16, which, when added to the HSICAL value, should trim the HSI to 8\nMHz ± 1%. The trimming step (F hsitrim ) is around 40 kHz between two consecutive HSICAL\nsteps.\nBit 2\nReserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is\ncleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.\n0: internal 8 MHz RC oscillator not ready\n1: internal 8 MHz RC oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby\nmode or in case of failure of the external 4-16 MHz oscillator used directly or indirectly as\nsystem clock. This bit cannot be reset if the internal 8 MHz RC is used directly or indirectly\nas system clock or is selected to become the system clock.\n0: internal 8 MHz RC oscillator OFF\n1: internal 8 MHz RC oscillator ON\nDoc ID 13902 Rev 14\n97/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\n7.3.2\nRM0008\nClock configuration register (RCC_CFGR)\nAddress offset: 0x04\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during clock source switch.\n31\n30\n29\n28\n27\n26\n25\n24\n23 22\nRes. USB\nPRE\nMCO[2:0]\nReserved\n15\n14\n13\nADCPRE[1:0]\nrw\nrw\n12\n11\nrw rw rw\n10 9 8\nPPRE2[2:0]\nrw\nrw\n7\nPPRE1[2:0]\nrw\nrw\nrw\n21\n20\nrw\n18\nPLLMUL[3:0]\n17 16\nPLL\nXTPRE PLL\nSRC\nrw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nHPRE[3:0]\nrw\n19\nrw\nrw\nSWS[1:0]\nrw\nr\nr\nSW[1:0]\nrw\nrw\nBits 31:27 Reserved, must be kept at reset value.\nBits 26:24 MCO: Microcontroller clock output\nSet and cleared by software.\n0xx: No clock\n100: System clock (SYSCLK) selected\n101: HSI clock selected\n110: HSE clock selected\n111: PLL clock divided by 2 selected\nNote: This clock output may have some truncated cycles at startup or during MCO clock\nsource switching.\nWhen the System Clock is selected to output to the MCO pin, make sure that this clock\ndoes not exceed 50 MHz (the maximum IO speed).\nBit 22 USBPRE: USB prescaler\nSet and cleared by software to generate 48 MHz USB clock. This bit must be valid before\nenabling the USB clock in the RCC_APB1ENR register. This bit can’t be reset if the USB\nclock is enabled.\n0: PLL clock is divided by 1.5\n1: PLL clock is not divided\n98/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBits 21:18 PLLMUL: PLL multiplication factor\nThese bits are written by software to define the PLL multiplication factor. These bits can be\nwritten only when PLL is disabled.\nCaution: The PLL output frequency must not exceed 72 MHz.\n0000: PLL input clock x 2\n0001: PLL input clock x 3\n0010: PLL input clock x 4\n0011: PLL input clock x 5\n0100: PLL input clock x 6\n0101: PLL input clock x 7\n0110: PLL input clock x 8\n0111: PLL input clock x 9\n1000: PLL input clock x 10\n1001: PLL input clock x 11\n1010: PLL input clock x 12\n1011: PLL input clock x 13\n1100: PLL input clock x 14\n1101: PLL input clock x 15\n1110: PLL input clock x 16\n1111: PLL input clock x 16\nBit 17 PLLXTPRE: HSE divider for PLL entry\nSet and cleared by software to divide HSE before PLL entry. This bit can be written only\nwhen PLL is disabled.\n0: HSE clock not divided\n1: HSE clock divided by 2\nBit 16 PLLSRC: PLL entry clock source\nSet and cleared by software to select PLL clock source. This bit can be written only when\nPLL is disabled.\n0: HSI oscillator clock / 2 selected as PLL input clock\n1: HSE oscillator clock selected as PLL input clock\nBits 15:14 ADCPRE: ADC prescaler\nSet and cleared by software to select the frequency of the clock to the ADCs.\n00: PCLK2 divided by 2\n01: PCLK2 divided by 4\n10: PCLK2 divided by 6\n11: PCLK2 divided by 8\nBits 13:11 PPRE2: APB high-speed prescaler (APB2)\nSet and cleared by software to control the division factor of the APB high-speed clock\n(PCLK2).\n0xx: HCLK not divided\n100: HCLK divided by 2\n101: HCLK divided by 4\n110: HCLK divided by 8\n111: HCLK divided by 16\nDoc ID 13902 Rev 14\n99/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nBits 10:8 PPRE1: APB low-speed prescaler (APB1)\nSet and cleared by software to control the division factor of the APB low-speed clock\n(PCLK1).\nWarning: the software has to set correctly these bits to not exceed 36 MHz on this domain.\n0xx: HCLK not divided\n100: HCLK divided by 2\n101: HCLK divided by 4\n110: HCLK divided by 8\n111: HCLK divided by 16\nBits 7:4 HPRE: AHB prescaler\nSet and cleared by software to control the division factor of the AHB clock.\n0xxx: SYSCLK not divided\n1000: SYSCLK divided by 2\n1001: SYSCLK divided by 4\n1010: SYSCLK divided by 8\n1011: SYSCLK divided by 16\n1100: SYSCLK divided by 64\n1101: SYSCLK divided by 128\n1110: SYSCLK divided by 256\n1111: SYSCLK divided by 512\nNote: The prefetch buffer must be kept on when using a prescaler different from 1 on the\nAHB clock. Refer to Reading the Flash memory on page 58 section for more details.\nBits 3:2 SWS: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as system clock.\n00: HSI oscillator used as system clock\n01: HSE oscillator used as system clock\n10: PLL used as system clock\n11: not applicable\nBits 1:0 SW: System clock switch\nSet and cleared by software to select SYSCLK source.\nSet by hardware to force HSI selection when leaving Stop and Standby mode or in case of\nfailure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security\nSystem is enabled).\n00: HSI selected as system clock\n01: HSE selected as system clock\n10: PLL selected as system clock\n11: not allowed\n100/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\n7.3.3\nClock interrupt register (RCC_CIR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\nCSSC\nReserved\nReserved\nw\n15\n14\n13\nReserved\n12 11 10 9 8 PLL\nRDYIE HSE\nRDYIE HSI\nRDYIE LSE\nRDYIE LSI\nRDYIE\n7\nCSSF\nrw rw rw rw rw r\n6\n5\nReserved\n20 19 18 17 16\nPLL\nRDYC HSE\nRDYC HSI\nRDYC LSE\nRDYC LSI\nRDYC\nw w w w w\n4 3 2 1 0\nPLL\nRDYF HSE\nRDYF HSI\nRDYF LSE\nRDYF LSI\nRDYF\nr r r r r\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBits 22:21\nReserved, must be kept at reset value.\nBit 20 PLLRDYC: PLL ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: PLLRDYF cleared\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: HSERDYF cleared\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set software to clear the HSIRDYF flag.\n0: No effect\n1: HSIRDYF cleared\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: LSERDYF cleared\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: LSIRDYF cleared\nBits 15:13\nReserved, must be kept at reset value.\nDoc ID 13902 Rev 14\n101/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nBit 12 PLLRDYIE: PLL ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the external 4-16 MHz\noscillator stabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\nBit 10 HSIRDYIE: HSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC\noscillator stabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the external 32 kHz\noscillator stabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by internal RC 40 kHz\noscillator stabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nBit 7 CSSF: Clock security system interrupt flag\nSet by hardware when a failure is detected in the external 4-16 MHz oscillator.\nCleared by software setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBits 6:5\nReserved, must be kept at reset value.\nBit 4 PLLRDYF: PLL ready interrupt flag\nSet by hardware when the PLL locks and PLLRDYDIE is set.\nCleared by software setting the PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\nBit3 HSERDYF: HSE ready interrupt flag\nSet by hardware when External High Speed clock becomes stable and HSERDYDIE is set.\nCleared by software setting the HSERDYC bit.\n0: No clock ready interrupt caused by the external 4-16 MHz oscillator\n1: Clock ready interrupt caused by the external 4-16 MHz oscillator\nBit 2 HSIRDYF: HSI ready interrupt flag\nSet by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is\nset.\nCleared by software setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the internal 8 MHz RC oscillator\n1: Clock ready interrupt caused by the internal 8 MHz RC oscillator\n102/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 1 LSERDYF: LSE ready interrupt flag\nSet by hardware when the External Low Speed clock becomes stable and LSERDYDIE is\nset.\nCleared by software setting the LSERDYC bit.\n0: No clock ready interrupt caused by the external 32 kHz oscillator\n1: Clock ready interrupt caused by the external 32 kHz oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nSet by hardware when the internal low speed clock becomes stable and LSIRDYDIE is set.\nCleared by software setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the internal RC 40 kHz oscillator\n1: Clock ready interrupt caused by the internal RC 40 kHz oscillator\n7.3.4\nAPB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x0C\nReset value: 0x00000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\nReserved\n21 20 19\nTIM11\nRST TIM10\nRST TIM9\nRST\nrw rw rw\n18\n17\n16\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nADC3\nRST USART1\nRST TIM8\nRST SPI1\nRST TIM1\nRST ADC2\nRST ADC1\nRST IOPG\nRST IOPF\nRST IOPE\nRST IOPD\nRST IOPC\nRST IOPB\nRST IOPA\nRST Res. AFIO\nRST\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw Res. rw\nBits 31:22\nReserved, must be kept at reset value.\nBit 21 TIM11RST: TIM11 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM11 timer\nBit 20 TIM10RST: TIM10 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM10 timer\nBit 19 TIM9RST: TIM9 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM9 timer\nBits 18:16\nReserved, always read as 0.\nBit 15 ADC3RST: ADC3 interface reset\nSet and cleared by software.\n0: No effect\n1: Reset ADC3 interface\nDoc ID 13902 Rev 14\n103/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nBit 14 USART1RST: USART1 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART1\nBit 13 TIM8RST: TIM8 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM8 timer\nBit 12 SPI1RST: SPI1 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI1\nBit 11 TIM1RST: TIM1 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM1 timer\nBit 10 ADC2RST: ADC 2 interface reset\nSet and cleared by software.\n0: No effect\n1: Reset ADC 2 interface\nBit 9 ADC1RST: ADC 1 interface reset\nSet and cleared by software.\n0: No effect\n1: Reset ADC 1 interface\nBit 8 IOPGRST: IO port G reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port G\nBit 7 IOPFRST: IO port F reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port F\nBit 6 IOPERST: IO port E reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port E\nBit 5 IOPDRST: IO port D reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port D\nBit 4 IOPCRST: IO port C reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port C\n104/1096\nDoc ID 13902 Rev 14\nRM0008 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 3 IOPBRST: IO port B reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port B\nBit 2 IOPARST: IO port A reset\nSet and cleared by software.\n0: No effect\n1: Reset IO port A\nBit 1\nReserved, must be kept at reset value.\nBit 0 AFIORST: Alternate function IO reset\nSet and cleared by software.\n0: No effect\n1: Reset Alternate Function\nDoc ID 13902 Rev 14\n105/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\n7.3.5\nRM0008\nAPB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\nReserved\n15 14\nSPI3\nRST SPI2\nRST\nrw rw\n29 28 27\nDAC\nRST PWR\nRST BKP\nRST\nrw rw rw\n13 12 11\nReserved\nWWD\nGRST\n26 25\nRes. CAN\nRST\n24 23 22 21 20 19 18 17 16\nRes. USB\nRST I2C2\nRST I2C1\nRST UART\n5\nRST UART\n4\nRST USART\n3\nRST USART\n2\nRST Res.\nrw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0\nTIM14\nRST TIM13\nRST TIM12\nRST TIM7\nRST TIM6\nRST TIM5\nRST TIM4\nRST TIM3\nRST TIM2\nRST\nrw rw rw rw rw rw rw rw rw\nrw\n10\n9\nReserved\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACRST: DAC interface reset\nSet and cleared by software.\n0: No effect\n1: Reset DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: No effect\n1: Reset power interface\nBit 27 BKPRST: Backup interface reset\nSet and cleared by software.\n0: No effect\n1: Reset backup interface\nBit 26 Reserved, must be kept at reset value.\nBit 25 CANRST: CAN reset\nSet and cleared by software.\n0: No effect\n1: Reset CAN\nBit 24 Reserved, always read as 0.\nBit 23 USBRST: USB reset\nSet and cleared by software.\n0: No effect\n1: Reset USB\nBit 22 I2C2RST: I2C2 reset\nSet and cleared by software.\n0: No effect\n1: Reset I2C2\n106/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: No effect\n1: Reset I2C1\nBit 20 UART5RST: USART5 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART5\nBit 19 UART4RST: USART4 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART4\nBit 18 USART3RST: USART3 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART3\nBit 17 USART2RST: USART2 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART2\nBit 16 Reserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI2\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: No effect\n1: Reset window watchdog\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14RST: TIM14 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM14\nBit 7 TIM13RST: TIM13 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM13\nDoc ID 13902 Rev 14\n107/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nBit 6 TIM12RST: TIM12 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM12\nBit 5 TIM7RST: TIM7 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM7\nBit 4 TIM6RST: TIM6 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM6\nBit 3 TIM5RST: TIM5 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM5\nBit 2 TIM4RST: TIM4 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM4\nBit 1 TIM3RST: TIM3 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM3\nBit 0 TIM2RST: TIM2 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM2\n7.3.6\nAHB peripheral clock enable register (RCC_AHBENR)\nAddress offset: 0x14\nReset value: 0x0000 0014\nAccess: no wait state, word, half-word and byte access\nNote:\n31\nWhen the peripheral clock is not active, the peripheral register values may not be readable\nby software and the returned value is always 0x0.\n30\n29\n28\n27\n26\n25\n24\n23\n22 21\n20 19 6\n18\n17\n16\n5 4 3 2 1 0\nRes. FLITF\nEN Res. SRAM\nEN DMA2\nEN DMA1\nEN\nrw rw rw\nReserved\n15\n14\n13\nReserved\n12\n11\n10\nSDIO\nEN\nrw\n9 8\nRes. FSMC\nEN\n7\nRes.\nrw\nCRCE\nN\nrw\nBits 31:11 Reserved, must be kept at reset value.\n108/1096\nDoc ID 13902 Rev 14\nrw RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 10 SDIOEN: SDIO clock enable\nSet and cleared by software.\n0: SDIO clock disabled\n1: SDIO clock enabled\nBits 9\nReserved, always read as 0.\nBit 8 FSMCEN: FSMC clock enable\nSet and cleared by software.\n0: FSMC clock disabled\n1: FSMC clock enabled\nBit 7\nReserved, always read as 0.\nBit 6 CRCEN: CRC clock enable\nSet and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBit 5 Reserved, must be kept at reset value.\nBit 4 FLITFEN: FLITF clock enable\nSet and cleared by software to disable/enable FLITF clock during Sleep mode.\n0: FLITF clock disabled during Sleep mode\n1: FLITF clock enabled during Sleep mode\nBit 3 Reserved, must be kept at reset value.\nBit 2 SRAMEN: SRAM interface clock enable\nSet and cleared by software to disable/enable SRAM interface clock during Sleep mode.\n0: SRAM interface clock disabled during Sleep mode.\n1: SRAM interface clock enabled during Sleep mode\nBit 1 DMA2EN: DMA2 clock enable\nSet and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\nBit 0 DMA1EN: DMA1 clock enable\nSet and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\n7.3.7\nAPB2 peripheral clock enable register (RCC_APB2ENR)\nAddress: 0x18\nReset value: 0x0000 0000\nAccess: word, half-word and byte access\nNo wait states, except if the access occurs while an access to a peripheral in the APB2\ndomain is on going. In this case, wait states are inserted until the access to APB2 peripheral\nis finished.\nNote:\nWhen the peripheral clock is not active, the peripheral register values may not be readable\nby software and the returned value is always 0x0.\nDoc ID 13902 Rev 14\n109/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\nReserved\nRM0008\n21 20 19\nTIM11\nEN TIM10\nEN TIM9\nEN\nrw rw rw\n18\n17\n16\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nADC3\nEN USAR\nT1EN TIM8\nEN SPI1\nEN TIM1\nEN ADC2\nEN ADC1\nEN IOPG\nEN IOPF\nEN IOPE\nEN IOPD\nEN IOPC\nEN IOPB\nEN IOPA\nEN Res. AFIO\nEN\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:22 Reserved, must be kept at reset value.\nBit 21 TIM11EN: TIM11 timer clock enable\nSet and cleared by software.\n0: TIM11 timer clock disabled\n1: TIM11 timer clock enabled\nBit 20 TIM10EN: TIM10 timer clock enable\nSet and cleared by software.\n0: TIM10 timer clock disabled\n1: TIM10 timer clock enabled\nBit 19 TIM9EN: TIM9 timer clock enable\nSet and cleared by software.\n0: TIM9 timer clock disabled\n1: TIM9 timer clock enabled\nBits 18:16 Reserved, always read as 0.\nBit 15 ADC3EN: ADC3 interface clock enable\nSet and cleared by software.\n0: ADC3 interface clock disabled\n1: ADC3 interface clock enabled\nBit 14 USART1EN: USART1 clock enable\nSet and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBit 13 TIM8EN: TIM8 Timer clock enable\nSet and cleared by software.\n0: TIM8 timer clock disabled\n1: TIM8 timer clock enabled\nBit 12 SPI1EN: SPI1 clock enable\nSet and cleared by software.\n0: SPI1 clock disabled\n1: SPI1 clock enabled\nBit 11 TIM1EN: TIM1 timer clock enable\nSet and cleared by software.\n0: TIM1 timer clock disabled\n1: TIM1 timer clock enabled\n110/1096\nDoc ID 13902 Rev 14\nrw RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 10 ADC2EN: ADC 2 interface clock enable\nSet and cleared by software.\n0: ADC 2 interface clock disabled\n1: ADC 2 interface clock enabled\nBit 9 ADC1EN: ADC 1 interface clock enable\nSet and cleared by software.\n0: ADC 1 interface disabled\n1: ADC 1 interface clock enabled\nBit 8 IOPGEN: IO port G clock enable\nSet and cleared by software.\n0: IO port G clock disabled\n1: IO port G clock enabled\nBit 7 IOPFEN: IO port F clock enable\nSet and cleared by software.\n0: IO port F clock disabled\n1: IO port F clock enabled\nBit 6 IOPEEN: IO port E clock enable\nSet and cleared by software.\n0: IO port E clock disabled\n1: IO port E clock enabled\nBit 5 IOPDEN: IO port D clock enable\nSet and cleared by software.\n0: IO port D clock disabled\n1: IO port D clock enabled\nBit 4 IOPCEN: IO port C clock enable\nSet and cleared by software.\n0: IO port C clock disabled\n1: IO port C clock enabled\nBit 3 IOPBEN: IO port B clock enable\nSet and cleared by software.\n0: IO port B clock disabled\n1: IO port B clock enabled\nBit 2 IOPAEN: IO port A clock enable\nSet and cleared by software.\n0: IO port A clock disabled\n1: IO port A clock enabled\nBit 1 Reserved, must be kept at reset value.\nBit 0 AFIOEN: Alternate function IO clock enable\nSet and cleared by software.\n0: Alternate Function IO clock disabled\n1: Alternate Function IO clock enabled\n7.3.8\nAPB1 peripheral clock enable register (RCC_APB1ENR)\nAddress: 0x1C\nReset value: 0x0000 0000\nDoc ID 13902 Rev 14\n111/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nAccess: word, half-word and byte access\nNo wait state, except if the access occurs while an access to a peripheral on APB1 domain\nis on going. In this case, wait states are inserted until this access to APB1 peripheral is\nfinished.\nNote:\n31\nWhen the peripheral clock is not active, the peripheral register values may not be readable\nby software and the returned value is always 0x0.\n30\nReserved\n15 14\nSPI3\nEN SPI2\nEN\nrw rw\n29 28 27\nDAC\nEN PWR\nEN BKP\nEN\nrw rw rw\n13 12 11\nReserved\nWWD\nGEN\n26\nRes.\n25\nCAN\nEN\n24\n23 22 21 20 19 18 17 USB\nEN I2C2\nEN I2C1\nEN UART5E\nN UART4\nEN USART\n3EN USART\n2EN rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0\nTIM14\nEN TIM13\nEN TIM12\nEN TIM7\nEN TIM6\nEN TIM5\nEN TIM4\nEN TIM3\nEN TIM2\nEN\nrw rw rw rw rw rw rw rw rw\nRes.\nrw\n10\n9\nReserved\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACEN: DAC interface clock enable\nSet and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nSet and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 BKPEN: Backup interface clock enable\nSet and cleared by software.\n0: Backup interface clock disabled\n1: Backup interface clock enabled\nBit 26 Reserved, must be kept at reset value.\nBit 25 CANEN: CAN clock enable\nSet and cleared by software.\n0: CAN clock disabled\n1: CAN clock enabled\nBit 24 Reserved, always read as 0.\nBit 23 USBEN: USB clock enable\nSet and cleared by software.\n0: USB clock disabled\n1: USB clock enabled\nBit 22 I2C2EN: I2C2 clock enable\nSet and cleared by software.\n0: I2C2 clock disabled\n1: I2C2 clock enabled\n112/1096\nDoc ID 13902 Rev 14\n16\nRes. RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nBit 21 I2C1EN: I2C1 clock enable\nSet and cleared by software.\n0: I2C1 clock disabled\n1: I2C1 clock enabled\nBit 20 UART5EN: USART5 clock enable\nSet and cleared by software.\n0: USART5 clock disabled\n1: USART5 clock enabled\nBit 19 UART4EN: USART4 clock enable\nSet and cleared by software.\n0: USART4 clock disabled\n1: USART4 clock enabled\nBit 18 USART3EN: USART3 clock enable\nSet and cleared by software.\n0: USART3 clock disabled\n1: USART3 clock enabled\nBit 17 USART2EN: USART2 clock enable\nSet and cleared by software.\n0: USART2 clock disabled\n1: USART2 clock enabled\nBits 16 Reserved, always read as 0.\nBit 15 SPI3EN: SPI 3 clock enable\nSet and cleared by software.\n0: SPI 3 clock disabled\n1: SPI 3 clock enabled\nBit 14 SPI2EN: SPI2 clock enable\nSet and cleared by software.\n0: SPI2 clock disabled\n1: SPI2 clock enabled\nBits 13:12 Reserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nSet and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBits 10:9 Reserved, must be kept at reset value.\nBit 8 TIM14EN: TIM14 timer clock enable\nSet and cleared by software.\n0: TIM14 clock disabled\n1: TIM14 clock enabled\nBit 7 TIM13EN: TIM13 timer clock enable\nSet and cleared by software.\n0: TIM13 clock disabled\n1: TIM13 clock enabled\nDoc ID 13902 Rev 14\n113/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nBit 6 TIM12EN: TIM12 timer clock enable\nSet and cleared by software.\n0: TIM12 clock disabled\n1: TIM12 clock enabled\nBit 5 TIM7EN: TIM7 timer clock enable\nSet and cleared by software.\n0: TIM7 clock disabled\n1: TIM7 clock enabled\nBit 4 TIM6EN: TIM6 timer clock enable\nSet and cleared by software.\n0: TIM6 clock disabled\n1: TIM6 clock enabled\nBit 3 TIM5EN: TIM5 timer clock enable\nSet and cleared by software.\n0: TIM5 clock disabled\n1: TIM5 clock enabled\nBit 2 TIM4EN: TIM4 timer clock enable\nSet and cleared by software.\n0: TIM4 clock disabled\n1: TIM4 clock enabled\nBit 1 TIM3EN: TIM3 timer clock enable\nSet and cleared by software.\n0: TIM3 clock disabled\n1: TIM3 clock enabled\nBit 0 TIM2EN: TIM2 timer clock enable\nSet and cleared by software.\n0: TIM2 clock disabled\n1: TIM2 clock enabled\n114/1096\nDoc ID 13902 Rev 14\nRM0008 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\n7.3.9\nBackup domain control register (RCC_BDCR)\nAddress offset: 0x20\nReset value: 0x0000 0000, reset by Backup domain Reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\nNote:\n31\nThe LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register\n(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-\nprotected and the DBP bit in the Power control register (PWR_CR) has to be set before\nthese can be modified. Refer to Section 5 on page 44 for further information. These bits are\nonly reset after a Backup domain Reset (see Section 7.1.3: Backup domain reset). Any\ninternal or external Reset will not have any effect on these bits.\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBDRST\nReserved\nrw\n15\n14\n13\nRTC\nEN\n12\n11\n10\n9\n8\n7\n6\n5\nRTCSEL[1:0]\nReserved\nrw\nReserved\nrw\nrw\n4\n3\n2 1 0\nLSE\nBYP LSE\nRDY LSEON\nrw r rw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nSet and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\nBit 15 RTCEN: RTC clock enable\nSet and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10\nReserved, must be kept at reset value.\nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nSet by software to select the clock source for the RTC. Once the RTC clock source has been\nselected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit\ncan be used to reset them.\n00: No clock\n01: LSE oscillator clock used as RTC clock10: LSI oscillator clock used as RTC clock\n11: HSE oscillator clock divided by 128 used as RTC clock\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 LSEBYP: External low-speed oscillator bypass\nSet and cleared by software to bypass oscillator in debug mode. This bit can be written only\nwhen the external 32 kHz oscillator is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nDoc ID 13902 Rev 14\n115/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nBit 1 LSERDY: External low-speed oscillator ready\nSet and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After\nthe LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock\ncycles.\n0: External 32 kHz oscillator not ready\n1: External 32 kHz oscillator ready\nBit 0 LSEON: External low-speed oscillator enable\nSet and cleared by software.\n0: External 32 kHz oscillator OFF\n1: External 32 kHz oscillator ON\n116/1096\nDoc ID 13902 Rev 14 RM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\n7.3.10\nControl/status register (RCC_CSR)\nAddress: 0x24\nReset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in case of successive accesses to this register.\n31 30 29 28 27 26 25\nLPWR\nRSTF WWDG\nRSTF IWDG\nRSTF SFT\nRSTF POR\nRSTF PIN\nRSTF Res.\nrw rw rw rw rw rw 15 14 13 12 11 10\n24\n23\n22\n21\n20\n19\n18 17 16\n2 1 0\nLSI\nRDY LSION\nr rw\nRMVF\nReserved\nrw\n9\n8\n7\n6\n5\nReserved\n4\n3\nBit 31 LPWRRSTF: Low-power reset flag\nSet by hardware when a Low-power management reset occurs.\nCleared by writing to the RMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Low-power management\nreset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nSet by hardware when a window watchdog reset occurs.\nCleared by writing to the RMVF bit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nSet by hardware when an independent watchdog reset from V DD domain occurs.\nCleared by writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\nBit 28 SFTRSTF: Software reset flag\nSet by hardware when a software reset occurs.\nCleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nSet by hardware when a POR/PDR reset occurs.\nCleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nDoc ID 13902 Rev 14\n117/1096 Low-, medium-, high- and XL-density reset and clock control (RCC)\nRM0008\nBit 26 PINRSTF: PIN reset flag\nSet by hardware when a reset from the NRST pin occurs.\nCleared by writing to the RMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25\nReserved, must be kept at reset value.\nBit 24 RMVF: Remove reset flag\nSet by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\nBits 23:2\nReserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low-speed oscillator ready\nSet and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.\nAfter the LSION bit is cleared, LSIRDY goes low after 3 internal RC 40 kHz oscillator clock\ncycles.\n0: Internal RC 40 kHz oscillator not ready\n1: Internal RC 40 kHz oscillator ready\nBit 0 LSION: Internal low-speed oscillator enable\nSet and cleared by software.\n0: Internal RC 40 kHz oscillator OFF\n1: Internal RC 40 kHz oscillator ON\n118/1096\nDoc ID 13902 Rev 14 0x24\nRCC_CSR\nReset value\nRCC_BDCR\nReset value\n0 0 0 0 1 1\nReserved\nReset value\n0 0 0\nReserved\n0 0 0 0 0 0 0\nDoc ID 13902 Rev 14\n0 0\n0 0 0 0 0 0\n0 0\nReserved\nReserved\n0\n0\nRTC\nSEL\n[1:0]\n0\n0\n0 0 0 0 0\n0\n1\n0 0 0 0 0 0\n0 0 0 0 0\nReserved\n0 0 0\nSWS\n[1:0] SW\n[1:0]\n0 0 0 0 0\n0 0 0 0 0 0 0 0 0\n0\n0\n0\n1 0 0\n0\n0\nHPRE[3:0]\nTIM2EN\n0 0\n0\n0 0\n0\n0 0 0\n0\n0\n0 0\nPPRE1\n[2:0]\n1\nTIM3EN 0 0 0\n0\nIOPCEN 0\n0\nReser\nved\nFSMCEN\n0\nIOPDEN 0\n0\nIOPEEN\n0\nReset value\n0\n0 0 0\n0\n0\n0 0 0 0\nPPRE2\n[2:0]\nReserved\nSDIOEN\n0\n0\nReserved\n0\n0 0 0\nReserved\n0\n0\n0\n0 0\n0\n0 0 0 0\n0\n0 0 0 SPI2RST PLLMUL[3:0] ADC\nPRE\n[1:0]\n0 0\n0\n0 0\nReserved\n0 0 0 0\nReserved\n0\nReserved\n0 0 0 0\nReset value\nReserved\n0\n0\nRCC_AHBENR\n0 0\n0\n0\nHSITRIM[4:0]\n0\nReset value\n0\nHSICAL[7:0]\n0\n0\n0\nReserved\n0\n0\nRCC_APB2ENR\nMCO [2:0]\n0\n0\nRCC_APB2RSTR\n0\nReset value\nRCC_CIR\nReset value\n0\nReserved\nRCC_APB1ENR\nReset value\nRCC_APB1RSTR\nReset value\n0x20\nReserved\n0x1C\nReserved\n0x18\n0x14\n0x010\nRCC_CFGR\n0x0C\nRCC_CR\n0x08\n0x04\n0x00\nRegister\nOffset\nTable 18.\n7.3.11\nRM0008\nLow-, medium-, high- and XL-density reset and clock control (RCC)\nRCC register map\nThe following table gives the RCC register map and the reset values.\nRCC register map and reset values\n1 1\n0\n0\n0\n0 0 0 0\n0 0\nRefer to Table 1 on page 24 for the register boundary addresses.\n119/1096 Connectivity line devices: reset and clock control (RCC)\n8\nRM0008\nConnectivity line devices: reset and clock control\n(RCC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis Section applies to all connectivity line devices, unless otherwise specified.\n8.1\nReset\nThere are three types of reset, defined as system reset, power reset and backup domain\nreset.\n8.1.1\nSystem reset\nA system reset sets all registers to their reset values except the reset flags in the clock\ncontroller CSR register and the registers in the Backup domain (see Figure 4).\nA system reset is generated when one of the following events occurs:\n1. A low level on the NRST pin (external reset)\n2. Window watchdog end of count condition (WWDG reset)\n3. Independent watchdog end of count condition (IWDG reset)\n4. A software reset (SW reset) (see Software reset)\n5. Low-power management reset (see Low-power management reset)\nThe reset source can be identified by checking the reset flags in the Control/Status register,\nRCC_CSR (see Section 8.3.10: Control/status register (RCC_CSR)).\nSoftware reset\nThe SYSRESETREQ bit in Cortex™-M3 Application Interrupt and Reset Control Register\nmust be set to force a software reset on the device. Refer to the STM32F10xxx Cortex-M3\nprogramming manual (see Related documents on page 1) for more details.\n120/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nLow-power management reset\nThere are two ways to generate a low-power management reset:\n1.\nReset generated when entering Standby mode:\nThis type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this\ncase, whenever a Standby mode entry sequence is successfully executed, the device\nis reset instead of entering Standby mode.\n2.\nReset when entering Stop mode:\nThis type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this\ncase, whenever a Stop mode entry sequence is successfully executed, the device is\nreset instead of entering Stop mode.\nFor further information on the User Option Bytes, refer to the STM32F10xxx Flash\nprogramming manual.\n8.1.2\nPower reset\nA power reset is generated when one of the following events occurs:\n1. Power-on/power-down reset (POR/PDR reset)\n2. When exiting Standby mode\nA power reset sets all registers to their reset values except the Backup domain (see\nFigure 4)\nThese sources act on the NRST pin and it is always kept low during the delay phase. The\nRESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more\ndetails, refer to Table 63: Vector table for other STM32F10xxx devices on page 196.\nThe system reset signal provided to the device is output on the NRST pin. The pulse\ngenerator guarantees a minimum reset pulse duration of 20 µs for each reset source\n(external or internal reset). In case of an external reset, the reset pulse is generated while\nthe NRST pin is asserted low.\nFigure 10. Simplified diagram of the reset circuit\n6 $$ \u000f6 $$!\n2 05\n%XTERNAL\nRESET\n&ILTER\n3YSTEM Connectivity line devices: reset and clock control (RCC)\n8.1.3\nRM0008\nBackup domain reset\nThe backup domain has two specific resets that affect only the backup domain (see\nFigure 4).\nA backup domain reset is generated when one of the following events occurs:\n8.2\n1. Software reset, triggered by setting the BDRST bit in the Backup domain control\nregister (RCC_BDCR).\n2. V DD or V BAT power on, if both supplies have previously been powered off.\nClocks\nThree different clock sources can be used to drive the system clock (SYSCLK):\n● HSI oscillator clock\n● HSE oscillator clock\n● PLL clock\nThe devices have the following two secondary clock sources:\n● 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and\noptionally the RTC used for Auto-wakeup from Stop/Standby mode.\n● 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-\ntime clock (RTCCLK)\nEach clock source can be switched on or off independently when it is not used, to optimize\npower consumption.\n122/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nFigure 11. Clock tree\n40 kHz\nLSI\nRC\nOSC32_IN\nOSC32_OUT\nto independent watchdog\nIWDGCLK\nLSI\n32.768 kHz\nLSE\nOSC\nto RTC\nLSE\nRTCCLK\n/128\nCSS\nRTCSEL[1:0]\nHSE\nto Flash prog. IF\nXT1 to MCO\nOSC_IN\nOSC_OUT\nFLITFCLK\nHSI\n8 MHz\nHSI RC\nSYSCLK\nsystem clock\nPLLMUL\n/2\n3-25 MHz\nHSE\nOSC\nx4, x5,... x9, PLLCLK\nx6.5\n/1,2,3....\n..../15, /16\nSW\nPLLVCO (2 × PLLCLK)\nUSB prescaler\nPLLSCR\nPREDIV1\nPREDIV1SCR\n/2,3\nOTGFSCLK\nPLL2MUL\n48 MHz\nto USB OTG FS\nx8, x9,... x14,\nx16, x20\nto I2S2 interface\nPREDIV2\n/1,2,3....\n..../15, /16\nPLL3MUL PLL2CLK\nto MCO\nto I2S3 interface\nx8, x9,... x14, PLL3VCO\n(2 × PLL3CLK)\nx16, x20\nPLL3CLK to MCO\nMCO[3:0]\nHCLK to AHB bus, core memory and DMA\nHSE\nHSI\nMCO\n/8\nto Cortex System timer\nFCLK Cortex free running clock\nPLLCLK/2\nPLL2CLK\nPLL3CLK/2\nPLL3CLK\nXT1\nAPB1 prescaler\n/1, 2, 4, 8, 16\nSYSCLK\n72 MHz max.\n(see note1)\n36 MHz max\nPeripheral clock enable\nPCLK1\nto APB1 peripherals\nto TIM2,3,4,5,\n6 & 7\nTIM2,3,4,5,6,7\nIf(APB1 prescaler =1) x1\nelse x2\nAHB prescaler\n/1,/2 ../512\nTIMxCLK\nPeripheral clock enable\nAPB2 prescaler\n/1, 2, 4, 8, 16\n72 MHz max\nPeripheral clock enable\nPCLK2\nto APB2 peripherals\nEthernet\nPHY\nTIM1\nIf(APB2 prescaler =1) x1\nelse x2\nMACTXCLK\nETH_MII_TX_CLK\n/2, /20\nETH_MII_RX_CLK\nMII_RMII_SEL\nin AFIO_MAPR\nMACRXCLK\nto TIM1\nTIMxCLK\nPeripheral clock enable\nto Ethernet MAC\nADC prescaler\n/2, 4, 6, 8\nADCCLK\n14 MHz max\nto ADC1,2\nMACRMIICLK\nai15699d\n1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is\n36 MHz.\n2. For full details about the internal and external clock source characteristics, please refer to the “Electrical\ncharacteristics” section in your device datasheet.\nThe advanced clock controller features 3 PLLs to provide a high degree of flexibility to the\napplication in the choice of the external crystal or oscillator to run the core and peripherals\nat the highest frequency and guarantee the appropriate frequency for the Ethernet and USB\nOTG FS.\nA single 25 MHz crystal can clock the entire system and all peripherals including the\nEthernet and USB OTG FS peripherals. In order to achieve high-quality audio performance,\nan audio crystal can be used. In this case, the I2S master clock can generate all standard\nsampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.\nFor more details about clock configuration for applications requiring Ethernet, USB OTG FS\nand/or I 2 S (audio), please refer to \"Appendix A Applicative block diagrams\" in your\nconnectivity line device datasheet.\nDoc ID 13902 Rev 14\n123/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nSeveral prescalers allow the configuration of the AHB frequency, the high speed APB\n(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and\nthe APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is\n36 MHz.\nAll peripheral clocks are derived from the system clock (SYSCLK) except:\n● The Flash memory programming interface clock (FLITFCLK) is always the HSI clock\n● The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock (2 ×\nPLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is\nmade through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS\noperation, the PLL should be configured to output 72 MHz or 48 MHz.\n● The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the\nPLL3 VCO clock (2 × PLL3CLK). This selection is made through the I2SxSRC bit in the\nRCC_CFGR2 register. For more information on PLL3 and how to configure the I2S\nclock to achieve high-quality audio performance, please refer to Section 25.4.3: Clock\ngenerator.\n● The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external\nPHY. For further information on the Ethernet configuration, please refer to\nSection 29.4.4: MII/RMII selection.\nWhen the Ethernet is used, the AHB clock frequency must be at least 25 MHz.\nThe RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock\n(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock\n(HCLK), configurable in the SysTick Control and Status Register. The ADCs are clocked by\nthe clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.\nThe timer clock frequencies are automatically fixed by hardware. There are two cases:\n1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as\nthat of the APB domain to which the timers are connected.\n2. otherwise, they are set to twice (×2) the frequency of the APB domain to which the\ntimers are connected.\nFCLK acts as Cortex™-M3’s free-running clock. For more details refer to the ARM Cortex™-\nM3 r1p1 Technical Reference Manual (TRM).\n8.2.1\nHSE clock\nThe high speed external clock signal (HSE) can be generated from two possible clock\nsources:\n● HSE external crystal/ceramic resonator\n● HSE user external clock\nThe resonator and the load capacitors have to be placed as close as possible to the\noscillator pins in order to minimize output distortion and startup stabilization time. The\nloading capacitance values must be adjusted according to the selected oscillator.\n124/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nFigure 12. HSE/ LSE clock sources\nClock source\nHardware configuration\nOSC_OUT\nExternal clock\n(HiZ)\nExternal\nsource\nOSC_IN OSC_OUT\nCrystal/ceramic\nresonators\nC L1\nLoad\ncapacitors\nC L2\nExternal source (HSE bypass)\nIn this mode, an external clock source must be provided. It can have a frequency of up to\n50 MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control\nregister (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty\ncycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See\nFigure 12.\nExternal crystal/ceramic resonator (HSE crystal)\nThe 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on\nthe main clock.\nThe associated hardware configuration is shown in Figure 12. Refer to the electrical\ncharacteristics section of the datasheet for more details.\nThe HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed\nexternal oscillator is stable or not. At startup, the clock is not released until this bit is set by\nhardware. An interrupt can be generated if enabled in the Clock interrupt register\n(RCC_CIR).\nThe HSE crystal can be switched on and off using the HSEON bit in the Clock control\nregister (RCC_CR).\n8.2.2\nHSI clock\nThe HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used\ndirectly as a system clock or divided by 2 to be used as PLL input.\nThe HSI RC oscillator has the advantage of providing a clock source at low cost (no external\ncomponents). It also has a faster startup time than the HSE crystal oscillator however, even\nwith calibration the frequency is less accurate than an external crystal oscillator or ceramic\nresonator.\nDoc ID 13902 Rev 14\n125/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nCalibration\nRC oscillator frequencies can vary from one chip to another due to manufacturing process\nvariations, this is why each device is factory calibrated by ST for 1% accuracy at T A = 25 °C.\nAfter reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control\nregister (RCC_CR).\nIf the application is subject to voltage or temperature variations this may affect the RC\noscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]\nbits in the Clock control register (RCC_CR).\nThe HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or\nnot. At startup, the HSI RC output clock is not released until this bit is set by hardware.\nThe HSI RC can be switched on and off using the HSION bit in the Clock control register\n(RCC_CR).\nThe HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal\noscillator fails. Refer to Section 8.2.7: Clock security system (CSS) on page 128.\n8.2.3\nPLLs\nThe main PLL provides a frequency multiplier starting from one of the following clock\nsources:\n● HSI clock divided by 2\n● HSE or PLL2 clock through a configurable divider\nRefer to Figure 11 and Clock control register (RCC_CR).\nPLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to\nFigure 11 and Clock configuration register2 (RCC_CFGR2)\nThe configuration of each PLL (selection of clock source, predivision factor and\nmultiplication factor) must be done before enabling the PLL. Each PLL should be enabled\nafter its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters\ncan not be changed.\nWhen changing the entry clock source of the main PLL, the original clock source must be\nswitched off only after the selection of the new clock source (done through bit PLLSRC in\nthe Clock configuration register (RCC_CFGR)).\nAn interrupt can be generated when the PLL is ready if enabled in the Clock interrupt\nregister (RCC_CIR).\n8.2.4\nLSE clock\nThe LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the\nadvantage providing a low-power but highly accurate clock source to the real-time clock\nperipheral (RTC) for clock/calendar or other timing functions.\nThe LSE crystal is switched on and off using the LSEON bit in Backup domain control\nregister (RCC_BDCR).\nThe LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE\ncrystal is stable or not. At startup, the LSE crystal output clock signal is not released until\nthis bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt\nregister (RCC_CIR).\n126/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nExternal source (LSE bypass)\nIn this mode, an external clock source must be provided. It can have a frequency of up to\n1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain\ncontrol register (RCC_BDCR). The external clock signal (square, sinus or triangle) with\n~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left\nHi-Z. See Figure 12.\n8.2.5\nLSI clock\nThe LSI RC acts as an low-power clock source that can be kept running in Stop and\nStandby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The\nclock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to\nthe electrical characteristics section of the datasheets.\nThe LSI RC can be switched on and off using the LSION bit in the Control/status register\n(RCC_CSR).\nThe LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed\ninternal oscillator is stable or not. At startup, the clock is not released until this bit is set by\nhardware. An interrupt can be generated if enabled in the Clock interrupt register\n(RCC_CIR).\nLSI calibration\nThe frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to\nhave accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for\nthese peripherals) with an acceptable accuracy.\nThis calibration is performed by measuring the LSI clock frequency with respect to TIM5\ninput clock (TIM5CLK). According to this measurement done at the precision of the HSE\noscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an\naccurate time base or can compute accurate IWDG timeout.\nUse the following procedure to calibrate the LSI:\n8.2.6\n1. Enable TIM5 timer and configure channel4 in input capture mode\n2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock\ninternally to TIM5 channel4 input capture for calibration purpose.\n3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or\ninterrupt.\n4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending\non the desired time base and/or to compute the IWDG timeout.\nSystem clock (SYSCLK) selection\nAfter a system reset, the HSI oscillator is selected as system clock. When a clock source is\nused directly or through the PLL as the system clock, it is not possible to stop it.\nA switch from one clock source to another occurs only if the target clock source is ready\n(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is\nselected, the switch will occur when the clock source will be ready. Status bits in the Clock\ncontrol register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently\nused as system clock.\nDoc ID 13902 Rev 14\n127/1096 Connectivity line devices: reset and clock control (RCC)\n8.2.7\nRM0008\nClock security system (CSS)\nClock Security System can be activated by software. In this case, the clock detector is\nenabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.\na failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock\nfailure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is\ngenerated to inform the software about the failure (Clock Security System Interrupt CSSI),\nallowing the MCU to perform rescue operations. The CSSI is linked to the Cortex™-M3 NMI\n(Non-Maskable Interrupt) exception vector.\nNote:\nOnce the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is\nautomatically generated. The NMI will be executed indefinitely unless the CSS interrupt\npending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt\nby setting the CSSC bit in the Clock interrupt register (RCC_CIR).\nIf the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is\nused as PLL input clock directly or through PLL2, and the PLL clock is used as system\nclock), a detected failure causes a switch of the system clock to the HSI oscillator and the\ndisabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the\nclock entry of the PLL (directly or through PLL2) used as system clock when the failure\noccurs, the PLL is disabled too.\n8.2.8\nRTC clock\nThe RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected\nby programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).\nThis selection cannot be modified without resetting the Backup domain.\nThe LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.\nConsequently:\n●\nIf LSE is selected as RTC clock:\n–\n●\nIf LSI is selected as Auto-Wakeup unit (AWU) clock:\n–\n●\n8.2.9\nThe RTC continues to work even if the V DD supply is switched off, provided the\nV BAT supply is maintained.\nThe AWU state is not guaranteed if the V DD supply is powered off. Refer to\nSection 8.2.5: LSI clock on page 127 for more details on LSI calibration.\nIf the HSE clock divided by 128 is used as RTC clock:\n– The RTC state is not guaranteed if the V DD supply is powered off or if the internal\nvoltage regulator is powered off (removing power from the 1.8 V domain).\n– The DPB bit (Disable backup domain write protection) in the Power controller\nregister must be set to 1 (refer to Section 5.4.1: Power control register\n(PWR_CR)).\nWatchdog clock\nIf the Independent watchdog (IWDG) is started by either hardware option or software\naccess, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator\ntemporization, the clock is provided to the IWDG.\n128/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\n8.2.10\nClock-out capability\nThe microcontroller clock output (MCO) capability allows the clock to be output onto the\nexternal MCO pin. The configuration registers of the corresponding GPIO port must be\nprogrammed in alternate function mode. One of 8 clock signals can be selected as the MCO\nclock.\n● SYSCLK\n● HSI\n● HSE\n● PLL clock divided by 2 selected\n● PLL2 clock selected\n● PLL3 clock divided by 2 selected\n● XT1 external 3-25 MHz oscillator clock selected (for Ethernet)\n● PLL3 clock selected (for Ethernet)\nThe selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed).\nThe selection is controlled by the MCO[3:0] bits of the Clock configuration register\n(RCC_CFGR).\n8.3\nRCC registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\n8.3.1\nClock control register (RCC_CR)\nAddress offset: 0x00\nReset value: 0x0000 XX83 where X is undefined.\nAccess: no wait state, word, half-word and byte access\n31\n30\nReserved\n29 28 27 26\nPLL3\nRDY PLL3\nON PLL2\nRDY PLL2\nON\n25\n24\n23\n22\n21\n20\nPLLRDY PLLON\n19\n18\n17\n16\nCSSON HSEBYP HSERDY HSEON\nReserved\nr rw r rw r rw 15 14 13 12 11 10 9 8 7 6\nr r r r r r rw rw\nHSICAL[7:0]\nrw rw r rw\n4 3 2 1 0\nHSIRDY HSION\nrw rw r rw\n5\nHSITRIM[4:0]\nRes.\nBits 31:30\nr\nr\nrw\nReserved, must be kept at reset value.\nBit 29 PLL3RDY: PLL3 clock ready flag\nSet by hardware to indicate that the PLL3 is locked.\n0: PLL3 unlocked\n1: PLL3 locked\nBit 28 PLL3ON: PLL3 enable\nSet and cleared by software to enable PLL3.\nCleared by hardware when entering Stop or Standby mode.\n0: PLL3 OFF\n1: PLL3 ON\nDoc ID 13902 Rev 14\n129/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBit 27 PLL2RDY: PLL2 clock ready flag\nSet by hardware to indicate that the PLL2 is locked.\n0: PLL2 unlocked\n1: PLL2 locked\nBit 26 PLL2ON: PLL2 enable\nSet and cleared by software to enable PLL2.\nCleared by hardware when entering Stop or Standby mode. This bit can not be cleared if\nthe PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is\nused as system clock).\n0: PLL2 OFF\n1: PLL2 ON\nBit 25 PLLRDY: PLL clock ready flag\nSet by hardware to indicate that the PLL is locked.\n0: PLL unlocked\n1: PLL locked\nBit 24 PLLON: PLL enable\nSet and cleared by software to enable PLL.\nCleared by hardware when entering Stop or Standby mode. This bit can not be reset if the\nPLL clock is used as system clock or is selected to become the system clock. Software\nmust disable the USB OTG FS clock before clearing this bit.\n0: PLL OFF\n1: PLL ON\nBits 23:20\nReserved, must be kept at reset value.\nBit 19 CSSON: Clock security system enable\nSet and cleared by software to enable the clock security system. When CSSON is set, the\nclock detector is enabled by hardware when the HSE oscillator is ready, and disabled by\nhardware if a HSE clock failure is detected.\n0: Clock detector OFF\n1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not)\nBit 18 HSEBYP: External high-speed clock bypass\nSet and cleared by software to bypass the oscillator with an external clock. The external\nclock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit\ncan be written only if the HSE oscillator is disabled.\n0: external 3-25 MHz oscillator not bypassed\n1: external 3-25 MHz oscillator bypassed with external clock\nBit 17 HSERDY: External high-speed clock ready flag\nSet by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the\nHSE oscillator clock to fall down after HSEON reset.\n0: HSE oscillator not ready\n1: HSE oscillator ready\nBit 16 HSEON: HSE clock enable\nSet and cleared by software.\nCleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This\nbit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.\n0: HSE oscillator OFF\n1: HSE oscillator ON\nBits 15:8 HSICAL[7:0]: Internal high-speed clock calibration\nThese bits are initialized automatically at startup.\n130/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nBits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming\nThese bits provide an additional user-programmable trimming value that is added to the\nHSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature\nthat influence the frequency of the internal HSI RC.\nThe default value is 16, which, when added to the HSICAL value, should trim the HSI to 8\nMHz ± 1%. The trimming step (F hsitrim ) is around 40 kHz between two consecutive HSICAL\nsteps.\nBit 2\nReserved, must be kept at reset value.\nBit 1 HSIRDY: Internal high-speed clock ready flag\nSet by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is\ncleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.\n0: Internal 8 MHz RC oscillator not ready\n1: Internal 8 MHz RC oscillator ready\nBit 0 HSION: Internal high-speed clock enable\nSet and cleared by software.\nSet by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby\nmode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as\nsystem clock. This bit can not be cleared if the internal 8 MHz RC is used directly or\nindirectly as system clock or is selected to become the system clock.\n0: Internal 8 MHz RC oscillator OFF\n1: Internal 8 MHz RC oscillator ON\n8.3.2\nClock configuration register (RCC_CFGR)\nAddress offset: 0x04\nReset value: 0x0000 0000\nAccess: 0 ≤ wait state ≤ 2, word, half-word and byte access\n1 or 2 wait states inserted only if the access occurs during a clock source switch.\n31\n30\n29\n28\n27\n26\n25\n24\n23 22\nRes. OTGFS\nPRE\nMCO[3:0]\nReserved\n15\n14\n13\nADC PRE[1:0]\nrw\nrw\nBits 31:27\n12\nrw rw\n11 10\nPPRE2[2:0]\nrw\nrw\nrw rw\n9 8\n7\nPPRE1[2:0]\nrw\nrw\nrw\n21\n20\nrw\n18\nPLLMUL[3:0]\n17 16\nPLL\nXTPRE PLL\nSRC\nrw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nHPRE[3:0]\nrw\n19\nrw\nrw\nSWS[1:0]\nrw\nr\nr\nSW[1:0]\nrw\nrw\nReserved, must be kept at reset value.\nDoc ID 13902 Rev 14\n131/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBits 26:24 MCO[3:0]: Microcontroller clock output\nSet and cleared by software.\n00xx: No clock\n0100: System clock (SYSCLK) selected\n0101: HSI clock selected\n0110: HSE clock selected\n0111: PLL clock divided by 2 selected\n1000: PLL2 clock selected\n1001: PLL3 clock divided by 2 selected\n1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)\n1011: PLL3 clock selected (for Ethernet)\nNote: This clock output may have some truncated cycles at startup or during MCO clock source\nswitching.\nThe selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O\nspeed).\nBit 22 OTGFSPRE: USB OTG FS prescaler\nSet and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid\nbefore enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the\nOTG FS clock is enabled.\n0: PLL VCO (2 × PLLCLK) clock is divided by 3 (PLL must be configured to output 72 MHz)\n1: PLL VCO (2 × PLLCLK) clock is divided by 2 (PLL must be configured to output 48 MHz)\nBits 21:18 PLLMUL[3:0]: PLL multiplication factor\nThese bits are written by software to define the PLL multiplication factor. They can be written only\nwhen PLL is disabled.\n000x: Reserved\n0010: PLL input clock x 4\n0011: PLL input clock x 5\n0100: PLL input clock x 6\n0101: PLL input clock x 7\n0110: PLL input clock x 8\n0111: PLL input clock x 9\n10xx: Reserved\n1100: Reserved\n1101: PLL input clock x 6.5\n111x: Reserved\nCaution: The PLL output frequency must not exceed 72 MHz.\nBit 17 PLLXTPRE: LSB of division factor PREDIV1\nSet and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the\nsame bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register\nchanges this bit accordingly.\nIf bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by\n2 (PLLXTPRE=1) or not (PLLXTPRE=0).\nThis bit can be written only when PLL is disabled.\nBit 16 PLLSRC: PLL entry clock source\nSet and cleared by software to select PLL clock source. This bit can be written only when PLL is\ndisabled.\n0: HSI oscillator clock / 2 selected as PLL input clock\n1: Clock from PREDIV1 selected as PLL input clock\nNote: When changing the main PLL’s entry clock source, the original clock source must be switched\noff only after the selection of the new clock source.\n132/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nBits 14:14 ADCPRE[1:0]: ADC prescaler\nSet and cleared by software to select the frequency of the clock to the ADCs.\n00: PCLK2 divided by 2\n01: PCLK2 divided by 4\n10: PCLK2 divided by 6\n11: PCLK2 divided by 8\nBits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)\nSet and cleared by software to control the division factor of the APB High speed clock (PCLK2).\n0xx: HCLK not divided\n100: HCLK divided by 2\n101: HCLK divided by 4\n110: HCLK divided by 8\n111: HCLK divided by 16\nBits 10:8 PPRE1[2:0]: APB Low-speed prescaler (APB1)\nSet and cleared by software to control the division factor of the APB Low speed clock (PCLK1).\n0xx: HCLK not divided\n100: HCLK divided by 2\n101: HCLK divided by 4\n110: HCLK divided by 8\n111: HCLK divided by 16\nCaution: Software must configure these bits ensure that the frequency in this domain does not\nexceed 36 MHz.\nBits 7:4 HPRE[3:0]: AHB prescaler\nSet and cleared by software to control AHB clock division factor.\n0xxx: SYSCLK not divided\n1000: SYSCLK divided by 2\n1001: SYSCLK divided by 4\n1010: SYSCLK divided by 8\n1011: SYSCLK divided by 16\n1100: SYSCLK divided by 64\n1101: SYSCLK divided by 128\n1110: SYSCLK divided by 256\n1111: SYSCLK divided by 512\nNote: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.\nRefer to the section Reading the Flash memory on page 58 for more details.\nCaution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.\nBits 3:2 SWS[1:0]: System clock switch status\nSet and cleared by hardware to indicate which clock source is used as system clock.\n00: HSI oscillator used as system clock\n01: HSE oscillator used as system clock\n10: PLL used as system clock\n11: Not applicable\nDoc ID 13902 Rev 14\n133/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBits 1:0 SW[1:0]: System clock Switch\nSet and cleared by software to select SYSCLK source.\nSet by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of\nthe HSE oscillator used directly or indirectly as system clock (if the Clock Security System is\nenabled).\n00: HSI selected as system clock\n01: HSE selected as system clock\n10: PLL selected as system clock\n11: Not allowed\n8.3.3\nClock interrupt register (RCC_CIR)\nAddress offset: 0x08\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23 22 21 20 19 18 17 16\nCSSC PLL3\nRDYC PLL2\nRDYC PLL\nRDYC HSE\nRDYC HSI\nRDYC LSE\nRDYC LSI\nRDYC\nw w w w w w w w\nReserved\n15\nRes.\n14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nPLL3\nRDYIE PLL2\nRDYIE PLL\nRDYIE HSE\nRDYIE HSI\nRDYIE LSE\nRDYIE LSI\nRDYIE CSSF PLL3\nRDYF PLL2\nRDYF PLL\nRDYF HSE\nRDYF HSI\nRDYF LSE\nRDYF LSI\nRDYF\nrw rw rw rw rw rw rw r r r r r r r r\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 CSSC: Clock security system interrupt clear\nThis bit is set by software to clear the CSSF flag.\n0: No effect\n1: Clear CSSF flag\nBit 22 PLL3RDYC: PLL3 Ready Interrupt Clear\nThis bit is set by software to clear the PLL3RDYF flag.\n0: No effect\n1: Clear PLL3RDYF flag\nBit 21 PLL2RDYC: PLL2 Ready Interrupt Clear\nThis bit is set by software to clear the PLL2RDYF flag.\n0: No effect\n1: Clear PLL2RDYF flag\nBit 20 PLLRDYC: PLL ready interrupt clear\nThis bit is set by software to clear the PLLRDYF flag.\n0: No effect\n1: Clear PLLRDYF flag\nBit 19 HSERDYC: HSE ready interrupt clear\nThis bit is set by software to clear the HSERDYF flag.\n0: No effect\n1: Clear HSERDYF flag\n134/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 18 HSIRDYC: HSI ready interrupt clear\nThis bit is set by software to clear the HSIRDYF flag.\n0: No effect\n1: Clear HSIRDYF flag\nBit 17 LSERDYC: LSE ready interrupt clear\nThis bit is set by software to clear the LSERDYF flag.\n0: No effect\n1: Clear LSERDYF flag\nBit 16 LSIRDYC: LSI ready interrupt clear\nThis bit is set by software to clear the LSIRDYF flag.\n0: No effect\n1: Clear LSIRDYF flag\nBit 15 Reserved, must be kept at reset value.\nBit 14 PLL3RDYIE: PLL3 Ready Interrupt Enable\nSet and cleared by software to enable/disable interrupt caused by PLL3 lock.\n0: PLL3 lock interrupt disabled\n1: PLL3 lock interrupt enabled\nBit 13 PLL2RDYIE: PLL2 Ready Interrupt Enable\nSet and cleared by software to enable/disable interrupt caused by PLL2 lock.\n0: PLL2 lock interrupt disabled\n1: PLL2 lock interrupt enabled\nBit 12 PLLRDYIE: PLL ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by PLL lock.\n0: PLL lock interrupt disabled\n1: PLL lock interrupt enabled\nBit 11 HSERDYIE: HSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the external 3-25 MHz\noscillator stabilization.\n0: HSE ready interrupt disabled\n1: HSE ready interrupt enabled\nBit 10 HSIRDYIE: HSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC\noscillator stabilization.\n0: HSI ready interrupt disabled\n1: HSI ready interrupt enabled\nBit 9 LSERDYIE: LSE ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by the external 32 kHz\noscillator stabilization.\n0: LSE ready interrupt disabled\n1: LSE ready interrupt enabled\nBit 8 LSIRDYIE: LSI ready interrupt enable\nSet and cleared by software to enable/disable interrupt caused by internal RC 40 kHz\noscillator stabilization.\n0: LSI ready interrupt disabled\n1: LSI ready interrupt enabled\nDoc ID 13902 Rev 14\n135/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBit 7 CSSF: Clock security system interrupt flag\nSet by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared\nby software setting the CSSC bit.\n0: No clock security interrupt caused by HSE clock failure\n1: Clock security interrupt caused by HSE clock failure\nBit 6 PLL3RDYF: PLL3 Ready Interrupt flag\nSet by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software\nsetting the PLL3RDYC bit.\n0: No clock ready interrupt caused by PLL3 lock\n1: Clock ready interrupt caused by PLL3 lock\nBit 5 PLL2RDYF: PLL2 Ready Interrupt flag\nSet by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software\nsetting the PLL2RDYC bit.\n0: No clock ready interrupt caused by PLL2 lock\n1: Clock ready interrupt caused by PLL2 lock\nBit 4 PLLRDYF: PLL ready interrupt flag\nSet by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting\nthe PLLRDYC bit.\n0: No clock ready interrupt caused by PLL lock\n1: Clock ready interrupt caused by PLL lock\nBit3 HSERDYF: HSE ready interrupt flag\nSet by hardware when External High Speed clock becomes stable and HSERDYIE is set. It\nis cleared by software setting the HSERDYC bit.\n0: No clock ready interrupt caused by the external 3-25 MHz oscillator\n1: Clock ready interrupt caused by the external 3-25 MHz oscillator\nBit 2 HSIRDYF: HSI ready interrupt flag\nSet by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set.\nIt is cleared by software setting the HSIRDYC bit.\n0: No clock ready interrupt caused by the internal 8 MHz RC oscillator\n1: Clock ready interrupt caused by the internal 8 MHz RC oscillator\nBit 1 LSERDYF: LSE ready interrupt flag\nSet by hardware when the External Low Speed clock becomes stable and LSERDYIE is set.\nIt is cleared by software setting the LSERDYC bit.\n0: No clock ready interrupt caused by the external 32 kHz oscillator\n1: Clock ready interrupt caused by the external 32 kHz oscillator\nBit 0 LSIRDYF: LSI ready interrupt flag\nSet by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is\ncleared by software setting the LSIRDYC bit.\n0: No clock ready interrupt caused by the internal RC 40 kHz oscillator\n1: Clock ready interrupt caused by the internal RC 40 kHz oscillator\n136/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\n8.3.4\nAPB2 peripheral reset register (RCC_APB2RSTR)\nAddress offset: 0x0C\nReset value: 0x00000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nIOPE\nRST IOPD\nRST IOPC\nRST IOPB\nRST IOPA\nRST Res. AFIO\nRST\nrw rw rw rw rw\nReserved\n15 14 13 12 11 10 9\nRes. USART1\nRST Res. SPI1\nRST TIM1\nRST ADC2\nRST ADC1\nRST\nrw rw rw rw\nrw\nBits 31:15\n8\n7\nReserved\nrw\nReserved, must be kept at reset value.\nBit 14 USART1RST: USART1 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART1\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1RST: SPI 1 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI 1\nBit 11 TIM1RST: TIM1 timer reset\nSet and cleared by software.\n0: No effect\n1: Reset TIM1 timer\nBit 10 ADC2RST: ADC 2 interface reset\nSet and cleared by software.\n0: No effect\n1: Reset ADC 2 interface\nBit 9 ADC1RST: ADC 1 interface reset\nSet and cleared by software.\n0: No effect\n1: Reset ADC 1 interface\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 IOPERST: I/O port E reset\nSet and cleared by software.\n0: No effect\n1: Reset I:O port E\nBit 5 IOPDRST: I/O port D reset\nSet and cleared by software.\n0: No effect\n1: Reset I/O port D\nDoc ID 13902 Rev 14\n137/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBit 4 IOPCRST: IO port C reset\nSet and cleared by software.\n0: No effect\n1: Reset I/O port C\nBit 3 IOPBRST: IO port B reset\nSet and cleared by software.\n0: No effect\n1: Reset I/O port B\nBit 2 IOPARST: I/O port A reset\nSet and cleared by software.\n0: No effect\n1: Reset I/O port A\nBit 1 Reserved, must be kept at reset value.\nBit 0 AFIORST: Alternate function I/O reset\nSet and cleared by software.\n0: No effect\n1: Reset Alternate Function\n8.3.5\nAPB1 peripheral reset register (RCC_APB1RSTR)\nAddress offset: 0x10\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\nReserved\n15 14\nSPI3\nRST SPI2\nRST\nrw rw\n29 28 27 26 25\nDAC\nRST PWR\nRST BKP\nRST CAN2\nRST CAN1\nRST\nrw rw rw rw rw\n13 12 11 10 9\nReserved\nWWD\nGRST\n24\n23\nReserved\n8\n7\n22 21 20 19 18 17 16\nI2C2\nRST I2C1\nRST UART\n5\nRST UART\n4\nRST USART\n3\nRST USART\n2\nRST Res.\nrw rw rw rw rw rw\n6\nReserved\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBit 29 DACRST: DAC interface reset\nSet and cleared by software.\n0: No effect\n1: Reset DAC interface\nBit 28 PWRRST: Power interface reset\nSet and cleared by software.\n0: No effect\n1: Reset power interface\n138/1096\nDoc ID 13902 Rev 14\n5 4 3 2 1 0\nTIM7\nRST TIM6\nRST TIM5\nRST TIM4\nRST TIM3\nRST TIM2\nRST\nrw rw rw rw rw rw RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 27 BKPRST: Backup interface reset\nSet and cleared by software.\n0: No effect\n1: Reset backup interface\nBit 26 CAN2RST: CAN2 reset\nSet and cleared by software.\n0: No effect\n1: Reset CAN2\nBit 25 CAN1RST: CAN1 reset\nSet and cleared by software.\n0: No effect\n1: Reset CAN1\nBits 24:23\nReserved, must be kept at reset value.\nBit 22 I2C2RST: I2C 2 reset\nSet and cleared by software.\n0: No effect\n1: Reset I2C 2\nBit 21 I2C1RST: I2C1 reset\nSet and cleared by software.\n0: No effect\n1: Reset I2C 1\nBit 20 UART5RST: USART 5 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART 5\nBit 19 UART4RST: USART 4 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART 4\nBit 18 USART3RST: USART 3 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART 3\nBit 17 USART2RST: USART 2 reset\nSet and cleared by software.\n0: No effect\n1: Reset USART 2\nBits 16\nReserved, must be kept at reset value.\nBit 15 SPI3RST: SPI3 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI 3\nBit 14 SPI2RST: SPI2 reset\nSet and cleared by software.\n0: No effect\n1: Reset SPI2\nDoc ID 13902 Rev 14\n139/1096 Connectivity line devices: reset and clock control (RCC)\nBits 13:12\nReserved, must be kept at reset value.\nBit 11 WWDGRST: Window watchdog reset\nSet and cleared by software.\n0: No effect\n1: Reset window watchdog\nBits 10:6 Reserved, must be kept at reset value.\nBit 5 TIM7RST: Timer 7 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 7\nBit 4 TIM6RST: Timer 6 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 6\nBit 3 TIM5RST: Timer 5 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 5\nBit 2 TIM4RST: Timer 4 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 4\nBit 1 TIM3RST: Timer 3 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 3\nBit 0 TIM2RST: Timer 2 reset\nSet and cleared by software.\n0: No effect\n1: Reset timer 2\n140/1096\nDoc ID 13902 Rev 14\nRM0008 RM0008\nConnectivity line devices: reset and clock control (RCC)\n8.3.6\nAHB Peripheral Clock enable register (RCC_AHBENR)\nAddress offset: 0x14\nReset value: 0x0000 0014\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nETH\nMACR\nXEN\nReserved\nrw\n15 14\nETHM\nACTX\nEN ETHM\nACEN\nrw rw\n13\nRes.\n12\nOTGF\nSEN\n11\n10\n9\n8\n7\n6\n5\nCRCEN\nReserved\nrw\nRes.\nrw\n4\nFLITFE\nN\nrw\n3 2 1 0\nRes. SRAM\nEN DMA2\nEN DMA1\nEN\nrw rw rw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 ETHMACRXEN: Ethernet MAC RX clock enable\nSet and cleared by software.\n0: Ethernet MAC RX clock disabled\n1: Ethernet MAC RX clock enabled\nNote: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.\nBit 15 ETHMACTXEN: Ethernet MAC TX clock enable\nSet and cleared by software.\n0: Ethernet MAC TX clock disabled\n1: Ethernet MAC TX clock enabled\nNote: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.\nBit 14 ETHMACEN: Ethernet MAC clock enable\nSet and cleared by software. Selection of PHY interface (MII/RMII) must be done before\nenabling the MAC clock.\n0: Ethernet MAC clock disabled\n1: Ethernet MAC clock enabled\nBit 13 Reserved, must be kept at reset value.\nBit 12 OTGFSEN: USB OTG FS clock enable\nSet and cleared by software.\n0: USB OTG FS clock disabled\n1: USB OTG FS clock enabled\nBits 11:7 Reserved, must be kept at reset value.\nBit 6 CRCEN: CRC clock enable\nSet and cleared by software.\n0: CRC clock disabled\n1: CRC clock enabled\nBit 5 Reserved, must be kept at reset value.\nDoc ID 13902 Rev 14\n141/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBit 4 FLITFEN: FLITF clock enable\nSet and cleared by software to disable/enable FLITF clock during sleep mode.\n0: FLITF clock disabled during Sleep mode\n1: FLITF clock enabled during Sleep mode\nBit 3 Reserved, must be kept at reset value.\nBit 2 SRAMEN: SRAM interface clock enable\nSet and cleared by software to disable/enable SRAM interface clock during Sleep mode.\n0: SRAM interface clock disabled during Sleep mode\n1: SRAM interface clock enabled during Sleep mode\nBit 1 DMA2EN: DMA2 clock enable\nSet and cleared by software.\n0: DMA2 clock disabled\n1: DMA2 clock enabled\nBit 0 DMA1EN: DMA1 clock enable\nSet and cleared by software.\n0: DMA1 clock disabled\n1: DMA1 clock enabled\n8.3.7\nAPB2 peripheral clock enable register (RCC_APB2ENR)\nAddress: 0x18\nReset value: 0x0000 0000\nAccess: word, half-word and byte access\nNo wait states, except if the access occurs while an access to a peripheral in the APB2\ndomain is on going. In this case, wait states are inserted until the access to APB2 peripheral\nis finished.\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18 17\n16\n1 0\nRes. AFIO\nEN\nReserved\n15\nRes.\n14\n13 12\n11\n10\n9\nRes. SPI1\nEN\nTIM1\nEN\nADC2\nEN\nADC1\nEN\nrw rw\nrw\nrw\nrw\nBits 31:15 Reserved, must be kept at reset value.\nUSAR\nT1EN\n8\n7\nReserved\n6 5 4 3 2\nIOPE\nEN IOPD\nEN IOPC\nEN IOPB\nEN IOPA\nEN\nrw rw rw rw rw\nBit 14 USART1EN: USART1 clock enable\nSet and cleared by software.\n0: USART1 clock disabled\n1: USART1 clock enabled\nBit 13 Reserved, must be kept at reset value.\nBit 12 SPI1EN: SPI 1 clock enable\nSet and cleared by software.\n0: SPI 1 clock disabled\n1: SPI 1 clock enabled\n142/1096\nDoc ID 13902 Rev 14\nrw RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 11 TIM1EN: TIM1 Timer clock enable\nSet and cleared by software.\n0: TIM1 timer clock disabled\n1: TIM1 timer clock enabled\nBit 10 ADC2EN: ADC 2 interface clock enable\nSet and cleared by software.\n0: ADC 2 interface clock disabled\n1: ADC 2 interface clock enabled\nBit 9 ADC1EN: ADC 1 interface clock enable\nSet and cleared by software.\n0: ADC 1 interface disabled\n1: ADC 1 interface clock enabled\nBits 8:7 Reserved, must be kept at reset value.\nBit 6 IOPEEN: I/O port E clock enable\nSet and cleared by software.\n0: I/O port E clock disabled\n1: I/O port E clock enabled\nBit 5 IOPDEN: I/O port D clock enable\nSet and cleared by software.\n0: I/O port D clock disabled\n1: I/O port D clock enabled\nBit 4 IOPCEN: I/O port C clock enable\nSet and cleared by software.\n0: I/O port C clock disabled\n1:I/O port C clock enabled\nBit 3 IOPBEN: I/O port B clock enable\nSet and cleared by software.\n0: I/O port B clock disabled\n1:I/O port B clock enabled\nBit 2 IOPAEN: I/O port A clock enable\nSet and cleared by software.\n0: I/O port A clock disabled\n1:I/O port A clock enabled\nBit 1\nReserved, must be kept at reset value.\nBit 0 AFIOEN: Alternate function I/O clock enable\nSet and cleared by software.\n0: Alternate Function I/O clock disabled\n1:Alternate Function I/O clock enabled\nDoc ID 13902 Rev 14\n143/1096 Connectivity line devices: reset and clock control (RCC)\n8.3.8\nRM0008\nAPB1 peripheral clock enable register (RCC_APB1ENR)\nAddress: 0x1C\nReset value: 0x0000 0000\nAccess: word, half-word and byte access\nNo wait state, except if the access occurs while an access to a peripheral on APB1 domain\nis on going. In this case, wait states are inserted until this access to APB1 peripheral is\nfinished.\n31\n30\nReserved\n15 14\nSPI3\nEN SPI2\nEN\nrw rw\n29 28 27 26 25\nDAC\nEN PWR\nEN BKP\nEN CAN2\nEN CAN1\nEN\nrw rw rw rw rw\n13 12 11 10 9\nReserved\nWWD\nGEN\n24\n23\nReserved\n8\n7\n22 21 20 19 18 17 I2C2\nEN I2C1\nEN UART5E\nN UART4\nEN USART\n3EN USART\n2EN rw rw rw rw rw rw 6 5 4 3 2 1 0\nTIM7\nEN TIM6\nEN TIM5\nEN TIM4\nEN TIM3\nEN TIM2\nEN\nrw rw rw rw rw rw\nReserved\nrw\nBits 31:30\nReserved, must be kept at reset value.\nBit 29 DACEN: DAC interface clock enable\nSet and cleared by software.\n0: DAC interface clock disabled\n1: DAC interface clock enable\nBit 28 PWREN: Power interface clock enable\nSet and cleared by software.\n0: Power interface clock disabled\n1: Power interface clock enable\nBit 27 BKPEN: Backup interface clock enable\nSet and cleared by software.\n0: Backup interface clock disabled\n1: Backup interface clock enabled\nBit 26 CAN2EN: CAN2 clock enable\nSet and cleared by software.\n0: CAN2 clock disabled\n1: CAN2 clock enabled\nBit 25 CAN1EN: CAN1 clock enable\nSet and cleared by software.\n0: CAN1 clock disabled\n1: CAN1 clock enabled\nBits 24:23\nReserved, must be kept at reset value.\nBit 22 I2C2EN: I2C 2 clock enable\nSet and cleared by software.\n0: I2C 2 clock disabled\n1: I2C 2 clock enabled\n144/1096\nDoc ID 13902 Rev 14\n16\nRes. RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 21 I2C1EN: I2C 1 clock enable\nSet and cleared by software.\n0: I2C 1 clock disabled\n1: I2C 1 clock enabled\nBit 20 UART5EN: USART 5 clock enable\nSet and cleared by software.\n0: USART 5 clock disabled\n1: USART 5 clock enabled\nBit 19 UART4EN: USART 4 clock enable\nSet and cleared by software.\n0: USART 4 clock disabled\n1: USART 4 clock enabled\nBit 18 USART3EN: USART 3 clock enable\nSet and cleared by software.\n0: USART 3 clock disabled\n1: USART 3 clock enabled\nBit 17 USART2EN: USART 2 clock enable\nSet and cleared by software.\n0: USART 2 clock disabled\n1: USART 2 clock enabled\nBits 16\nReserved, must be kept at reset value.\nBit 15 SPI3EN: SPI 3 clock enable\nSet and cleared by software.\n0: SPI 3 clock disabled\n1: SPI 3 clock enabled\nBit 14 SPI2EN: SPI 2 clock enable\nSet and cleared by software.\n0: SPI 2 clock disabled\n1: SPI 2 clock enabled\nBits 13:12\nReserved, must be kept at reset value.\nBit 11 WWDGEN: Window watchdog clock enable\nSet and cleared by software.\n0: Window watchdog clock disabled\n1: Window watchdog clock enabled\nBits 10:6 Reserved, must be kept at reset value.\nBit 5 TIM7EN: Timer 7 clock enable\nSet and cleared by software.\n0: Timer 7 clock disabled\n1: Timer 7 clock enabled\nBit 4 TIM6EN: Timer 6 clock enable\nSet and cleared by software.\n0: Timer 6 clock disabled\n1: Timer 6 clock enabled\nDoc ID 13902 Rev 14\n145/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBit 3 TIM5EN: Timer 5 clock enable\nSet and cleared by software.\n0: Timer 5 clock disabled\n1: Timer 5 clock enabled\nBit 2 TIM4EN: Timer 4 clock enable\nSet and cleared by software.\n0: Timer 4 clock disabled\n1: Timer 4 clock enabled\nBit 1 TIM3EN: Timer 3 clock enable\nSet and cleared by software.\n0: Timer 3 clock disabled\n1: Timer 3 clock enabled\nBit 0 TIM2EN: Timer 2 clock enable\nSet and cleared by software.\n0: Timer 2 clock disabled\n1: Timer 2 clock enabled\n8.3.9\nBackup domain control register (RCC_BDCR)\nAddress: 0x20\nReset value: 0x0000 0000, reset by Backup domain Reset.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in the case of successive accesses to this register.\nNote:\n31\nLSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register\n(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-\nprotected and the DBP bit in the Power control register (PWR_CR) has to be set before\nthese can be modified. Refer to Section 6 on page 79 for further information. These bits are\nonly reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset). Any\ninternal or external Reset will not have any effect on these bits.\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nBDRST\nReserved\nrw\n15\nRTC\nEN\nrw\n14\n13\n12\n11\n10\n9\n8\n7\n6\nRTCSEL[1:0]\nReserved\nReserved\nrw\nrw\nBits 31:17 Reserved, must be kept at reset value.\nBit 16 BDRST: Backup domain software reset\nSet and cleared by software.\n0: Reset not activated\n1: Resets the entire Backup domain\n146/1096\n5\nDoc ID 13902 Rev 14\n4\n3\n2 1 0\nLSE\nBYP LSE\nRDY LSEON\nrw r rw RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 15 RTCEN: RTC clock enable\nSet and cleared by software.\n0: RTC clock disabled\n1: RTC clock enabled\nBits 14:10 Reserved, must be kept at reset value.\nBits 9:8 RTCSEL[1:0]: RTC clock source selection\nSet by software to select the clock source for the RTC. Once the RTC clock source has been\nselected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit\ncan be used to reset the RTCSEL[1:0] bits.\n00: No clock\n01: LSE oscillator clock used as RTC clock\n10: LSI oscillator clock used as RTC clock\n11: HSE oscillator clock divided by 128 used as RTC clock\nBits 7:3 Reserved, must be kept at reset value.\nBit 2 LSEBYP: External Low Speed oscillator bypass\nSet and cleared by software to bypass oscillator in debug mode. This bit can be written only\nwhen the external 32 kHz oscillator is disabled.\n0: LSE oscillator not bypassed\n1: LSE oscillator bypassed\nBit 1 LSERDY: External Low Speed oscillator ready\nSet and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After\nthe LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock\ncycles\n0: External 32 kHz oscillator not ready\n1: External 32 kHz oscillator ready\nBit 0 LSEON: External Low Speed oscillator enable\nSet and cleared by software.\n0: External 32 kHz oscillator OFF\n1: External 32 kHz oscillator ON\nDoc ID 13902 Rev 14\n147/1096 Connectivity line devices: reset and clock control (RCC)\n8.3.10\nRM0008\nControl/status register (RCC_CSR)\nAddress: 0x24\nReset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.\nAccess: 0 ≤ wait state ≤ 3, word, half-word and byte access\nWait states are inserted in the case of successive accesses to this register.\n31 30 29 28 27 26 25\nLPWR\nRSTF WWDG\nRSTF IWDG\nRSTF SFT\nRSTF POR\nRSTF PIN\nRSTF Res.\nrw rw rw rw rw rw 15 14 13 12 11 10\n24\n23\n22\n21\n20\n19\n18 17 16\n2 1 0\nLSI\nRDY LSION\nr rw\nRMVF\nReserved\nrw\n9\n8\n7\n6\nReserved\n5\n4\n3\nBit 31 LPWRRSTF: Low-power reset flag\nSet by hardware when a Low-power management reset occurs. It is cleared by writing to the\nRMVF bit.\n0: No Low-power management reset occurred\n1: Low-power management reset occurred\nFor further information on Low-power management reset, refer to Section : Low-power\nmanagement reset.\nBit 30 WWDGRSTF: Window watchdog reset flag\nSet by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF\nbit.\n0: No window watchdog reset occurred\n1: Window watchdog reset occurred\nBit 29 IWDGRSTF: Independent watchdog reset flag\nSet by hardware when an independent watchdog reset from V DD domain occurs. It is cleared\nby writing to the RMVF bit.\n0: No watchdog reset occurred\n1: Watchdog reset occurred\nBit 28 SFTRSTF: Software reset flag\nSet by hardware when a software reset occurs. It is cleared by writing to the RMVF bit.\n0: No software reset occurred\n1: Software reset occurred\nBit 27 PORRSTF: POR/PDR reset flag\nSet by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.\n0: No POR/PDR reset occurred\n1: POR/PDR reset occurred\nBit 26 PINRSTF: PIN reset flag\nSet by hardware when a reset from the NRST pin occurs. It is cleared by writing to the\nRMVF bit.\n0: No reset from NRST pin occurred\n1: Reset from NRST pin occurred\nBit 25 Reserved, must be kept at reset value.\n148/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nBit 24 RMVF: Remove reset flag\nSet by software to clear the reset flags.\n0: No effect\n1: Clear the reset flags\nBits 23:2 Reserved, must be kept at reset value.\nBit 1 LSIRDY: Internal low speed oscillator ready\nSet and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.\nAfter the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock\ncycles.\n0: Internal RC 40 kHz oscillator not ready\n1: Internal RC 40 kHz oscillator ready\nBit 0 LSION: Internal low speed oscillator enable\nSet and cleared by software.\n0: Internal RC 40 kHz oscillator OFF\n1: Internal RC 40 kHz oscillator ON\n8.3.11\nAHB peripheral clock reset register (RCC_AHBRSTR)\nAddress offset: 0x28\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23 22 21 20 19 18 17 16\n7 6 5 4 3 2 1 0\nReserved\n15\n14\n13\nETHMAC\nRST\nRes.\n12\n11\n10\n9\n8\nOTGFS\nRST\nRes.\nrw\nReserved\nrw\nBits 31:15 Reserved, must be kept at reset value.\nBit 14 ETHMACRST Ethernet MAC reset\nSet and cleared by software.\n0: No effect\n1: Reset ETHERNET MAC\nBit 13\nReserved, must be kept at reset value.\nBit 12 OTGFSRST USB OTG FS reset\nSet and cleared by software.\n0: No effect\n1: Reset USB OTG FS\nBits 11:0 Reserved, must be kept at reset value.\nDoc ID 13902 Rev 14\n149/1096 Connectivity line devices: reset and clock control (RCC)\n8.3.12\nRM0008\nClock configuration register2 (RCC_CFGR2)\nAddress offset: 0x2C\nReset value: 0x0000 0000\nAccess: no wait state, word, half-word and byte access\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\nReserved\n15\n14\n13\n12\n11\nPLL3MUL[3:0]\nrw\nrw\nrw\n10\n9\n8\n7\nPLL2MUL[3:0]\nrw\nrw\nrw\nrw\n6\n5\n4\n3\nPREDIV2[3:0]\nrw\nrw\nrw\nrw\n18 17 16\nI2S3S\nRC I2S2S\nRC PREDI\nV1SRC\nrw rw rw\n2 1 0\nPREDIV1[3:0]\nrw\nrw\nrw\nrw\nrw\n7\nBits 31:19 Reserved, must be kept at reset value.\nBit 18 I2S3SRC: I2S3 clock source\nSet and cleared by software to select I2S3 clock source. This bit must be valid before\nenabling I2S3 clock.\n0: System clock (SYSCLK) selected as I2S3 clock entry\n1: PLL3 VCO clock selected as I2S3 clock entry\nBit 17 I2S2SRC: I2S2 clock source\nSet and cleared by software to select I2S2 clock source. This bit must be valid before\nenabling I2S2 clock.\n0: System clock (SYSCLK) selected as I2S2 clock entry\n1: PLL3 VCO clock selected as I2S2 clock entry\nBit 16 PREDIV1SRC: PREDIV1 entry clock source\nSet and cleared by software to select PREDIV1 clock source. This bit can be written only\nwhen PLL is disabled.\n0: HSE oscillator clock selected as PREDIV1 clock entry\n1: PLL2 selected as PREDIV1 clock entry\nBits 15:12 PLL3MUL[3:0]: PLL3 Multiplication Factor\nSet and cleared by software to control PLL3 multiplication factor. These bits can be written\nonly when PLL3 is disabled.\n00xx: Reserved\n010x: Reserved\n0110: PLL3 clock entry x 8\n0111: PLL3 clock entry x 9\n1000: PLL3 clock entry x 10\n1001: PLL3 clock entry x 11\n1010: PLL3 clock entry x 12\n1011: PLL3 clock entry x 13\n1100: PLL3 clock entry x 14\n1101: Reserved\n1110: PLL3 clock entry x 16\n1111: PLL3 clock entry x 20\n150/1096\nDoc ID 13902 Rev 14 RM0008\nConnectivity line devices: reset and clock control (RCC)\nBits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor\nSet and cleared by software to control PLL2 multiplication factor. These bits can be written\nonly when PLL2 is disabled.\n00xx: Reserved\n010x: Reserved\n0110: PLL2 clock entry x 8\n0111: PLL2 clock entry x 9\n1000: PLL2 clock entry x 10\n1001: PLL2 clock entry x 11\n1010: PLL2 clock entry x 12\n1011: PLL2 clock entry x 13\n1100: PLL2 clock entry x 14\n1101: Reserved\n1110: PLL2 clock entry x 16\n1111: PLL2 clock entry x 20\nBits 7:4 PREDIV2[3:0]: PREDIV2 division factor\nSet and cleared by software to select PREDIV2 division factor. These bits can be written only\nwhen both PLL2 and PLL3 are disabled.\n0000: PREDIV2 input clock not divided\n0001: PREDIV2 input clock divided by 2\n0010: PREDIV2 input clock divided by 3\n0011: PREDIV2 input clock divided by 4\n0100: PREDIV2 input clock divided by 5\n0101: PREDIV2 input clock divided by 6\n0110: PREDIV2 input clock divided by 7\n0111: PREDIV2 input clock divided by 8\n1000: PREDIV2 input clock divided by 9\n1001: PREDIV2 input clock divided by 10\n1010: PREDIV2 input clock divided by 11\n1011: PREDIV2 input clock divided by 12\n1100: PREDIV2 input clock divided by 13\n1101: PREDIV2 input clock divided by 14\n1110: PREDIV2 input clock divided by 15\n1111: PREDIV2 input clock divided by 16\nDoc ID 13902 Rev 14\n151/1096 Connectivity line devices: reset and clock control (RCC)\nRM0008\nBits 3:0 PREDIV1[3:0]: PREDIV1 division factor\nSet and cleared by software to select PREDIV1 division factor. These bits can be written only\nwhen PLL is disabled.\nNote: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the\nRCC_CFGR register changes Bit(0) accordingly.\n0000: PREDIV1 input clock not divided\n0001: PREDIV1 input clock divided by 2\n0010: PREDIV1 input clock divided by 3\n0011: PREDIV1 input clock divided by 4\n0100: PREDIV1 input clock divided by 5\n0101: PREDIV1 input clock divided by 6\n0110: PREDIV1 input clock divided by 7\n0111: PREDIV1 input clock divided by 8\n1000: PREDIV1 input clock divided by 9\n1001: PREDIV1 input clock divided by 10\n1010: PREDIV1 input clock divided by 11\n1011: PREDIV1 input clock divided by 12\n1100: PREDIV1 input clock divided by 13\n1101: PREDIV1 input clock divided by 14\n1110: PREDIV1 input clock divided by 15\n1111: PREDIV1 input clock divided by 16\n8.3.13\nRCC register map\nThe following table gives the RCC register map and the reset values.\nRCC register map and reset values\nPLLMUL [3:0] ADC\nPRE\n[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0\n152/1096\nDoc ID 13902 Rev 14\n0\n0 0 0 0 0 0 0 0\n0\n0\nReserved\n0 0 0 0 0 0\n0\n0 0 0\n0 0 0 0 SW\n[1:0]\n0 SWS\n[1:0]\nHPRE[3:0]\n0\n1\n0 1 0\n0\n0\n0\n0\n0\n0\n0\n0 0 0\n1\nPPRE1\n[2:0]\n0 0 0\n0 0 0 0\nReset value\nRCC_APB1RSTR Reser\nved\n0x010\nx\n0\n0\nReset value\nx\nReserved\nx\nRCC_APB2RSTR\nPPRE2\n[2:0]\n0x00C\nx\nReset value\nx\nReserved\nx\n0\n0\nx\nx\nHSITRIM[4:0]\n0\nHSICAL[7:0]\n0\nRCC_CIR\n0\n0\n0\n0\n0\nMCO [3:0]\nReserved\nReset value\n0x008\n0\n0\nReserved\n0 0\nRCC_CFGR\n0x004\n0\nReset value\nReser\nved\nRCC_CR\n0x000\nRegister\nOffset\n8\nTable 19.\n0 0 0 0 0 0\n0 RM0008\nConnectivity line devices: reset and clock control (RCC)\nReserved\nReserved\n0\nReset value\n0 0 0 0\n0 0 0 0\nReserved\n0\n0 0 0\n0 0\nReserved\n0\nPLL3MUL\n[3:0]\n0\n0\n0\n0\n0\nRCC_CFGR2\n0\nReserved\nReset value\n0x02C\n0 1\n0 1 0\n0\n0\n0\n0 0\nReserved\nRTC\nSEL\n[1:0]\n1 0 0\n1\n0 0\n0\nReserved\n0 0 0 0\nOTGFSRST\nRCC_AHBSTR\nReset value\n0\n0x028\nRCC_CSR\n0\n0\nReserved\nReset value\n0x024\n0\n0\n0 0 0\n0\nRCC_BDCR\n0\n0\n0 0\nReserved\n0\n0x020\n0\nReset value\nRCC_APB1ENR Reser\nved\n0x01C\n0\n0\nReset value\nReserved\nReserved\n0\n0\nRCC_APB2ENR\n0\n0x018\nReset value\nReserved\nRCC_AHBENR\n0x014\nRegister\nOffset\nRCC register map and reset values (continued)\nTable 19.\n0\nPLL2MUL\n[3:0]\n0\n0\n0\n0\nPREDIV2[3:0] PREDIV1[3:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n153/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9\nRM0008\nGeneral-purpose and alternate-function I/Os (GPIOs\nand AFIOs)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F10xxx family, unless otherwise specified.\n9.1\nGPIO functional description\nEach of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL,\nGPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset\nregister (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register\n(GPIOx_LCKR).\nSubject to the specific hardware characteristics of each I/O port listed in the datasheet, each\nport bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\nin several modes:\n● Input floating\n● Input pull-up\n● Input-pull-down\n● Analog\n● Output open-drain\n● Output push-pull\n● Alternate function push-pull\n● Alternate function open-drain\nEach I/O port bit is freely programmable, however the I/O port registers have to be accessed\nas 32-bit words (half-word or byte accesses are not allowed). The purpose of the\nGPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of\nthe GPIO registers. This way, there is no risk that an IRQ occurs between the read and the\nmodify access.\nFigure 13 shows the basic structure of an I/O Port bit.\n154/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nFigure 13. Basic structure of a standard I/O port bit\non/off\nAlternate Function Input\non/off\nV DD\nTTL Schmitt\ntrigger\nV SS\nOutput driver\nI/O pin\nV DD\nProtection\ndiode\nP-MOS\nOutput\ncontrol\nV SS\nN-MOS\nRead/write\nV SS\nFrom on-chip\nperipheral\nProtection\ndiode\non/off\nInput driver\nRead\nWrite\nV DD\nAnalog Input\nTo on-chip\nperipheral\nPush-pull,\nopen-drain or\ndisabled\nAlternate Function Output\nai14781\nFigure 14. Basic structure of a five-volt tolerant I/O port bit\non/off\nAlternate Function Input\non/off\nV DD_FT(1)\nTTL Schmitt\ntrigger\non/off\nV SS\nInput driver\nRead\nWrite\nV DD\nAnalog Input\nTo on-chip\nperipheral\nOutput driver\nV DD\nProtection\ndiode\nP-MOS\nOutput\ncontrol\nV SS\nN-MOS\nRead/write\nV SS\nFrom on-chip\nperipheral\nI/O pin\nAlternate Function Output\nPush-pull,\nopen-drain or\ndisabled\nai14782\n1. V DD_FT is a potential specific to five-volt tolerant I/Os and different from V DD .\nDoc ID 13902 Rev 14\n155/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 20.\nRM0008\nPort bit configuration table\nConfiguration mode\nGeneral purpose\noutput Push-pull\nAlternate Function\noutput Push-pull\nCNF1\nCNF0\n0\n0\nOpen-drain\n1\n0\n1\nOpen-drain\n1\nAnalog\nMODE1\nMODE0\n01\n10\n11\nsee Table 21\n0\nPxODR\nregister\n0 or 1\n0 or 1\ndon’t care\ndon’t care\ndon’t care\n0\nInput floating\n1\nInput\ndon’t care\n00\nInput pull-down\n0\n1\n0\nInput pull-up\nTable 21.\n9.1.1\n1\nOutput MODE bits\nMODE[1:0] Meaning\n00 Reserved\n01 Max. output speed 10 MHz\n10 Max. output speed 2 MHz\n11 Max. output speed 50 MHz\nGeneral-purpose I/O (GPIO)\nDuring and just after reset, the alternate functions are not active and the I/O ports are\nconfigured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).\nThe JTAG pins are in input PU/PD after reset:\nPA15: JTDI in PU\nPA14: JTCK in PD\nPA13: JTMS in PU\nPB4: NJTRST in PU\nWhen configured as output, the value written to the Output Data register (GPIOx_ODR) is\noutput on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain\nmode (only the N-MOS is activated when outputting 0).\nThe Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every\nAPB2 clock cycle.\nAll GPIO pins have an internal weak pull-up and weak pull-down which can be activated or\nnot when configured as input.\n9.1.2\nAtomic bit set or reset\nThere is no need for the software to disable interrupts when programming the GPIOx_ODR\nat bit level: it is possible to modify only one or several bits in a single atomic APB2 write\naccess. This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR,\n156/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nor for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will\nnot be modified.\n9.1.3\nExternal interrupt/wakeup lines\nAll ports have external interrupt capability. To use external interrupt lines, the port must be\nconfigured in input mode. For more information on external interrupts, refer to:\n9.1.4\n● Section 10.2: External interrupt/event controller (EXTI) on page 198 and\n● Section 10.2.3: Wakeup event management on page 199\nAlternate functions (AF)\nIt is necessary to program the Port Bit Configuration Register before using a default\nalternate function.\n●\nNote:\nFor alternate function inputs, the port must be configured in Input mode (floating, pull-\nup or pull-down) and the input pin must be driven externally.\nIt is also possible to emulate the AFI input pin by software by programming the GPIO\ncontroller. In this case, the port should be configured in Alternate Function Output mode.\nAnd obviously, the corresponding port should not be driven externally as it will be driven by\nthe software using the GPIO controller.\n● For alternate function outputs, the port must be configured in Alternate Function Output\nmode (Push-Pull or Open-Drain).\n● For bidirectional Alternate Functions, the port bit must be configured in Alternate\nFunction Output mode (Push-Pull or Open-Drain). In this case the input driver is\nconfigured in input floating mode\nIf you configure a port bit as Alternate Function Output, this disconnects the output register\nand connects the pin to the output signal of an on-chip peripheral.\nIf software configures a GPIO pin as Alternate Function Output, but peripheral is not\nactivated, its output is not specified.\n9.1.5\nSoftware remapping of I/O alternate functions\nTo optimize the number of peripheral I/O functions for different device packages, it is\npossible to remap some alternate functions to some other pins. This is achieved by\nsoftware, by programming the corresponding registers (refer to AFIO registers on page 177.\nIn that case, the alternate functions are no longer mapped to their original assignations.\n9.1.6\nGPIO locking mechanism\nThe locking mechanism allows the IO configuration to be frozen. When the LOCK sequence\nhas been applied on a port bit, it is no longer possible to modify the value of the port bit until\nthe next reset.\nDoc ID 13902 Rev 14\n157/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.1.7\nRM0008\nInput configuration\nWhen the I/O Port is programmed as Input:\n● The Output Buffer is disabled\n● The Schmitt Trigger Input is activated\n● The weak pull-up and pull-down resistors are activated or not depending on input\nconfiguration (pull-up, pull-down or floating):\n● The data present on the I/O pin is sampled into the Input Data Register every APB2\nclock cycle\n● A read access to the Input Data Register obtains the I/O State.\nThe Figure 15 on page 158 shows the Input Configuration of the I/O Port bit.\nFigure 15. Input floating/pull up/pull down configurations\nV DD\non/off\nWrite\nRead\nRead/write\non\nV DD or V DD_FT(1)\nTTL Schmitt\ntrigger\ninput driver\nprotection\ndiode\non/off\nV SS\nI/O pin\noutput driver\nprotection\ndiode\nV SS\nai14783\n1. V DD_FT is a potential specific to five-volt tolerant I/Os and different from V DD .\n9.1.8\nOutput configuration\nWhen the I/O Port is programmed as Output:\n●\n158/1096\nThe Output Buffer is enabled:\n– Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in\nthe Output register leaves the port in Hi-Z. (the P-MOS is never activated)\n– Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the\nOutput register activates the P-MOS.\n● The Schmitt Trigger Input is activated.\n● The weak pull-up and pull-down resistors are disabled.\n● The data present on the I/O pin is sampled into the Input Data Register every APB2\nclock cycle\n● A read access to the Input Data Register gets the I/O state in open drain mode\n● A read access to the Output Data register gets the last written value in Push-Pull mode\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nThe Figure 16 on page 159 shows the Output configuration of the I/O Port bit.\nregister\nFigure 16. Output configuration\nRead/write\nWrite\nRead\non\nV DD or V DD_FT (1)\nTTL Schmitt\ntrigger\nProtection\ndiode\nInput driver\nI/O pin\nOutput driver\nV DD\nProtection\ndiode\nP-MOS\nOutput\ncontrol\nV SS\nN-MOS\nPush-pull or\nV SS\nOpen-drain\nai14784\n1. V DD_FT is a potential specific to five-volt tolerant I/Os and different from V DD .\n9.1.9\nAlternate function configuration\nWhen the I/O Port is programmed as Alternate Function:\n● The Output Buffer is turned on in Open Drain or Push-Pull configuration\n● The Output Buffer is driven by the signal coming from the peripheral (alternate function\nout)\n● The Schmitt Trigger Input is activated\n● The weak pull-up and pull-down resistors are disabled.\n● The data present on the I/O pin is sampled into the Input Data Register every APB2\nclock cycle\n● A read access to the Input Data Register gets the I/O state in open drain mode\n● A read access to the Output Data register gets the last written value in Push-Pull mode\nThe Figure 17 on page 160 shows the Alternate Function Configuration of the I/O Port bit.\nAlso, refer to Section 9.4: AFIO registers on page 177 for further information.\nA set of Alternate Function I/O registers allow you to remap some alternate functions to\ndifferent pins. Refer to Section 9.3: Alternate function I/O and debug configuration (AFIO).\nDoc ID 13902 Rev 14\n159/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nFigure 17. Alternate function configuration\nregister\nAlternate Function Input\nTo on-chip\nperipheral\nRead/write\nWrite\nRead\non\nV DD or V DD_FT (1)\nTTL Schmitt\ntrigger\nProtection\ndiode\nInput driver\nOutput driver\nI/O pin\nV DD\nP-MOS\nOutput\ncontrol\nVSS\nN-MOS\nV SS\nFrom on-chip\nperipheral\nProtection\ndiode\npush-pull or\nopen-drain\nAlternate Function Output\nai14785\n1. V DD_FT is a potential specific to five-volt tolerant I/Os and different from V DD .\n9.1.10\nAnalog configuration\nWhen the I/O Port is programmed as Analog configuration:\n● The Output Buffer is disabled.\n● The Schmitt Trigger Input is de-activated providing zero consumption for every analog\nvalue of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).\n● The weak pull-up and pull-down resistors are disabled.\n● Read access to the Input Data Register gets the value “0”.\nThe Figure 18 on page 161 shows the high impedance-analog configuration of the I/O Port\nbit.\n160/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nFigure 18. High impedance-analog configuration\nInput data\nAnalog Input\nTo on-chip\nperipheral\nRead/write\noff\n0\nV DD or V DD_FT (1)\nTTL Schmitt\ntrigger\nWrite\nRead\nProtection\ndiode\nInput driver\nI/O pin\nProtection\ndiode\nV SS\nFrom on-chip\nperipheral\n9.1.11\nai14786\nGPIO configurations for device peripherals\nTable 22 to Table 33 give the GPIO configurations of the device peripherals.\nTable 22.\nAdvanced timers TIM1/TIM8\nTIM1/8 pinout\nConfiguration\nGPIO configuration\nInput capture channel x Input floating\nOutput compare channel x Alternate function push-pull\nTIM1/8_CHxN Complementary output channel x Alternate function push-pull\nTIM1/8_BKIN Break input Input floating\nTIM1/8_ETR External trigger timer input Input floating\nTIM1/8_CHx\nTable 23.\nGeneral-purpose timers TIM2/3/4/5\nTIM2/3/4/5 pinout\nConfiguration\nGPIO configuration\nInput capture channel x Input floating\nOutput compare channel x Alternate function push-pull\nExternal trigger timer input Input floating\nTIM2/3/4/5_CHx\nTIM2/3/4/5_ETR\nTable 24.\nUSARTs\nUSART pinout\nUSARTx_TX (1)\nConfiguration\nGPIO configuration\nFull duplex Alternate function push-pull\nHalf duplex synchronous mode Alternate function push-pull\nDoc ID 13902 Rev 14\n161/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 24.\nRM0008\nUSARTs (continued)\nUSART pinout\nConfiguration\nGPIO configuration\nFull duplex Input floating / Input pull-up\nHalf duplex synchronous mode Not used. Can be used as a general IO\nUSARTx_CK Synchronous mode Alternate function push-pull\nUSARTx_RTS Hardware flow control Alternate function push-pull\nUSARTx_CTS Hardware flow control Input floating/ Input pull-up\nUSARTx_RX\n1. The USART_TX pin can also be configured as alternate function open drain.\nTable 25.\nSPI\nSPI pinout\nConfiguration\nGPIO configuration\nMaster Alternate function push-pull\nSlave Input floating\nFull duplex / master Alternate function push-pull\nFull duplex / slave Input floating / Input pull-up\nSimplex bidirectional data wire / master Alternate function push-pull\nSimplex bidirectional data wire/ slave Not used. Can be used as a GPIO\nFull duplex / master Input floating / Input pull-up\nFull duplex / slave (point to point) Alternate function push-pull\nFull duplex / slave (multi-slave) Alternate function open drain\nSPIx_SCK\nSPIx_MOSI\nSPIx_MISO Simplex bidirectional data wire / master\nSPIx_NSS\nTable 26.\nNot used. Can be used as a GPIO\nSimplex bidirectional data wire/ slave\n(point to point) Alternate function push-pull\nSimplex bidirectional data wire/ slave\n(multi-slave) Alternate function open drain\nHardware master /slave Input floating/ Input pull-up / Input pull-down\nHardware master/ NSS output enabled Alternate function push-pull\nSoftware Not used. Can be used as a GPIO\nI2S\nI2S pinout\nConfiguration\nGPIO configuration\nMaster Alternate function push-pull\nSlave Input floating\nMaster Alternate function push-pull\nSlave Input floating\nTransmitter Alternate function push-pull\nReceiver Input floating/ Input pull-up/ Input pull-down\nI2Sx_ WS\nI2Sx_CK\nI2Sx_SD\n162/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 26.\nI2S\nI2S pinout\nConfiguration\nGPIO configuration\nMaster Alternate function push-pull\nSlave Not used. Can be used as a GPIO\nI2Sx_MCK\nTable 27.\nI2C\nI2C pinout\nConfiguration\nGPIO configuration\nI2Cx_SCL I2C clock Alternate function open drain\nI2Cx_SDA I2C Data I/O Alternate function open drain\nTable 28.\nBxCAN\nBxCAN pinout\nGPIO configuration\nCAN_TX (Transmit data line) Alternate function push-pull\nCAN_RX (Receive data line) Input floating / Input pull-up\nTable 29.\nUSB (1)\nUSB pinout\nUSB_DM / USB_DP\nGPIO configuration\nAs soon as the USB is enabled, these pins are connected to the USB\ninternal transceiver automatically.\n1. This table applies to low-, medium-, high and XL-density devices only.\nTable 30.\nOTG_FS pin configuration (1)\nOTG_FS pinout\nOTG_FS_SOF\nOTG_FS_VBUS\n(2)\nOTG_FS_ID\nOTG_FS_DM\nConfiguration\nGPIO configuration\nHost AF push-pull, if used\nDevice AF push-pull, if used\nOTG AF push-pull, if used\nHost Input floating\nDevice Input floating\nOTG Input floating\nHost No need if the Force host mode is selected by software\n(FHMOD set in the OTG_FS_GUSBCFG register)\nDevice No need if the Force device mode is selected by software\n(FDMOD set in the OTG_FS_GUSBCFG register)\nOTG Input pull-up\nHost Controlled automatically by the USB power-down\nDevice Controlled automatically by the USB power-down\nOTG Controlled automatically by the USB power-down\nDoc ID 13902 Rev 14\n163/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nOTG_FS pin configuration (1)\nTable 30.\nOTG_FS pinout\nOTG_FS_DP\nConfiguration\nGPIO configuration\nHost Controlled automatically by the USB power-down\nDevice Controlled automatically by the USB power-down\nOTG Controlled automatically by the USB power-down\n1. This table applies to connectivity line devices only.\n2. For the OTG_FS_VBUS pin (PA9) to be used by another shared peripheral or as a general-purpose IO,\nthe PHY Power-down mode has to be active (clear bit 16 in the OTG_FS_GCCFG register).\nTable 31.\nSDIO\nSDIO pinout\nGPIO configuration\nSDIO_CK Alternate function push-pull\nSDIO_CMD Alternate function push-pull\nSDIO[D7:D0] Alternate function push-pull\nThe GPIO configuration of the ADC inputs should be analog.\nFigure 19. ADC / DAC\nADC/DAC pin\nADC/DAC\nTable 32.\nGPIO configuration\nAnalog\nFSMC\nFSMC pinout\n164/1096\nGPIO configuration\nFSMC_A[25:0]\nFSMC_D[15:0] Alternate function push-pull\nFSMC_CK Alternate function push-pull\nFSMC_NOE\nFSMC_NWE Alternate function push-pull\nFSMC_NE[4:1]\nFSMC_NCE[3:2]\nFSMC_NCE4_1\nFSMC_NCE4_2 Alternate function push-pull\nFSMC_NWAIT\nFSMC_CD Input floating/ Input pull-up\nFSMC_NIOS16,\nFSMC_INTR\nFSMC_INT[3:2] Input floating\nFSMC_NL\nFSMC_NBL[1:0] Alternate function push-pull\nFSMC_NIORD, FSMC_NIOWR\nFSMC_NREG Alternate function push-pull\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 33.\nOther IOs\nPins\nAlternate function\nRTC output\nGPIO configuration\nTamper event input Forced by hardware when configuring the\nBKP_CR and BKP_RTCCR registers\nMCO Clock output Alternate function push-pull\nEXTI input lines External input interrupts Input floating / input pull-up / input pull-down\nTAMPER-RTC pin\nDoc ID 13902 Rev 14\n165/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.2\nRM0008\nGPIO registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by words (32-bit).\n9.2.1\nPort configuration register low (GPIOx_CRL) (x=A..G)\nAddress offset: 0x00\nReset value: 0x4444 4444\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n20\n18\n16\nMODE7[1:0] CNF6[1:0] MODE6[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nCNF2[1:0] MODE2[1:0]\nrw rw rw rw\nrw\nrw\nrw\nrw\nCNF1[1:0]\nrw\nrw\nMODE1[1:0]\nrw\nrw\nCNF4[1:0]\n17\nCNF7[1:0] MODE3[1:0]\nMODE5[1:0]\n19\nrw CNF3[1:0]\nCNF5[1:0]\n21\nCNF0[1:0]\nrw\nrw\nBits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 0 .. 7)\n23:22, 19:18, 15:14,\nThese bits are written by software to configure the corresponding I/O port.\n11:10, 7:6, 3:2\nRefer to Table 20: Port bit configuration table on page 156.\nIn input mode (MODE[1:0]=00):\n00: Analog mode\n01: Floating input (reset state)\n10: Input with pull-up / pull-down\n11: Reserved\nIn output mode (MODE[1:0] > 00):\n00: General purpose output push-pull\n01: General purpose output Open-drain\n10: Alternate function output Push-pull\n11: Alternate function output Open-drain\nBits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 0 .. 7)\n21:20, 17:16, 13:12,\nThese bits are written by software to configure the corresponding I/O port.\n9:8, 5:4, 1:0\nRefer to Table 20: Port bit configuration table on page 156.\n00: Input mode (reset state)\n01: Output mode, max speed 10 MHz.\n10: Output mode, max speed 2 MHz.\n11: Output mode, max speed 50 MHz.\n166/1096\nDoc ID 13902 Rev 14\nMODE4[1:0]\nMODE0[1:0]\nrw\nrw RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.2.2\nPort configuration register high (GPIOx_CRH) (x=A..G)\nAddress offset: 0x04\nReset value: 0x4444 4444\n31\n30\n29\nCNF15[1:0]\n28\nMODE15[1:0]\n27\n26\nCNF14[1:0]\n25\n24\n23\nMODE14[1:0]\n22\nCNF13[1:0]\n21\n20\nMODE13[1:0]\n19\n18\nCNF12[1:0]\n17\n16\nMODE12[1:0]\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nCNF11[1:0]\nrw\nMODE11[1:0]\nrw\nrw\nrw\nCNF10[1:0]\nrw\nMODE10[1:0]\nrw\nrw\nrw\nCNF9[1:0]\nrw\nrw\nMODE9[1:0]\nrw\nrw\nCNF8[1:0]\nrw\nrw\nMODE8[1:0]\nrw rw\n17 16\nBits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 .. 15)\n23:22, 19:18, 15:14,\nThese bits are written by software to configure the corresponding I/O port.\n11:10, 7:6, 3:2\nRefer to Table 20: Port bit configuration table on page 156.\nIn input mode (MODE[1:0]=00):\n00: Analog mode\n01: Floating input (reset state)\n10: Input with pull-up / pull-down\n11: Reserved\nIn output mode (MODE[1:0] > 00):\n00: General purpose output push-pull\n01: General purpose output Open-drain\n10: Alternate function output Push-pull\n11: Alternate function output Open-drain\nBits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 8 .. 15)\n21:20, 17:16, 13:12,\nThese bits are written by software to configure the corresponding I/O port.\n9:8, 5:4, 1:0\nRefer to Table 20: Port bit configuration table on page 156.\n00: Input mode (reset state)\n01: Output mode, max speed 10 MHz.\n10: Output mode, max speed 2 MHz.\n11: Output mode, max speed 50 MHz.\n9.2.3\nPort input data register (GPIOx_IDR) (x=A..G)\nAddress offset: 0x08h\nReset value: 0x0000 XXXX\n31 30 29 28 27 26 25 24\n23\n22\n21\n20\n19\n18\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nIDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0\nr r r r r r r r r r r r r r r r\nReserved\nBits 31:16\nReserved, must be kept at reset value.\nBits 15:0 IDRy[15:0]: Port input data (y= 0 .. 15)\nThese bits are read only and can be accessed in Word mode only. They contain the input\nvalue of the corresponding I/O port.\nDoc ID 13902 Rev 14\n167/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.2.4\nRM0008\nPort output data register (GPIOx_ODR) (x=A..G)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\nODR15 ODR14 ODR13 ODR12 ODR11 ODR10\nrw\nrw\nrw\nBits 31:16\nrw\nrw\nrw\n9 8 7 6 5 4 3 2 1 0\nODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0\nrw rw rw rw rw rw rw rw rw rw\nReserved, must be kept at reset value.\nBits 15:0 ODRy[15:0]: Port output data (y= 0 .. 15)\nThese bits can be read and written by software and can be accessed in Word mode only.\nNote: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to\nthe GPIOx_BSRR register (x = A .. G).\n9.2.5\nPort bit set/reset register (GPIOx_BSRR) (x=A..G)\nAddress offset: 0x10\nReset value: 0x0000 0000\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16\nBR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0\nw w w w w w w w w w w w w w w w\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nBS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0\nw w w w w w w w w w w w w w w w\nBits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)\nThese bits are write-only and can be accessed in Word mode only.\n0: No action on the corresponding ODRx bit\n1: Reset the corresponding ODRx bit\nNote: If both BSx and BRx are set, BSx has priority.\nBits 15:0 BSy: Port x Set bit y (y= 0 .. 15)\nThese bits are write-only and can be accessed in Word mode only.\n0: No action on the corresponding ODRx bit\n1: Set the corresponding ODRx bit\n168/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.2.6\nPort bit reset register (GPIOx_BRR) (x=A..G)\nAddress offset: 0x14\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nBR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0\nw w w w w w w w w w w w w w w w\nBits 31:16\nReserved\nBits 15:0 BRy: Port x Reset bit y (y= 0 .. 15)\nThese bits are write-only and can be accessed in Word mode only.\n0: No action on the corresponding ODRx bit\n1: Reset the corresponding ODRx bit\n9.2.7\nPort configuration lock register (GPIOx_LCKR) (x=A..G)\nThis register is used to lock the configuration of the port bits when a correct write sequence\nis applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the\nGPIO. During the write sequence, the value of LCKR[15:0] must not change. When the\nLOCK sequence has been applied on a port bit it is no longer possible to modify the value of\nthe port bit until the next reset.\nEach lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).\nAddress offset: 0x18\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\n18\n17\n16\nLCKK\nReserved\nrw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nLCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:17\nReserved\nDoc ID 13902 Rev 14\n169/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nBit 16 LCKK[16]: Lock key\nThis bit can be read anytime. It can only be modified using the Lock Key Writing Sequence.\n0: Port configuration lock key not active\n1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset\noccurs.\nLOCK key writing sequence:\nWrite 1\nWrite 0\nWrite 1\nRead 0\nRead 1 (this read is optional but confirms that the lock is active)\nNote: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.\nAny error in the lock sequence will abort the lock.\nBits 15:0 LCKy: Port x Lock bit y (y= 0 .. 15)\nThese bits are read write but can only be written when the LCKK bit is 0.\n0: Port configuration not locked\n1: Port configuration locked.\n9.3\nAlternate function I/O and debug configuration (AFIO)\nTo optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin\npackage, it is possible to remap some alternate functions to some other pins. This is\nachieved by software, by programming the AF remap and debug I/O configuration register\n(AFIO_MAPR) on page 179. In this case, the alternate functions are no longer mapped to\ntheir original assignations.\n9.3.1\nUsing OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15\nThe LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O\nPC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the\nGP IOs function.\nNote:\n1 The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by\nentering standby mode) or when the backup domain is supplied by V BAT (V DD no more\nsupplied). In this case the IOs are set in analog mode.\n2 Refer to the note on IO usage restrictions in Section 5.1.2 on page 67.\n9.3.2\nUsing OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1\nThe HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1\nby programming the PD01_REMAP bit in the AF remap and debug I/O configuration register\n(AFIO_MAPR).\nThis remap is available only on 36-, 48- and 64-pin packages (PD0 and PD1 are available\non 100-pin and 144-pin packages, no need for remapping).\nNote:\n170/1096\nThe external interrupt/event function is not remapped. PD0 and PD1 cannot be used for\nexternal interrupt/event generation on 36-, 48- and 64-pin packages.\nDoc ID 13902 Rev 14 RM0008\n9.3.3\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nCAN1 alternate function remapping\nThe CAN signals can be mapped on Port A, Port B or Port D as shown in Table 34. For port\nD, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages.\nTable 34.\nCAN1 alternate function remapping\nAlternate function (1) CAN_REMAP[1:0] =\n“00” CAN_REMAP[1:0] =\n“10” (2) CAN_REMAP[1:0] =\n“11” (3)\nCAN1_RX or CAN_RX PA11 PB8 PD0\nCAN1_TX or CAN_RX PA12 PB9 PD1\n1. CAN1_RX and CAN1_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single\nCAN interface.\n2. Remap not available on 36-pin package\n3. This remapping is available only on 100-pin and 144-pin packages, when PD0 and PD1 are not remapped\non OSC-IN and OSC-OUT.\n9.3.4\nCAN2 alternate function remapping\nCAN2 is available in connectivity line devices. The external signal can be remapped as\nshown in Chapter Table 35.\nTable 35.\n9.3.5\nCAN2 alternate function remapping\nAlternate function CAN2_REMAP = “0” CAN2_REMAP = “1”\nCAN2_RX PB12 PB5\nCAN2_TX PB13 PB6\nJTAG/SWD alternate function remapping\nThe debug interface signals are mapped on the GPIO ports as shown in Table 36.\nTable 36.\nDebug interface signals\nAlternate function GPIO port\nJTMS / SWDIO PA13\nJTCK / SWCLK PA14\nJTDI PA15\nJTDO / TRACESWO PB3\nNJTRST PB4\nTRACECK PE2\nTRACED0 PE3\nTRACED1 PE4\nTRACED2 PE5\nTRACED3 PE6\nDoc ID 13902 Rev 14\n171/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nTo optimize the number of free GPIOs during debugging, this mapping can be configured in\ndifferent ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O\nconfiguration register (AFIO_MAPR). Refer to Table 37\nTable 37.\nDebug port mapping\nSWJ I/O pin assigned\nSWJ _CFG\n[2:0] Available debug ports\n000 PA13 /\nJTMS/\nSWDIO PA14 /\nJTCK/S\nWCLK PA15 /\nJTDI Full SWJ (JTAG-DP + SW-DP)\n(Reset state) X X X X X\n001 Full SWJ (JTAG-DP + SW-DP)\nbut without NJTRST X X X x free\n010 JTAG-DP Disabled and\nSW-DP Enabled X X free free (1) free\n100 JTAG-DP Disabled and\nSW-DP Disabled free free free free free\nOther\nPB3 / JTDO/\nPB4/\nTRACE\nNJTRST\nSWO\nForbidden\n1. Released only if not using asynchronous trace.\n9.3.6\nADC alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR).\nTable 38.\nADC1 external trigger injected conversion alternate function remapping (1)\nAlternate function\nADC1 external trigger injected\nconversion\nADC1_ETRGINJ_REMAP = 0\nADC1 external trigger injected\nconversion is connected to\nEXTI15\nADC1_ETRGINJ_REMAP = 1\nADC1 external trigger injected\nconversion is connected to\nTIM8_CH4\n1. Remap available only for high-density and XL-density devices.\nTable 39.\nADC1 external trigger regular conversion alternate function remapping (1)\nAlternate function\nADC1 external trigger regular\nconversion\nADC1_ETRGREG_REMAP = 0 ADC1_ETRGREG_REMAP = 1\nADC1 external trigger regular\nconversion is connected to\nEXTI11\nADC1 external trigger regular\nconversion is connected to\nTIM8_TRGO\n1. Remap available only for high-density and XL-density devices.\nTable 40.\nADC2 external trigger injected conversion alternate function remapping (1)\nAlternate function\nADC2 external trigger injected\nconversion\nADC2_ETRGINJ_REMAP = 0\nADC2 external trigger injected\nconversion is connected to\nEXTI 15\n1. Remap available only for high-density and XL-density devices.\n172/1096\nDoc ID 13902 Rev 14\nADC2_ETRGINJ_REMAP = 1\nADC2 external trigger injected\nconversion is connected to\nTIM8_CH4 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 41.\nADC2 external trigger regular conversion alternate function remapping (1)\nAlternate function\nADC2_ETRGREG_REG = 0\nADC2 external trigger regular\nconversion\nADC2_ETRGREG_REG = 1\nADC2 external trigger regular\nconversion is connected to\nEXTI11\nADC2 external trigger regular\nconversion is connected to\nTIM8_TRGO\n1. Remap available only for high-density and XL-density devices.\n9.3.7\nTimer alternate function remapping\nTimer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping\npossibilities are listed in Table 44 to Table 46. Refer to AF remap and debug I/O\nconfiguration register (AFIO_MAPR).\nTable 42.\nTIM5 alternate function remapping (1)\nAlternate function\nTIM5_CH4\nTIM5CH4_IREMAP = 0\nTIM5 Channel4 is\nconnected to PA3\nTIM5CH4_IREMAP = 1\nLSI internal clock is connected to TIM5_CH4\ninput for calibration purpose.\n1. Remap available only for high-density, XL-density and connectivity line devices.\nTable 43.\nTIM4 alternate function remapping\nAlternate function TIM4_REMAP = 0 TIM4_REMAP = 1 (1)\nTIM4_CH1 PB6 PD12\nTIM4_CH2 PB7 PD13\nTIM4_CH3 PB8 PD14\nTIM4_CH4 PB9 PD15\n1. Remap available only for 100-pin and for 144-pin package.\nTable 44.\nTIM3 alternate function remapping\nAlternate function\nTIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] =\n“00” (no remap)\n“10” (partial remap) “11” (full remap) (1)\nTIM3_CH1 PA6 PB4 PC6\nTIM3_CH2 PA7 PB5 PC7\nTIM3_CH3 PB0 PC8\nTIM3_CH4 PB1 PC9\n1. Remap available only for 64-pin, 100-pin and 144-pin packages.\nDoc ID 13902 Rev 14\n173/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 45.\nRM0008\nTIM2 alternate function remapping\nAlternate function\nTIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1:\n0] = “00” (no\n0] = “01” (partial 0] = “10” (partial\nremap)\nremap)\nremap) (1)\nTIM2_REMAP[1:\n0] = “11” (full\nremap) (1)\nTIM2_CH1_ETR (2) PA0 PA15 PA0 PA15\nTIM2_CH2 PA1 PB3 PA1 PB3\nTIM2_CH3 PA2 PB10\nTIM2_CH4 PA3 PB11\n1. Remap not available on 36-pin package.\n2. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have\nthis notation: TIM2_CH1_ETR).\nTable 46.\nTIM1 alternate function remapping\nAlternate functions\nmapping\nTIM1_REMAP[1:0] = TIM1_REMAP[1:0] = TIM1_REMAP[1:0] =\n“00” (no remap)\n“01” (partial remap) “11” (full remap) (1)\nTIM1_ETR PA12 PE7\nTIM1_CH1 PA8 PE9\nTIM1_CH2 PA9 PE11\nTIM1_CH3 PA10 PE13\nPA11 PE14\nTIM1_CH4\nTIM1_BKIN\nPB12\n(2)\nPA6 PE15\nTIM1_CH1N PB13 PA7 PE8\nTIM1_CH2N PB14 (2) PB0 PE10\nTIM1_CH3N PB15 (2) PB1 PE12\n1. Remap available only for 100-pin and 144-pin packages.\n2. Remap not available on 36-pin package.\nTable 47.\nTIM9 remapping (1)\nAlternate function\nTIM9_REMAP = 0\nTIM9_REMAP = 1\nTIM9_CH1 PA2 PE5\nTIM9_CH2 PA3 PE6\n1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O\nconfiguration register2 (AFIO_MAPR2).\nTable 48.\nTIM10 remapping (1)\nAlternate function\nTIM10_CH1\nTIM10_REMAP = 0\nPB8\nTIM10_REMAP = 1\nPF6\n1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O\nconfiguration register2 (AFIO_MAPR2).\n174/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTIM11 remapping (1)\nTable 49.\nAlternate function\nTIM11_CH1\nTIM11_REMAP = 0\nPB9\nTIM11_REMAP = 1\nPF7\n1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O\nconfiguration register2 (AFIO_MAPR2).\nTIM13 remapping (1)\nTable 50.\nAlternate function\nTIM13_CH1\nTIM13_REMAP = 0\nPA6\nTIM13_REMAP = 1\nPF8\n1. Refer to the AF remap and debug I/O configuration registerSection 9.4.7: AF remap and debug I/O\nconfiguration register2 (AFIO_MAPR2).\nTIM14 remapping (1)\nTable 51.\nAlternate function\nTIM14_CH1\nTIM14_REMAP = 0\nPA7\nTIM14_REMAP = 1\nPF9\n1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O\nconfiguration register2 (AFIO_MAPR2).\n9.3.8\nUSART alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR).\nTable 52.\nUSART3 remapping\nAlternate function USART3_REMAP[1:0]\n= “00” (no remap) USART3_REMAP[1:0] =\n“01” (partial remap) (1) USART3_REMAP[1:0]\n= “11” (full remap) (2)\nUSART3_TX PB10 PC10 PD8\nUSART3_RX PB11 PC11 PD9\nUSART3_CK PB12 PC12 PD10\nUSART3_CTS PB13 PD11\nUSART3_RTS PB14 PD12\n1. Remap available only for 64-pin, 100-pin and 144-pin packages\n2. Remap available only for 100-pin and 144-pin packages.\nTable 53.\nUSART2 remapping\nAlternate functions USART2_REMAP = 0 USART2_REMAP = 1 (1)\nUSART2_CTS PA0 PD3\nUSART2_RTS PA1 PD4\nUSART2_TX PA2 PD5\nUSART2_RX PA3 PD6\nUSART2_CK PA4 PD7\n1. Remap available only for 100-pin and 144-pin packages.\nDoc ID 13902 Rev 14\n175/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 54.\n9.3.9\nRM0008\nUSART1 remapping\nAlternate function USART1_REMAP = 0 USART1_REMAP = 1\nUSART1_TX PA9 PB6\nUSART1_RX PA10 PB7\nI2C1 alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR)\nTable 55.\nI2C1 remapping\nAlternate function I2C1_REMAP = 0 I2C1_REMAP = 1 (1)\nI2C1_SCL PB6 PB8\nI2C1_SDA PB7 PB9\n1. Remap not available on 36-pin package.\n9.3.10\nSPI1 alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR)\nTable 56.\n9.3.11\nSPI1 remapping\nAlternate function SPI1_REMAP = 0 SPI1_REMAP = 1\nSPI1_NSS PA4 PA15\nSPI1_SCK PA5 PB3\nSPI1_MISO PA6 PB4\nSPI1_MOSI PA7 PB5\nSPI3/I2S3 alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR). This remap is\navailable only in connectivity line devices.\nTable 57.\n9.3.12\nSPI3/I2S3 remapping\nAlternate function SPI3_REMAP = 0 SPI3_REMAP = 1\nSPI3_NSS / I2S3_WS PA15 PA4\nSPI3_SCK / I2S3_CK PB3 PC10\nSPI3_MISO PB4 PC11\nSPI3_MOSI / I2S3_SD PB5 PC12\nEthernet alternate function remapping\nRefer to AF remap and debug I/O configuration register (AFIO_MAPR). Ethernet is available\nonly in connectivity line devices.\n176/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nTable 58.\n9.4\nETH remapping\nAlternate function ETH_REMAP = 0 ETH_REMAP = 1\nRX_DV-CRS_DV PA7 PD8\nRXD0 PC4 PD9\nRXD1 PC5 PD10\nRXD2 PB0 PD11\nRXD3 PB1 PD12\nAFIO registers\nRefer to Section 2.1 on page 46for a list of abbreviations used in register descriptions.\nNote:\nTo read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock\nshould first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register\n(RCC_APB2ENR).\nThe peripheral registers have to be accessed by words (32-bit).\nDoc ID 13902 Rev 14\n177/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.4.1\nRM0008\nEvent control register (AFIO_EVCR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21 20 19 18 17 16\n5 4 3 2 1 0\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\nEVOE\nPORT[2:0]\nPIN[3:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:8 Reserved\nBit 7 EVOE: Event output enable\nSet and cleared by software. When set the EVENTOUT Cortex output is connected to the\nI/O selected by the PORT[2:0] and PIN[3:0] bits.\nBits 6:4 PORT[2:0]: Port selection\nSet and cleared by software. Select the port used to output the Cortex EVENTOUT signal.\nNote: The EVENTOUT signal output capability is not extended to ports PF and PG.\n000: PA selected\n001: PB selected\n010: PC selected\n011: PD selected\n100: PE selected\nBits 3:0 PIN[3:0]: Pin selection (x = A .. E)\nSet and cleared by software. Select the pin used to output the Cortex EVENTOUT signal.\n0000: Px0 selected\n0001: Px1 selected\n0010: Px2 selected\n0011: Px3 selected\n...\n1111: Px15 selected\n178/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.4.2\nAF remap and debug I/O configuration register (AFIO_MAPR)\nAddress offset: 0x04\nReset value: 0x0000 0000\nMemory map and bit definitions for low-, medium- high- and XL-density\ndevices:\n31\n30\n29\n28\n27\n26\n25\n24\n23\nSWJ_\nCFG[2:0]\nReserved\nw\nw\n22\n21\n20\n19\n18\n17\nReserved\nw\nrw\nrw\nrw\nrw\nPD01_\nREMAP\nrw\n14\n13\nCAN_REMAP\n[1:0]\nrw\nrw\nBits 31:27\nReserved\n12\nTIM4_\nREMAP\nrw\n11\nw w w\n10 9 8\nTIM3_REMAP\n[1:0]\nrw\nrw\nTIM2_REMAP\n[1:0]\nrw\nrw\nrw\nTIM5CH\n4_IREM\nAP\nSWJ_CFG[2:0]\nReserved\n15\n16\nADC2_\nADC1_\nADC2_ET ADC1_ET\nTIM5CH\nETRGR\nETRGIN\nRGINJ_R RGREG_\n4_IREM\nEG_RE\nJ_REM\nEMAP\nREMAP\nAP\nMAP\nAP\nrw\n7\n6\nTIM1_REMAP\n[1:0]\nrw\nrw\n5\n4\nUSART3_\nREMAP[1:0]\nrw\nrw\n3\n2\n1\n0\nUSART2_ USART1_ I2C1_ SPI1_\nREMAP REMAP REMAP REMAP\nrw\nrw\nrw\nrw\nReserved\nBits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration\nThese bits are write-only (when read, the value is undefined). They are used to configure the\nSWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD\naccess to the Cortex debug port. The default state after reset is SWJ ON without trace. This\nallows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /\nJTCK pin.\n000: Full SWJ (JTAG-DP + SW-DP): Reset State\n001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST\n010: JTAG-DP Disabled and SW-DP Enabled\n100: JTAG-DP Disabled and SW-DP Disabled\nOther combinations: no effect\nBits 23:21\nReserved.\nBits 20 ADC2_ETRGREG_REMAP: ADC 2 external trigger regular conversion remapping\nSet and cleared by software. This bit controls the trigger input connected to ADC2 external\ntrigger regular conversion. When this bit is reset, the ADC2 external trigger regular\nconversion is connected to EXTI11. When this bit is set, the ADC2 external event regular\nconversion is connected to TIM8_TRGO.\nBits 19 ADC2_ETRGINJ_REMAP: ADC 2 external trigger injected conversion remapping\nSet and cleared by software. This bit controls the trigger input connected to ADC2 external\ntrigger injected conversion. When this bit is reset, the ADC2 external trigger injected\nconversion is connected to EXTI15. When this bit is set, the ADC2 external event injected\nconversion is connected to TIM8_Channel4.\nBits 18 ADC1_ETRGREG_REMAP: ADC 1 external trigger regular conversion remapping\nSet and cleared by software. This bit controls the trigger input connected to ADC1\nExternal trigger regular conversion. When reset the ADC1 External trigger regular\nconversion is connected to EXTI11. When set the ADC1 External Event regular conversion\nis connected to TIM8 TRGO.\nDoc ID 13902 Rev 14\n179/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nBits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping\nSet and cleared by software. This bit controls the trigger input connected to ADC1\nExternal trigger injected conversion. When reset the ADC1 External trigger injected\nconversion is connected to EXTI15. When set the ADC1 External Event injected conversion\nis connected to TIM8 Channel4.\nBits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap\nSet and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset\nthe timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to\nTIM5_CH4 input for calibration purpose.\nNote: This bit is available only in high density value line devices.\nBit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT\nThis bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO\nfunctionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)\nPD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48-\nand 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no\nneed for remapping).\n0: No remapping of PD0 and PD1\n1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,\nBits 14:13 CAN_REMAP[1:0]: CAN alternate function remapping\nThese bits are set and cleared by software. They control the mapping of alternate functions\nCAN_RX and CAN_TX in devices with a single CAN interface.\n00: CAN_RX mapped to PA11, CAN_TX mapped to PA12\n01: Not used\n10: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)\n11: CAN_RX mapped to PD0, CAN_TX mapped to PD1\nBit 12 TIM4_REMAP: TIM4 remapping\nThis bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto\nthe GPIO ports.\n0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)\n1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)\nNote: TIM4_ETR on PE0 is not re-mapped.\nBits 11:10 TIM3_REMAP[1:0]: TIM3 remapping\nThese bits are set and cleared by software. They control the mapping of TIM3 channels 1 to\n4 on the GPIO ports.\n00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)\n01: Not used\n10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)\n11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)\nNote: TIM3_ETR on PE0 is not re-mapped.\nBits 9:8 TIM2_REMAP[1:0]: TIM2 remapping\nThese bits are set and cleared by software. They control the mapping of TIM2 channels 1 to\n4 and external trigger (ETR) on the GPIO ports.\n00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)\n01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)\n10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)\n11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)\n180/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nBits 7:6 TIM1_REMAP[1:0]: TIM1 remapping\nThese bits are set and cleared by software. They control the mapping of TIM1 channels 1 to\n4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.\n00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,\nCH1N/PB13, CH2N/PB14, CH3N/PB15)\n01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,\nCH1N/PA7, CH2N/PB0, CH3N/PB1)\n10: not used\n11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,\nCH1N/PE8, CH2N/PE10, CH3N/PE12)\nBits 5:4 USART3_REMAP[1:0]: USART3 remapping\nThese bits are set and cleared by software. They control the mapping of USART3 CTS,\nRTS,CK,TX and RX alternate functions on the GPIO ports.\n00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)\n01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)\n10: not used\n11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)\nBit 3 USART2_REMAP: USART2 remapping\nThis bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX\nand RX alternate functions on the GPIO ports.\n0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)\n1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)\nBit 2 USART1_REMAP: USART1 remapping\nThis bit is set and cleared by software. It controls the mapping of USART1 TX and RX\nalternate functions on the GPIO ports.\n0: No remap (TX/PA9, RX/PA10)\n1: Remap (TX/PB6, RX/PB7)\nBit 1 I2C1_REMAP: I2C1 remapping\nThis bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA\nalternate functions on the GPIO ports.\n0: No remap (SCL/PB6, SDA/PB7)\n1: Remap (SCL/PB8, SDA/PB9)\nBit 0 SPI1_REMAP: SPI1 remapping\nThis bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,\nMOSI alternate functions on the GPIO ports.\n0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)\n1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)\nDoc ID 13902 Rev 14\n181/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nMemory map and bit definitions for connectivity line devices:\n31\nRes.\n30\n15\nPD01_\nREMAP\n29\n28\nPTP_P TIM2ITR\nSPI3_\nPS_RE\n1_\nREMAP\nMAP IREMAP\nrw rw\n14 13\nCAN1_REMAP\n[1:0]\nrw\nrw\nrw\nBit 31\n27\nw\n11\n10\nTIM4_ TIM3_REMAP\nREMAP\n[1:0]\nrw\nrw\n25\n24\nrw\nw w\n9 8\nTIM2_REMAP\n[1:0]\nrw\n23\n22\n21\n20\n19\nMII_RMI CAN2_ ETH_R\nI_SEL REMAP EMAP\nSWJ_\nCFG[2:0]\nRes.\nrw\n12\n26\nrw\nrw rw rw\n7 6 5\nTIM1_REMAP\n[1:0]\nrw\nrw\n17\n16\nTIM5CH\n4_IREM\nAP\nReserved\nrw\n4\nUSART3_\nREMAP[1:0]\nrw\n18\nrw\n3\n2\n1\n0\nUSART2_ USART1_ I2C1_ SPI1_\nREMAP REMAP REMAP REMAP\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBit 30 PTP_PPS_REMAP: Ethernet PTP PPS remapping\nThis bit is set and cleared by software. It enables the Ethernet MAC PPS_PTS to be output\non the PB5 pin.\n0: PTP_PPS not output on PB5 pin.\n1: PTP_PPS is output on PB5 pin.\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\nBit 29 TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping\nThis bit is set and cleared by software. It controls the TIM2_ITR1 internal mapping.\n0: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.\n1: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\nBit 28 SPI3_REMAP: SPI3/I2S3 remapping\nThis bit is set and cleared by software. It controls the mapping of SPI3_NSS/I2S3_WS,\nSPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD alternate functions on the GPIO\nports.\n0: No remap (SPI_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4,\nSPI3_MOSI-I2S3_SD/PB5)\n1: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11,\nSPI3_MOSI-I2S3_SD/PC12)\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\nBit 27\nReserved\nBits 26:24 SWJ_CFG[2:0]: Serial wire JTAG configuration\nThese bits are write-only (when read, the value is undefined). They are used to configure the\nSWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD\naccess to the Cortex debug port. The default state after reset is SWJ ON without trace. This\nallows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS /\nJTCK pin.\n000: Full SWJ (JTAG-DP + SW-DP): Reset State\n001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST\n010: JTAG-DP Disabled and SW-DP Enabled\n100: JTAG-DP Disabled and SW-DP Disabled\nOther combinations: no effect\nBit 23 MII_RMII_SEL: MII or RMII selection\nThis bit is set and cleared by software. It configures the Ethernet MAC internally for use with\nan external MII or RMII PHY.\n0: Configure Ethernet MAC for connection with an MII PHY\n1: Configure Ethernet MAC for connection with an RMII PHY\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\n182/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\nBit 22 CAN2_REMAP: CAN2 I/O remapping\nThis bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins.\n0: No remap (CAN2_RX/PB12, CAN2_TX/PB13)\n1: Remap (CAN2_RX/PB5, CAN2_TX/PB6)\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\nBit 21 ETH_REMAP: Ethernet MAC I/O remapping\nThis bit is set and cleared by software. It controls the Ethernet MAC connections with the\nPHY.\n0: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)\n1: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)\nNote: This bit is available only in connectivity line devices and is reserved otherwise.\nBits 20:17 Reserved\nBits 16 TIM5CH4_IREMAP: TIM5 channel4 internal remap\nSet and cleared by software. This bit controls the TIM5_CH4 internal mapping. When reset\nthe timer TIM5_CH4 is connected to PA3. When set the LSI internal clock is connected to\nTIM5_CH4 input for calibration purpose.\nBit 15 PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT\nThis bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO\nfunctionality. When the HSE oscillator is not used (application running on internal 8 MHz RC)\nPD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 36-, 48-\nand 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no\nneed for remapping).\n0: No remapping of PD0 and PD1\n1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,\nBits 14:13 CAN1_REMAP[1:0]: CAN1 alternate function remapping\nThese bits are set and cleared by software. They control the mapping of alternate functions\nCAN1_RX and CAN1_TX.\n00: CAN1_RX mapped to PA11, CAN1_TX mapped to PA12\n01: Not used\n10: CAN1_RX mapped to PB8, CAN1_TX mapped to PB9 (not available on 36-pin package)\n11: CAN1_RX mapped to PD0, CAN1_TX mapped to PD1\nBit 12 TIM4_REMAP: TIM4 remapping\nThis bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto\nthe GPIO ports.\n0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)\n1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)\nNote: TIM4_ETR on PE0 is not re-mapped.\nBits 11:10 TIM3_REMAP[1:0]: TIM3 remapping\nThese bits are set and cleared by software. They control the mapping of TIM3 channels 1 to\n4 on the GPIO ports.\n00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)\n01: Not used\n10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)\n11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)\nNote: TIM3_ETR on PE0 is not re-mapped.\nDoc ID 13902 Rev 14\n183/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\nRM0008\nBits 9:8 TIM2_REMAP[1:0]: TIM2 remapping\nThese bits are set and cleared by software. They control the mapping of TIM2 channels 1 to\n4 and external trigger (ETR) on the GPIO ports.\n00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)\n01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)\n10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)\n11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)\nBits 7:6 TIM1_REMAP[1:0]: TIM1 remapping\nThese bits are set and cleared by software. They control the mapping of TIM1 channels 1 to\n4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.\n00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12,\nCH1N/PB13, CH2N/PB14, CH3N/PB15)\n01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,\nCH1N/PA7, CH2N/PB0, CH3N/PB1)\n10: not used\n11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15,\nCH1N/PE8, CH2N/PE10, CH3N/PE12)\nBits 5:4 USART3_REMAP[1:0]: USART3 remapping\nThese bits are set and cleared by software. They control the mapping of USART3 CTS,\nRTS,CK,TX and RX alternate functions on the GPIO ports.\n00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)\n01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)\n10: not used\n11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)\nBit 3 USART2_REMAP: USART2 remapping\nThis bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS,CK,TX\nand RX alternate functions on the GPIO ports.\n0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)\n1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)\nBit 2 USART1_REMAP: USART1 remapping\nThis bit is set and cleared by software. It controls the mapping of USART1 TX and RX\nalternate functions on the GPIO ports.\n0: No remap (TX/PA9, RX/PA10)\n1: Remap (TX/PB6, RX/PB7)\nBit 1 I2C1_REMAP: I2C1 remapping\nThis bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA\nalternate functions on the GPIO ports.\n0: No remap (SCL/PB6, SDA/PB7)\n1: Remap (SCL/PB8, SDA/PB9)\nBit 0 SPI1_REMAP: SPI1 remapping\nThis bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO,\nMOSI alternate functions on the GPIO ports.\n0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)\n1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)\n184/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.4.3\nExternal interrupt configuration register 1 (AFIO_EXTICR1)\nAddress offset: 0x08\nReset value: 0x0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19\n6 5 4 3\n18 17 16\n2 1 0\nReserved\n15\n14\n13\n12\n11\nEXTI3[3:0]\nrw\nrw\nrw\nBits 31:16\n10\n9\n8\n7\nEXTI2[3:0]\nrw\nrw\nrw\nrw\nEXTI1[3:0]\nrw\nrw\nrw\nrw\nEXTI0[3:0]\nrw\nrw\nrw\nrw\nrw\nReserved\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3)\nThese bits are written by software to select the source input for EXTIx external interrupt.\nRefer to Section 10.2.5: External interrupt/event line mapping on page 200\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n9.4.4\nExternal interrupt configuration register 2 (AFIO_EXTICR2)\nAddress offset: 0x0C\nReset value: 0x0000\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19\n6 5 4 3\n18 17 16\n2 1 0\nReserved\nEXTI7[3:0]\nrw\nrw\nrw\nBits 31:16\n7\nEXTI6[3:0]\nrw\nrw\nrw\nrw\nEXTI5[3:0]\nrw\nrw\nrw\nrw\nEXTI4[3:0]\nrw\nrw\nrw\nrw\nrw\nReserved\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x= 4 to 7)\nThese bits are written by software to select the source input for EXTIx external interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\nDoc ID 13902 Rev 14\n185/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.4.5\nRM0008\nExternal interrupt configuration register 3 (AFIO_EXTICR3)\nAddress offset: 0x10\nReset value: 0x0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19\n6 5 4 3\n18 17 16\n2 1 0\nReserved\n15\n14\n13\n12\n11\nEXTI11[3:0]\nrw\nrw\nrw\nBits 31:16\n10\n9\n8\n7\nEXTI10[3:0]\nrw\nrw\nrw\nrw\nEXTI9[3:0]\nrw\nrw\nrw\nrw\nEXTI8[3:0]\nrw\nrw\nrw\nrw\nrw\nReserved\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11)\nThese bits are written by software to select the source input for EXTIx external interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n9.4.6\nExternal interrupt configuration register 4 (AFIO_EXTICR4)\nAddress offset: 0x14\nReset value: 0x0000\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19\n6 5 4 3\n18 17 16\n2 1 0\nReserved\nEXTI15[3:0]\nrw\nrw\nBits 31:16\nrw\n7\nEXTI14[3:0]\nrw\nrw\nrw\nrw\nEXTI13[3:0]\nrw\nrw\nrw\nrw\nEXTI12[3:0]\nrw\nrw\nrw\nrw\nReserved\nBits 15:0 EXTIx[3:0]: EXTI x configuration (x= 12 to 15)\nThese bits are written by software to select the source input for EXTIx external interrupt.\n0000: PA[x] pin\n0001: PB[x] pin\n0010: PC[x] pin\n0011: PD[x] pin\n0100: PE[x] pin\n0101: PF[x] pin\n0110: PG[x] pin\n186/1096\nDoc ID 13902 Rev 14\nrw RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.4.7\nAF remap and debug I/O configuration register2 (AFIO_MAPR2)\nAddress offset: 0x1C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nReserved\n15\n14\n13\n12\n11\n10\nReserved\nrw\nBits 31:11\n9\n8\n7\nFSMC_ TIM14_ TIM13_ TIM11_ TIM10_ TIM9_R\nNADV REMAP REMAP REMAP REMAP EMAP\nrw\nrw\nrw\nrw\nReserved\nrw\nReserved.\nBit 10 FSMC_NADV: NADV connect/disconnect\nThis bit is set and cleared by software. It controls the use of the optional FSMC_NADV\nsignal.\n0: The NADV signal is connected to the output (default)\n1: The NADV signal is not connected. The I/O pin can be used by another peripheral.\nBit 9 TIM14_REMAP: TIM14 remapping\nThis bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate\nfunction onto the GPIO ports.\n0: No remap (PA7)\n1: Remap (PF9)\nBit 8 TIM13_REMAP: TIM13 remapping\nThis bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate\nfunction onto the GPIO ports.\n0: No remap (PA6)\n1: Remap (PF8)\nBit 7 TIM11_REMAP: TIM11 remapping\nThis bit is set and cleared by software. It controls the mapping of the TIM11_CH1 alternate\nfunction onto the GPIO ports.\n0: No remap (PB9)\n1: Remap (PF7)\nBit 6 TIM10_REMAP: TIM10 remapping\nThis bit is set and cleared by software. It controls the mapping of the TIM10_CH1 alternate\nfunction onto the GPIO ports.\n0: No remap (PB8)\n1: Remap (PF6)\nBit 5 TIM9_REMAP: TIM9 remapping\nThis bit is set and cleared by software. It controls the mapping of the TIM9_CH1 and\nTIM9_CH2 alternate functions onto the GPIO ports.\n0: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3)\n1: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6)\nBits 4:0\nReserved.\nDoc ID 13902 Rev 14\n187/1096 General-purpose and alternate-function I/Os (GPIOs and AFIOs)\n9.5\nRM0008\nGPIO and AFIO register maps\nRefer to Table 3 on page 50 for the register boundary addresses. The following tables give\nthe GPIO and AFIO register map and the reset values.\n0x00\nGPIOx_CRL\nOffset Register\nGPIO register map and reset values\n30\n29\nTable 59.\nCNF7 MODE7 CNF6 MODE6 CNF5 MODE5 CNF4 MODE4 CNF3 MODE3 CNF2 MODE2 CNF1 MODE1 CNF0 MODE0\n[1:0] [1:0]\n[1:0] [1:0] [1:0] [1:0]\n[1:0]\n[1:0] [1:0]\n[1:0]\n[1:0]\n[1:0] [1:0] [1:0]\n[1:0]\n[1:0]\nReset value\n0x04\n0x08\n0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0\nCNF MODE1 CNF MODE1 CNF MODE1 CNF MODE1 CNF MODE1 CNF MODE1 CNF\nCNF\nMODE9\nMODE8\nGPIOx_CRH 15\n5\n14\n4\n13\n3\n12\n2\n11\n1\n10\n0\n9\n8\n[1:0]\n[1:0]\n[1:0] [1:0]\n[1:0] [1:0] [1:0] [1:0]\n[1:0]\n[1:0] [1:0]\n[1:0]\n[1:0]\n[1:0] [1:0]\n[1:0]\nReset value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0\nGPIOx_IDR\nIDR[15:0]l\nReserved\nReset value\n0x0C\nGPIOx_ODR\nGPIOx_BSRR\nReset value\n0x14\n0 0\n0\n0\n0 0\n0 0 0 0 0 0 0\n0\n0\n0\n0 0\n0\n0 0\n0 0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0\n0\n0 0\nReserved\n0\n0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\n0\n0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\nLCK[15:0]\n0 0\n0\n0\n0 0\n0\n0\n0 0\nEVOE\nAFIO_EVCR\nReserved\nUSART1_REMAP I2C1_REMAP SPI1_REMAP\n0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0\n0 0\n0 0 0 0 0 0\n0 0 0 0 0 0 0\nPORT[2:0] PIN[3:0]\n0\n0\n0\n0\n0\n0\nReserved\n0\n0 0\nReset value\nAFIO_MAPR\nconnectivity line\ndevices\n0\nReserved\nAFIO_MAPR\nlow-, medium-,\nhigh- and XL-\ndensity devices\n188/1096\n0 0\nAFIO register map and reset values\nRegister\nReset value\n0x04\n0\nBR[15:0]\nReset value\n0x04\n0\nBSR[15:0]\nReset value\n0x00\n0\nReserved\nGPIOx_LCKR\nOffset\n0 0\nBR[15:0]\nGPIOx_BRR\nTable 60.\n0\nODR[15:0]\nReset value\n0x18\n0\nReserved\nReset value\n0x10\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose and alternate-function I/Os (GPIOs and AFIOs)\n0\nReserved\nReset value\n0x1C\nAFIO_MAPR2\n0\n0\n0\n0\n0\n0\n0\n0\n0\nEXTI5[3:0]\n0\n0\n0\n0\nEXTI9[3:0]\n0\n0\n0\n0\nEXTI10[3:0]\n0\n0 0 0\nEXTI0[3:0]\n0\n0\n0\n0\nEXTI4[3:0]\n0\n0\n0\n0\nEXTI8[3:0]\n0\n0\n0\n0\nEXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]\n0 0 0\n0\n0\n0\nREMAP\nReset value\n0\n0\n0\nReserved\nReserved\n0\nEXTI11[3:0]\nAFIO_MAPR2\n0\n0\nReset value\n0x1C\n0\nEXTI1[3:0]\n0 0 0 0\n0 0 0 0 0 0\n0 0 0 0\n0\n0\nReserved\n0 0 0\n0\n0\n0\n0\nReserved\n0\nAFIO_EXTICR4\n0\n0\n0\n0x14\n0\n0\nEXTI6[3:0]\n0\nReserved\nReset value\n0\n0\n0\nAFIO_EXTICR3\n0\nEXTI2[3:0]\n0\n0x10\n0\n0\nReserved\nReset value\n0\nEXTI7[3:0]\n0\n0x0C\n0\n0\nReset value\nAFIO_EXTICR2\nEXTI3[3:0]\n0\nReserved\n0\n0\n0\n0\nTIM13_REMAP\n0\nTIM14_REMAP\nAFIO_EXTICR1\n0\nReserved\n0x08\nSWJ_\nCFG[2:0]\nFSMC_NADV\nReset value\nReserved\nAFIO_MAPR\n0x04\nAFIO register map and reset values (continued)\nRegister\nOffset\nTable 60.\n0 0 0 0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n189/1096 Interrupts and events\n10\nRM0008\nInterrupts and events\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis Section applies to the whole STM32F10xxx family, unless otherwise specified.\n10.1\nNested vectored interrupt controller (NVIC)\nFeatures\n● 68 (not including the sixteen Cortex™-M3 interrupt lines)\n● 16 programmable priority levels (4 bits of interrupt priority are used)\n● Low-latency exception and interrupt handling\n● Power management control\n● Implementation of System Control Registers\nThe NVIC and the processor core interface are closely coupled, which enables low latency\ninterrupt processing and efficient processing of late arriving interrupts.\nAll interrupts including the core exceptions are managed by the NVIC. For more information\non exceptions and NVIC programming, refer to STM32F10xxx Cortex-M3 programming\nmanual (see Related documents on page 1).\n10.1.1\nSysTick calibration value register\nThe SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with\nthe SysTick clock set to 9 MHz (max HCLK/8).\n10.1.2\nInterrupt and exception vectors\nTable 61 and Table 63 are the vector tables for connectivity line and other STM32F10xxx\ndevices, respectively.\n190/1096\nVector table for connectivity line devices\nTable 61.\nType of\npriority\n- -\n-3 fixed\nAcronym\nDescription\nAddress\n- Reserved 0x0000_0000\nReset Reset 0x0000_0004\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\nVector table for connectivity line devices (continued)\nPosition\nTable 61.\nType of\npriority -2 fixed NMI Non maskable interrupt. The RCC\nClock Security System (CSS) is\nlinked to the NMI vector. 0x0000_0008\n-1 fixed HardFault All class of fault 0x0000_000C\n0 settable MemManage Memory management 0x0000_0010\n1 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014\n2 settable UsageFault Undefined instruction or illegal state 0x0000_0018\n- - - Reserved 3 settable SVCall System service call via SWI\ninstruction 0x0000_002C\n4 settable Debug Monitor Debug Monitor 0x0000_0030\n- - - Reserved 0x0000_0034\n5 settable PendSV Pendable request for system service 0x0000_0038\n6 settable SysTick System tick timer 0x0000_003C\n0 7 settable WWDG Window Watchdog interrupt 0x0000_0040\n1 8 settable PVD PVD through EXTI Line detection\ninterrupt 0x0000_0044\n2 9 settable TAMPER Tamper interrupt 0x0000_0048\n3 10 settable RTC RTC global interrupt 0x0000_004C\n4 11 settable FLASH Flash global interrupt 0x0000_0050\n5 12 settable RCC RCC global interrupt 0x0000_0054\n6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058\n7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C\n8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060\n9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064\n10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068\n11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C\n12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070\n13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074\n14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078\n15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C\n16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080\n17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084\n18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088\nAcronym\nDescription\nDoc ID 13902 Rev 14\nAddress\n0x0000_001C -\n0x0000_002B\n191/1096 Interrupts and events\nType of\npriority 19 26 settable CAN1_TX CAN1 TX interrupts 0x0000_008C\n20 27 settable CAN1_RX0 CAN1 RX0 interrupts 0x0000_0090\n21 28 settable CAN1_RX1 CAN1 RX1 interrupt 0x0000_0094\n22 29 settable CAN1_SCE CAN1 SCE interrupt 0x0000_0098\n23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C\n24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0\n25 32 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4\n26 33 settable TIM1_TRG_COM TIM1 Trigger and Commutation\ninterrupts 0x0000_00A8\n27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC\n28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0\n29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4\n30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8\nAcronym\nDescription\n2 C1\nAddress\n31 38 settable I2C1_EV I event interrupt 0x0000_00BC\n32 39 settable I2C1_ER I 2 C1 error interrupt 0x0000_00C0\nI2C2_EV I 2 C2 event interrupt 0x0000_00C4\n2 C2 error interrupt 0x0000_00C8\n33\n192/1096\nVector table for connectivity line devices (continued)\nPosition\nTable 61.\nRM0008\n40\nsettable\n34 41 settable I2C2_ER I 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC\n36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0\n37 44 settable USART1 USART1 global interrupt 0x0000_00D4\n38 45 settable USART2 USART2 global interrupt 0x0000_00D8\n39 46 settable USART3 USART3 global interrupt 0x0000_00DC\n40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0\n41 48 settable RTCAlarm RTC alarm through EXTI line\ninterrupt 0x0000_00E4\n42 49 settable OTG_FS_WKUP USB On-The-Go FS Wakeup\nthrough EXTI line interrupt 0x0000_00E8\n- - - - Reserved 50 57 settable TIM5 TIM5 global interrupt 0x0000_0108\n51 58 settable SPI3 SPI3 global interrupt 0x0000_010C\n52 59 settable UART4 UART4 global interrupt 0x0000_0110\n53 60 settable UART5 UART5 global interrupt 0x0000_0114\n54 61 settable TIM6 TIM6 global interrupt 0x0000_0118\n55 62 settable TIM7 TIM7 global interrupt 0x0000_011C\nDoc ID 13902 Rev 14\n0x0000_00EC -\n0x0000_0104 RM0008\nInterrupts and events\nVector table for connectivity line devices (continued)\nPosition\nTable 61.\nType of\npriority 56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120\n57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124\n58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128\n59 66 settable DMA2_Channel4 DMA2 Channel4 global interrupt 0x0000_012C\n60 67 settable DMA2_Channel5 DMA2 Channel5 global interrupt 0x0000_0130\n61 68 settable ETH Ethernet global interrupt 0x0000_0134\n62 69 settable ETH_WKUP Ethernet Wakeup through EXTI line\ninterrupt 0x0000_0138\n63 70 settable CAN2_TX CAN2 TX interrupts 0x0000_013C\n64 71 settable CAN2_RX0 CAN2 RX0 interrupts 0x0000_0140\n65 72 settable CAN2_RX1 CAN2 RX1 interrupt 0x0000_0144\n66 73 settable CAN2_SCE CAN2 SCE interrupt 0x0000_0148\n67 74 settable OTG_FS USB On The Go FS global interrupt 0x0000_014C\nTable 62.\n-\n0\nAcronym\nAddress\nVector table for XL-density devices\nType of\npriority\n-\nDescription\nAcronym\nDescription\nAddress\n- Reserved 0x0000_0000\n-3 fixed Reset Reset 0x0000_0004\n-2 fixed NMI Nonmaskable interrupt. The RCC\nClock Security System (CSS) is\nlinked to the NMI vector. 0x0000_0008\n-1 fixed HardFault All class of fault 0x0000_000C\n0 settable MemManage Memory management 0x0000_0010\n1 settable BusFault Prefetch fault, memory access fault 0x0000_0014\n2 settable UsageFault Undefined instruction or illegal state 0x0000_0018\n- - Reserved 0x0000_001C -\n0x0000_002B\n3 settable SVCall System service call via SWI\ninstruction 0x0000_002C\n4 settable Debug Monitor Debug monitor 0x0000_0030\n- - Reserved 0x0000_0034\n5 settable PendSV Pendable request for system service 0x0000_0038\n6 settable SysTick Systick timer 0x0000_003C\n7 settable WWDG Window watchdog interrupt 0x0000_0040\n-\n-\nDoc ID 13902 Rev 14\n193/1096 Interrupts and events\n194/1096\nPosition\nTable 62.\nRM0008\nVector table for XL-density devices (continued)\nType of\npriority\nAcronym\nDescription\nAddress\n1 8 settable PVD PVD through EXTI Line detection\ninterrupt 0x0000_0044\n2 9 settable TAMPER Tamper interrupt 0x0000_0048\n3 10 settable RTC RTC global interrupt 0x0000_004C\n4 11 settable FLASH Flash global interrupt 0x0000_0050\n5 12 settable RCC RCC global interrupt 0x0000_0054\n6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058\n7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C\n8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060\n9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064\n10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068\n11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C\n12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070\n13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074\n14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078\n15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C\n16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080\n17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084\n18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088\n19 26 settable USB_HP_CAN_TX USB high priority or CAN TX\ninterrupts 0x0000_008C\n20 27 settable USB_LP_CAN_RX0 USB low priority or CAN RX0\ninterrupts 0x0000_0090\n21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094\n22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098\n23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C\n24 31 settable TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9\nglobal interrupt 0x0000_00A0\n25 32 settable TIM1_UP_TIM10 TIM1 Update interrupt and TIM10\nglobal interrupt 0x0000_00A4\n26 33 settable TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation\n0x0000_00A8\ninterrupts and TIM11 global interrupt\n27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC\n28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0\n29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4\n30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\nPosition\nTable 62.\nVector table for XL-density devices (continued)\nType of\npriority\nAcronym\nDescription\nAddress\n31 38 settable I2C1_EV I2C1 event interrupt 0x0000_00BC\n32 39 settable I2C1_ER I2C1 error interrupt 0x0000_00C0\n33 40 settable I2C2_EV I2C2 event interrupt 0x0000_00C4\n34 41 settable I2C2_ER I2C2 error interrupt 0x0000_00C8\n35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC\n36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0\n37 44 settable USART1 USART1 global interrupt 0x0000_00D4\n38 45 settable USART2 USART2 global interrupt 0x0000_00D8\n39 46 settable USART3 USART3 global interrupt 0x0000_00DC\n40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0\n41 48 settable RTCAlarm RTC alarm through EXTI line\ninterrupt 0x0000_00E4\n42 49 settable USBWakeUp USB wakeup from suspend through\nEXTI line interrupt 0x0000_00E8\n43 50 settable TIM8_BRK_TIM12 TIM8 Break interrupt and TIM12\nglobal interrupt 0x0000_00EC\n44 51 settable TIM8_UP_TIM13 TIM8 Update interrupt and TIM13\nglobal interrupt 0x0000_00F0\n45 52 settable TIM8_TRG_COM_TIM14 TIM8 Trigger and Commutation\n0x0000_00F4\ninterrupts and TIM14 global interrupt\n46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8\n47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC\n48 55 settable FSMC FSMC global interrupt 0x0000_0100\n49 56 settable SDIO SDIO global interrupt 0x0000_0104\n50 57 settable TIM5 TIM5 global interrupt 0x0000_0108\n51 58 settable SPI3 SPI3 global interrupt 0x0000_010C\n52 59 settable UART4 UART4 global interrupt 0x0000_0110\n53 60 settable UART5 UART5 global interrupt 0x0000_0114\n54 61 settable TIM6 TIM6 global interrupt 0x0000_0118\n55 62 settable TIM7 TIM7 global interrupt 0x0000_011C\n56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120\n57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124\n58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128\n59 66 settable DMA2_Channel4_5 DMA2 Channel4 and DMA2\nChannel5 global interrupts 0x0000_012C\nDoc ID 13902 Rev 14\n195/1096 Interrupts and events\n196/1096\nVector table for other STM32F10xxx devices\nPosition\nTable 63.\nRM0008\nType of\npriority\n- -\n-3\nAcronym\nDescription\nAddress\n- Reserved 0x0000_0000\nfixed Reset Reset 0x0000_0004\n-2 fixed NMI Non maskable interrupt. The RCC\nClock Security System (CSS) is\nlinked to the NMI vector. 0x0000_0008\n-1 fixed HardFault All class of fault 0x0000_000C\n0 settable MemManage Memory management 0x0000_0010\n1 settable BusFault Prefetch fault, memory access fault 0x0000_0014\n2 settable UsageFault Undefined instruction or illegal state 0x0000_0018\n- - - Reserved 3 settable SVCall System service call via SWI\ninstruction 0x0000_002C\n4 settable Debug Monitor Debug Monitor 0x0000_0030\n- - - Reserved 0x0000_0034\n5 settable PendSV Pendable request for system service 0x0000_0038\n6 settable SysTick System tick timer 0x0000_003C\n0 7 settable WWDG Window watchdog interrupt 0x0000_0040\n1 8 settable PVD PVD through EXTI Line detection\ninterrupt 0x0000_0044\n2 9 settable TAMPER Tamper interrupt 0x0000_0048\n3 10 settable RTC RTC global interrupt 0x0000_004C\n4 11 settable FLASH Flash global interrupt 0x0000_0050\n5 12 settable RCC RCC global interrupt 0x0000_0054\n6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058\n7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C\n8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060\n9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064\n10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068\n11 18 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C\n12 19 settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070\n13 20 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074\n14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078\n15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C\n16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080\nDoc ID 13902 Rev 14\n0x0000_001C -\n0x0000_002B RM0008\nInterrupts and events\nVector table for other STM32F10xxx devices (continued)\nPosition\nTable 63.\nType of\npriority 17 24 settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084\n18 25 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088\n19 26 settable USB_HP_CAN_\nTX USB High Priority or CAN TX\ninterrupts 0x0000_008C\n20 27 settable USB_LP_CAN_\nRX0 USB Low Priority or CAN RX0\ninterrupts 0x0000_0090\n21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094\n22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098\n23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C\n24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0\n25 32 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4\n26 33 settable TIM1_TRG_COM TIM1 Trigger and Commutation\ninterrupts 0x0000_00A8\n27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC\n28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0\n29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4\n30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8\nAcronym\nDescription\n2 C1\nAddress\n31 38 settable I2C1_EV I event interrupt 0x0000_00BC\n32 39 settable I2C1_ER I 2 C1 error interrupt 0x0000_00C0\n33\n40\nsettable\nI2C2_EV\nI 2 C2 event interrupt 0x0000_00C4\n2 C2 error interrupt 0x0000_00C8\n34 41 settable I2C2_ER I 35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC\n36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0\n37 44 settable USART1 USART1 global interrupt 0x0000_00D4\n38 45 settable USART2 USART2 global interrupt 0x0000_00D8\n39 46 settable USART3 USART3 global interrupt 0x0000_00DC\n40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0\n41 48 settable RTCAlarm RTC alarm through EXTI line\ninterrupt 0x0000_00E4\n42 49 settable USBWakeup USB wakeup from suspend through\nEXTI line interrupt 0x0000_00E8\n43 50 settable TIM8_BRK TIM8 Break interrupt 0x0000_00EC\n44 51 settable TIM8_UP TIM8 Update interrupt 0x0000_00F0\n45 52 settable TIM8_TRG_COM TIM8 Trigger and Commutation\ninterrupts 0x0000_00F4\n46 53 settable TIM8_CC TIM8 Capture Compare interrupt 0x0000_00F8\nDoc ID 13902 Rev 14\n197/1096 Interrupts and events\n10.2\nVector table for other STM32F10xxx devices (continued)\nPosition\nTable 63.\nRM0008\nType of\npriority 47 54 settable ADC3 ADC3 global interrupt 0x0000_00FC\n48 55 settable FSMC FSMC global interrupt 0x0000_0100\n49 56 settable SDIO SDIO global interrupt 0x0000_0104\n50 57 settable TIM5 TIM5 global interrupt 0x0000_0108\n51 58 settable SPI3 SPI3 global interrupt 0x0000_010C\n52 59 settable UART4 UART4 global interrupt 0x0000_0110\n53 60 settable UART5 UART5 global interrupt 0x0000_0114\n54 61 settable TIM6 TIM6 global interrupt 0x0000_0118\n55 62 settable TIM7 TIM7 global interrupt 0x0000_011C\n56 63 settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120\n57 64 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124\n58 65 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128\n59 66 settable DMA2_Channel4_5 DMA2 Channel4 and DMA2\nChannel5 global interrupts 0x0000_012C\nAcronym\nDescription\nAddress\nExternal interrupt/event controller (EXTI)\nThe external interrupt/event controller consists of up to 20 edge detectors in connectivity line\ndevices, or 19 edge detectors in other devices for generating event/interrupt requests. Each\ninput line can be independently configured to select the type (pulse or pending) and the\ncorresponding trigger event (rising or falling or both). Each line can also masked\nindependently. A pending register maintains the status line of the interrupt requests\n10.2.1\nMain features\nThe EXTI controller main features are the following:\n10.2.2\n● Independent trigger and mask on each interrupt/event line\n● Dedicated status bit for each interrupt line\n● Generation of up to 20 software event/interrupt requests\n● Detection of external signal with pulse width lower than APB2 clock period. Refer to the\nelectrical characteristics section of the datasheet for details on this parameter.\nBlock diagram\nThe block diagram is shown in Figure 20.\n198/1096\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\nFigure 20. External interrupt/event controller block diagram\n!-\"!  Interrupts and events\nRM0008\ngenerated. The pending bit corresponding to the interrupt line is also set. This request is\nreset by writing a ‘1’ in the pending register.\nTo generate the event, the event line should be configured and enabled. This is done by\nprogramming the two trigger registers with the desired edge detection and by enabling the\nevent request by writing a ‘1’ to the corresponding bit in the event mask register. When the\nselected edge occurs on the event line, an event pulse is generated. The pending bit\ncorresponding to the event line is not set\nAn interrupt/event request can also be generated by software by writing a ‘1’ in the software\ninterrupt/event register.\nHardware interrupt selection\nTo configure the 20 lines as interrupt sources, use the following procedure:\n● Configure the mask bits of the 20 Interrupt lines (EXTI_IMR)\n● Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and\nEXTI_FTSR)\n● Configure the enable and mask bits that control the NVIC IRQ channel mapped to the\nExternal Interrupt Controller (EXTI) so that an interrupt coming from one of the 20 lines\ncan be correctly acknowledged.\nHardware event selection\nTo configure the 20 lines as event sources, use the following procedure:\n● Configure the mask bits of the 20 Event lines (EXTI_EMR)\n● Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)\nSoftware interrupt/event selection\nThe 20 lines can be configured as software interrupt/event lines. The following is the\nprocedure to generate a software interrupt.\n10.2.5\n● Configure the mask bits of the 20 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)\n● Set the required bit of the software interrupt register (EXTI_SWIER)\nExternal interrupt/event line mapping\nThe 112 GPIOs are connected to the 16 external interrupt/event lines in the following\nmanner:\n200/1096\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\nFigure 21. External interrupt/event GPIO mapping\nEXTI0[3:0] bits in AFIO_EXTICR1 register\nPA0\nPB0\nPC0\nPD0\nEXTI0\nPE0\nPF0\nPG0\nEXTI1[3:0] bits in AFIO_EXTICR1 register\nPA1\nPB1\nPC1\nPD1\nEXTI1\nPE1\nPF1\nPG1\nEXTI15[3:0] bits in AFIO_EXTICR4 register\nPA15\nPB15\nPC15\nPD15\nEXTI15\nPE15\nPF15\nPG15\n1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO\nclock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register\n(RCC_APB2ENR) for low-, medium-, high- and XL-density devices and, to Section 8.3.7: APB2 peripheral\nclock enable register (RCC_APB2ENR) for connectivity line devices.\nThe four other EXTI lines are connected as follows:\n● EXTI line 16 is connected to the PVD output\n● EXTI line 17 is connected to the RTC Alarm event\n● EXTI line 18 is connected to the USB Wakeup event\n● EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity\nline devices)\nDoc ID 13902 Rev 14\n201/1096 Interrupts and events\n10.3\nRM0008\nEXTI registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by words (32-bit).\n10.3.1\nInterrupt mask register (EXTI_IMR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19 18 17 16\nMR19 MR18 MR17 MR16\nrw rw rw rw\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nMR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:20 Reserved, must be kept at reset value (0).\nBits 19:0 MRx: Interrupt Mask on line x\n0: Interrupt request from Line x is masked\n1: Interrupt request from Line x is not masked\nNote: Bit 19 is used in connectivity line devices only and is reserved otherwise.\n10.3.2\nEvent mask register (EXTI_EMR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19 18 17 16\nMR19 MR18 MR17 MR16\nrw rw rw rw\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nMR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:20 Reserved, must be kept at reset value (0).\nBits 19:0 MRx: Event mask on line x\n0: Event request from Line x is masked\n1: Event request from Line x is not masked\nNote: Bit 19 is used in connectivity line devices only and is reserved otherwise.\n202/1096\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\n10.3.3\nRising trigger selection register (EXTI_RTSR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19 18 17 16\nTR19 TR18 TR17 TR16\nReserved\nrw rw rw rw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nTR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:20\nReserved, must be kept at reset value (0).\nBits 19:0 TRx: Rising trigger event configuration bit of line x\n0: Rising trigger disabled (for Event and Interrupt) for input line\n1: Rising trigger enabled (for Event and Interrupt) for input line.\nNote: Bit 19 is used in connectivity line devices only and is reserved otherwise.\nNote:\nThe external wakeup lines are edge triggered, no glitches must be generated on these lines.\nIf a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the\npending bit will not be set.\nRising and Falling edge triggers can be set for the same interrupt line. In this configuration,\nboth generate a trigger condition.\n10.3.4\nFalling trigger selection register (EXTI_FTSR)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19 18 17 16\nTR19 TR18 TR17 TR16\nReserved\nrw rw rw rw\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nTR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw\nBits 31:20\nReserved, must be kept at reset value (0).\nBits 19:0 TRx: Falling trigger event configuration bit of line x\n0: Falling trigger disabled (for Event and Interrupt) for input line\n1: Falling trigger enabled (for Event and Interrupt) for input line.\nNote: Bit 19 used in connectivity line devices and is reserved otherwise.\nNote:\nThe external wakeup lines are edge triggered, no glitches must be generated on these lines.\nIf a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the\npending bit will not be set.\nRising and Falling edge triggers can be set for the same interrupt line. In this configuration,\nboth generate a trigger condition.\nDoc ID 13902 Rev 14\n203/1096 Interrupts and events\n10.3.5\nRM0008\nSoftware interrupt event register (EXTI_SWIER)\nAddress offset: 0x10\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\nSWIER SWIER SWIER SWIER SWIER SWIER SWIER\n15\n14\n13\n12\n11\n10\n9\nrw\nrw\nrw\nBits 31:20\nrw\nrw\nrw\n19\n18\n17\n16\nSWIER SWIER SWIER SWIER\n19\n18\n17\n16\nrw\n7\n6\n5\n4\nrw rw rw rw\n3 2 1 0\nSWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER\n8\n7\n6\n5\n4\n3\n2\n1\n0\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value (0).\nBits 19:0 SWIERx: Software interrupt on line x\nWriting a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the\ninterrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt request is\ngenerated.\nThis bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit).\nNote: Bit 19 used in connectivity line devices and is reserved otherwise.\n10.3.6\nPending register (EXTI_PR)\nAddress offset: 0x14\nReset value: undefined\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19 18 17 16\nPR19 PR18 PR17 PR16\nrc_w1 rc_w1 rc_w1 rc_w1\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nPR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0\nrc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1\nBits 31:20\nReserved, must be kept at reset value (0).\nBits 19:0 PRx: Pending bit\n0: No trigger request occurred\n1: selected trigger request occurred\nThis bit is set when the selected edge event arrives on the external interrupt line. This bit is\ncleared by writing a 1 into the bit or by changing the sensitivity of the edge detector.\nNote: Bit 19 is used in connectivity line devices only and is reserved otherwise.\n204/1096\nDoc ID 13902 Rev 14 RM0008\nInterrupts and events\n10.3.7\nEXTI register map\nThe following table gives the EXTI register map and the reset values. Bits 19 in all registers,\nare used in connectivity line devices and is reserved otherwise.\nOffset\n0x00\nExternal interrupt/event controller register map and reset values\nRegister\nEXTI_IMR\n31\nTable 64.\nReset value\n0x04\nEXTI_EMR\n0\nEXTI_RTSR\nEXTI_FTSR\nEXTI_SWIER\nEXTI_PR\nReset value\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0\nTR[19:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nTR[19:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nSWIER[19:0]\nReserved\nReset value\n0x14\n0\nReserved\nReset value\n0x10\n0\nMR[19:0]\n0\nReset value\n0x0C\n0\nReserved\nReset value\n0x08\nMR[19:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nPR[19:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n205/1096 Analog-to-digital converter (ADC)\n11\nRM0008\nAnalog-to-digital converter (ADC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis Section applies to the whole STM32F10xxx family, unless otherwise specified.\n11.1\nADC introduction\nThe 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18\nmultiplexed channels allowing it measure signals from 16 external and two internal sources.\nA/D conversion of the various channels can be performed in single, continuous, scan or\ndiscontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit\ndata register.\nThe analog watchdog feature allows the application to detect if the input voltage goes\noutside the user-defined high or low thresholds.\nThe ADC input clock is generated from the PCLK2 clock divided by a prescaler and it must\nnot exceed 14 MHz, refer to Figure 8: Clock tree for low-, medium-, high- and XL-density\ndevices, and to Figure 11: Clock tree for connectivity line devices.\n206/1096\nDoc ID 13902 Rev 14 RM0008\n11.2\nAnalog-to-digital converter (ADC)\nADC main features\n● 12-bit resolution\n● Interrupt generation at End of Conversion, End of Injected conversion and Analog\nwatchdog event\n● Single and continuous conversion modes\n● Scan mode for automatic conversion of channel 0 to channel ‘n’\n● Self-calibration\n● Data alignment with in-built data coherency\n● Channel by channel programmable sampling time\n● External trigger option for both regular and injected conversion\n● Discontinuous mode\n● Dual mode (on devices with 2 ADCs or more)\n● ADC conversion time:\n– STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)\n– STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz)\n– STM32F102xx USB access line devices: 1.2 µs at 48 MHz\n– STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)\n● ADC supply requirement: 2.4 V to 3.6 V\n● ADC input range: V REF- ≤ V IN ≤ V REF+\n● DMA request generation during regular channel conversion\nThe block diagram of the ADC is shown in Figure 22.\nNote: V REF- ,if available (depending on package), must be tied to V SSA .\n11.3 ADC functional description\nFigure 22 shows a single ADC block diagramand Table 65 gives the ADC pin description.\nDoc ID 13902 Rev 14\n207/1096 Analog-to-digital converter (ADC)\nRM0008\nFigure 22. Single ADC block diagram\nFlags\nEnd of conversion\nEnd of injected conversion\nAnalog watchdog event\nInterrupt\nenable bits\nEOC EOCIE\nJEOC JEOCIE\nAWD AWDIE\nADC Interrupt to NVIC\nAnalog\nwatchdog\nCompare Result\nHigh Threshold (12 bits)\nLow Threshold (12 bits)\nInjected data registers\n(4 x 16 bits)\nV REF+\nV REF-\nRegular data register\n(16 bits)\nV DDA\nV SSA\nAnalog\nDMA request\nMUX\nADCx_IN0\nADCx_IN1\nGPIO\nPorts\nup to 4\nup to 16\nADCx_IN15\nADCCLK\nInjected\nchannels\nAnalog to digital\nRegular\nchannels\nconverter\nTemp. sensor\nV REFINT\nFrom ADC prescaler\nJEXTSEL[2:0] bits\nTIM1_TRGO\nTIM1_CH4\nTIM2_TRGO\nTIM2_CH1\nTIM3_CH4\nTIM4_TRGO\nEXTI_15\nJEXTRIG\nbit\nStart trigger\n(injected group)\nTIM8_CH4 (2)\nJEXTSEL[2:0] bits\nADCx-ETRGINJ_REMAP bit\nEXTRIG\nbit\nEXTSEL[2:0] bits\nTIM1_CH1\nTIM1_CH2\nTIM1_CH3\nTIM2_CH2\nTIM3_TRGO\nTIM4_CH4\nStart trigger\n(regular group)\nTIM1_TRGO\nTIM1_CH4\nTIM4_CH3\nTIM8_CH2\nTIM8_CH4\nTIM5_TRGO\nTIM5_CH4\n(2)\nTIM8_TRGO\nADCx_ETRGREG_REMAP bit\nStart trigger\n(injected group)\nEXTSEL[2:0] bits\nTIM3_CH1\nTIM2_CH3\nTIM1_CH3\nTIM8_CH1\nTIM8_TRGO\nTIM5_CH1\nTIM5_CH3\nEXTI_11\nJEXTRIG\nbit\nEXTRIG\nbit\nStart trigger\n(regular group)\nTriggers for ADC3 (1)\nai14802d\n1. ADC3 has regular and injected conversion triggers different from those of ADC1 and ADC2.\n2. TIM8_CH4 and TIM8_TRGO with their corresponding remap bits exist only in High-density and XL-density\nproducts.\n208/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nTable 65.\nADC pins\nName\nSignal type\nRemarks\nV REF+ Input, analog reference\npositive The higher/positive reference voltage for the ADC,\n2.4 V ≤ V REF+ ≤ V DDA\nV DDA(1) Input, analog supply Analog power supply equal to V DD and\n2.4 V ≤ V DDA ≤ 3.6 V\nV REF- Input, analog reference\nnegative The lower/negative reference voltage for the ADC,\nV REF- = V SSA\nV SSA(1) Input, analog supply\nground Ground for analog power supply equal to V SS\nADCx_IN[15:0] Analog signals Up to 21 analog channels (2)\n1. V DDA and V SSA have to be connected to V DD and V SS , respectively.\n2. For full details about the ADC I/O pins, please refer to the “Pinouts and pin descriptions” section of the\ncorresponding device datasheet.\nDoc ID 13902 Rev 14\n209/1096 Analog-to-digital converter (ADC)\n11.3.1\nRM0008\nADC on-off control\nThe ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the\nADON bit is set for the first time, it wakes up the ADC from Power Down mode.\nConversion starts when ADON bit is set for a second time by software after ADC power-up\ntime (t STAB ).\nYou can stop conversion and put the ADC in power down mode by resetting the ADON bit. In\nthis mode the ADC consumes almost no power (only a few µA).\n11.3.2\nADC clock\nThe ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2\nclock). The RCC controller has a dedicated programmable prescaler for the ADC clock (refer\nto Low-, medium-, high- and XL-density reset and clock control (RCC) on page 87for more\ndetails.\n11.3.3\nChannel selection\nThere are 16 multiplexed channels. It is possible to organize the conversions in two groups:\nregular and injected. A group consists of a sequence of conversions which can be done on\nany channel and in any order. For instance, it is possible to do the conversion in the\nfollowing order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15.\n● The regular group is composed of up to 16 conversions. The regular channels and\ntheir order in the conversion sequence must be selected in the ADC_SQRx registers.\nThe total number of conversions in the regular group must be written in the L[3:0] bits in\nthe ADC_SQR1 register.\n● The injected group is composed of up to 4 conversions. The injected channels and\ntheir order in the conversion sequence must be selected in the ADC_JSQR register.\nThe total number of conversions in the injected group must be written in the L[1:0] bits\nin the ADC_JSQR register.\nIf the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current\nconversion is reset and a new start pulse is sent to the ADC to convert the new chosen\ngroup.\nTemperature sensor/V REFINT internal channels\nThe Temperature sensor is connected to channel ADCx_IN16 and the internal reference\nvoltage V REFINT is connected to ADCx_IN17. These two internal channels can be selected\nand converted as injected or regular channels.\nNote: The sensor and V REFINT are only available on the master ADC1 peripheral.\n11.3.4 Single conversion mode\nIn Single conversion mode the ADC does one conversion. This mode is started either by\nsetting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external\ntrigger (for a regular or injected channel), while the CONT bit is 0.\n210/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nOnce the conversion of the selected channel is complete:\n●\n●\nIf a regular channel was converted:\n– The converted data is stored in the 16-bit ADC_DR register\n– The EOC (End Of Conversion) flag is set\n– and an interrupt is generated if the EOCIE is set.\nIf an injected channel was converted:\n–\nThe converted data is stored in the 16-bit ADC_DRJ1 register\n– The JEOC (End Of Conversion Injected) flag is set\n– and an interrupt is generated if the JEOCIE bit is set.\nThe ADC is then stopped.\n11.3.5\nContinuous conversion mode\nIn continuous conversion mode ADC starts another conversion as soon as it finishes one.\nThis mode is started either by external trigger or by setting the ADON bit in the ADC_CR2\nregister, while the CONT bit is 1.\nAfter each conversion:\n●\n●\n11.3.6\nIf a regular channel was converted:\n– The converted data is stored in the 16-bit ADC_DR register\n– The EOC (End Of Conversion) flag is set\n– An interrupt is generated if the EOCIE is set.\nIf an injected channel was converted:\n– The converted data is stored in the 16-bit ADC_DRJ1 register\n– The JEOC (End Of Conversion Injected) flag is set\n– An interrupt is generated if the JEOCIE bit is set.\nTiming diagram\nAs shown in Figure 23, the ADC needs a stabilization time of t STAB before it starts\nconverting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC\nflag is set and the 16-bit ADC Data register contains the result of the conversion.\nFigure 23. Timing diagram\nADC_CLK\nSET ADON\nStart 1st conversion\nADC power on\nADC Conversion\nADC\nt STAB\nStart next conversion\nNext ADC Conversion\nConversion Time\n(total conv time)\nEOC\nSoftware resets EOC bit\nDoc ID 13902 Rev 14\n211/1096 Analog-to-digital converter (ADC)\n11.3.7\nRM0008\nAnalog watchdog\nThe AWD analog watchdog status bit is set if the analog voltage converted by the ADC is\nbelow a low threshold or above a high threshold. These thresholds are programmed in the\n12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be\nenabled by using the AWDIE bit in the ADC_CR1 register.\nThe threshold value is independent of the alignment selected by the ALIGN bit in the\nADC_CR2 register. The comparison is done before the alignment (see Section 11.5).\nThe analog watchdog can be enabled on one or more channels by configuring the\nADC_CR1 register as shown in Table 66.\nFigure 24. Analog watchdog guarded area\nAnalog voltage\nHTR\nHigh threshold\nGuarded area\nLow threshold\nTable 66.\nLTR\nAnalog watchdog channel selection\nChannels to be guarded by analog\nwatchdog\nADC_CR1 register control bits (x = don’t care)\nAWDSGL bit AWDEN bit JAWDEN bit\nNone x 0 0\nAll injected channels 0 0 1\nAll regular channels 0 1 0\nAll regular and injected channels 0 1 1\n1 0 1\nSingle (1) regular channel 1 1 0\nSingle (1) 1 1 1\n(1)\nSingle\ninjected channel\nregular or injected channel\n1. Selected by AWDCH[4:0] bits\n11.3.8\nScan mode\nThis mode is used to scan a group of analog channels.\nScan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit\nis set, ADC scans all the channels selected in the ADC_SQRx registers (for regular\nchannels) or in the ADC_JSQR (for injected channels). A single conversion is performed for\neach channel of the group. After each end of conversion the next channel of the group is\nconverted automatically. If the CONT bit is set, conversion does not stop at the last selected\ngroup channel but continues again from the first selected group channel.\nWhen using scan mode, DMA bit must be set and the direct memory access controller is\nused to transfer the converted data of regular group channels to SRAM after each update of\nthe ADC_DR register.\nThe injected channel converted data is always stored in the ADC_JDRx registers.\n212/1096\nDoc ID 13902 Rev 14 RM0008\n11.3.9\nAnalog-to-digital converter (ADC)\nInjected channel management\nTriggered injection\nTo use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the\nADC_CR1 register.\nNote:\n1. Start conversion of a group of regular channels either by external trigger or by setting\nthe ADON bit in the ADC_CR2 register.\n2. If an external injected trigger occurs during the regular group channel conversion, the\ncurrent conversion is reset and the injected channel sequence is converted in Scan\nonce mode.\n3. Then, the regular group channel conversion is resumed from the last interrupted\nregular conversion. If a regular event occurs during an injected conversion, it doesn’t\ninterrupt it but the regular sequence is executed at the end of the injected sequence.\nFigure 25 shows the timing diagram.\nWhen using triggered injection, one must ensure that the interval between trigger events is\nlonger than the injection sequence. For instance, if the sequence length is 28 ADC clock\ncycles (that is two conversions with a 1.5 clock-period sampling time), the minimum interval\nbetween triggers must be 29 ADC clock cycles.\nAuto-injection\nIf the JAUTO bit is set, then the injected group channels are automatically converted after\nthe regular group channels. This can be used to convert a sequence of up to 20 conversions\nprogrammed in the ADC_SQRx and ADC_JSQR registers.\nIn this mode, external trigger on injected channels must be disabled.\nIf the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected\nchannels are continuously converted.\nFor ADC clock prescalers ranging from 4 to 8, a delay of 1 ADC clock period is automatically\ninserted when switching from regular to injected sequence (respectively injected to regular).\nWhen the ADC clock prescaler is set to 2, the delay is 2 ADC clock periods.\nNote:\nIt is not possible to use both auto-injected and discontinuous modes simultaneously.\nFigure 25. Injected conversion latency\nADC clock\nInj. event\nReset ADC\nSOC\nmax latency (1)\n1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and\nSTM32F103xx datasheets.\nDoc ID 13902 Rev 14\n213/1096 Analog-to-digital converter (ADC)\n11.3.10\nRM0008\nDiscontinuous mode\nRegular group\nThis mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to\nconvert a short sequence of n conversions (n <=8) which is a part of the sequence of\nconversions selected in the ADC_SQRx registers. The value of n is specified by writing to\nthe DISCNUM[2:0] bits in the ADC_CR1 register.\nWhen an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx\nregisters until all the conversions in the sequence are done. The total sequence length is\ndefined by the L[3:0] bits in the ADC_SQR1 register.\nExample:\nn = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10\n1st trigger: sequence converted 0, 1, 2\n2nd trigger: sequence converted 3, 6, 7\n3rd trigger: sequence converted 9, 10 and an EOC event generated\n4th trigger: sequence converted 0, 1, 2\nNote:\nWhen a regular group is converted in discontinuous mode, no rollover will occur. When all\nsub groups are converted, the next trigger starts conversion of the first sub-group.\nIn the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2.\nInjected group\nThis mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to\nconvert the sequence selected in the ADC_JSQR register, channel by channel, after an\nexternal trigger event.\nWhen an external trigger occurs, it starts the next channel conversions selected in the\nADC_JSQR registers until all the conversions in the sequence are done. The total sequence\nlength is defined by the JL[1:0] bits in the ADC_JSQR register.\nExample:\nn = 1, channels to be converted = 1, 2, 3\n1st trigger: channel 1 converted\n2nd trigger: channel 2 converted\n3rd trigger: channel 3 converted and EOC and JEOC events generated\n4th trigger: channel 1\nNote:\n1 When all injected channels are converted, the next trigger starts the conversion of the first\ninjected channel. In the example above, the 4th trigger reconverts the 1st injected channel\n1.\n2 It is not possible to use both auto-injected and discontinuous modes simultaneously.\n3 The user must avoid setting discontinuous mode for both regular and injected groups\ntogether. Discontinuous mode must be enabled only for one group conversion.\n11.4\nCalibration\nThe ADC has an built-in self calibration mode. Calibration significantly reduces accuracy\nerrors due to internal capacitor bank variations. During calibration, an error-correction code\n(digital word) is calculated for each capacitor, and during all subsequent conversions, the\nerror contribution of each capacitor is removed using this code.\n214/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nCalibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is\nover, the CAL bit is reset by hardware and normal conversion can be performed. It is\nrecommended to calibrate the ADC once at power-on. The calibration codes are stored in\nthe ADC_DR as soon as the calibration phase ends.\nNote:\n1 It is recommended to perform a calibration after each power-up.\n2 Before starting a calibration the ADC must have been in power-off state (ADON bit = ‘0’) for\nat least two ADC clock cycles.\nFigure 26. Calibration timing diagram\nCLK\nCalibration Reset by Hardware\nCalibration ongoing\nt CAL\nCAL\nNormal ADC Conversion\nADC\nConversion\n11.5\nData alignment\nALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.\nData can be left or right aligned as shown in Figure 27. and Figure 28.\nThe injected group channels converted data value is decreased by the user-defined offset\nwritten in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is\nthe extended sign value.\nFor regular group channels no offset is subtracted so only twelve bits are significant.\nFigure 27. Right alignment of data\nInjected group\nSEXT SEXT SEXT SEXT\nD11 D10 D9 D8\nD11 D10 D9 D8\nD7\nD6\nD5 D4 D3 D2 D1 D0\nD5 D4 D3 D2 D1 D0\nRegular group\n0\n0\n0\n0\nD7\nD6\nFigure 28. Left alignment of data\nInjected group\nSEXT\nD11\nD10\nD9\nD8\nD7 D6 D5 D4 D3 D2 D1 D0 0 0 0\nD6 D5 D4 D3 D2 D1 D0 0 0 0 0\nRegular group\nD11\nD10\nD9\nD8\nD7\nDoc ID 13902 Rev 14\n215/1096 Analog-to-digital converter (ADC)\n11.6\nRM0008\nChannel-by-channel programmable sample time\nADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-\ning the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be\nsampled with a different sample time.\nThe total conversion time is calculated as follows:\nTconv = Sampling time + 12.5 cycles\nExample:\nWith an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:\nTconv = 1.5 + 12.5 = 14 cycles = 1 µs\n11.7\nConversion on external trigger\nConversion can be triggered by an external event (e.g. timer capture, EXTI line). If the EXT-\nTRIG control bit is set then external events are able to trigger a conversion. The EXT-\nSEL[2:0] and JEXTSEL[2:0] control bits allow the application to select decide which out of 8\npossible events can trigger conversion for the regular and injected groups.\nNote:\nWhen an external trigger is selected for ADC regular or injected conversion, only the rising\nedge of the signal can start the conversion.\nTable 67.\nExternal trigger for regular channels for ADC1 and ADC2\nSource\nType\nEXTSEL[2:0]\nTIM1_CC1 event 000\nTIM1_CC2 event 001\nTIM1_CC3 event\nTIM2_CC2 event\nInternal signal from on-chip\ntimers\n010\n011\nTIM3_TRGO event 100\nTIM4_CC4 event 101\nEXTI line 11/TIM8_TRGO\nevent (1)(2) External pin/Internal signal from\n110\non-chip timers\nSWSTART Software control bit\n111\n1. The TIM8_TRGO event exists only in high-density and XL-density devices.\n2. The selection of the external trigger EXTI line11 or TIM8_TRGO event for regular channels is done through\nconfiguration bits ADC1_ETRGREG_REMAP and ADC2_ETRGREG_REMAP for ADC1 and ADC2,\nrespectively.\n216/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nTable 68.\nExternal trigger for injected channels for ADC1 and ADC2\nSource\nConnection type\nJEXTSEL[2:0]\nTIM1_TRGO event 000\nTIM1_CC4 event 001\nTIM2_TRGO event\nTIM2_CC1 event\nInternal signal from on-chip\ntimers\n010\n011\nTIM3_CC4 event 100\nTIM4_TRGO event 101\nEXTI line 15/TIM8_CC4\nevent (1)(2) External pin/Internal signal from\n110\non-chip timers\nJSWSTART Software control bit\n111\n1. The TIM8_CC4 event exists only in high-density and XL-density devices.\n2. The selection of the external trigger EXTI line15 or TIM8_CC4 event for injected channels is done through\nconfiguration bits ADC1_ETRGINJ_REMAP and ADC2_ETRGINJ_REMAP for ADC1 and ADC2,\nrespectively.\nTable 69.\nExternal trigger for regular channels for ADC3\nSource\nConnection type\nEXTSEL[2:0]\nTIM3_CC1 event 000\nTIM2_CC3 event 001\nTIM1_CC3 event\nTIM8_CC1 event\n010\nInternal signal from on-chip\ntimers\n011\nTIM8_TRGO event 100\nTIM5_CC1 event 101\nTIM5_CC3 event 110\nSWSTART\nTable 70.\nSoftware control bit\n111\nExternal trigger for injected channels for ADC3\nSource\nConnection type\nJEXTSEL[2:0]\nTIM1_TRGO event 000\nTIM1_CC4 event 001\nTIM4_CC3 event\nTIM8_CC2 event\n010\nInternal signal from on-chip\ntimers\n011\nTIM8_CC4 event 100\nTIM5_TRGO event 101\nTIM5_CC4 event 110\nJSWSTART\nSoftware control bit\nDoc ID 13902 Rev 14\n111\n217/1096 Analog-to-digital converter (ADC)\nRM0008\nThe software source trigger events can be generated by setting a bit in a register\n(SWSTART and JSWSTART in ADC_CR2).\nA regular group conversion can be interrupted by an injected trigger.\n11.8\nDMA request\nSince converted regular channels value are stored in a unique data register, it is necessary\nto use DMA for conversion of more than one regular channel. This avoids the loss of data\nalready stored in the ADC_DR register.\nOnly the end of conversion of a regular channel generates a DMA request, which allows the\ntransfer of its converted data from the ADC_DR register to the destination location selected\nby the user.\nNote:\n218/1096\nOnly ADC1 and ADC3 have this DMA capability. ADC2-converted data can be transferred in\ndual ADC mode using DMA thanks to master ADC1.\nDoc ID 13902 Rev 14 RM0008\n11.9\nAnalog-to-digital converter (ADC)\nDual ADC mode\nIn devices with two ADCs or more, dual ADC mode can be used (see Figure 29).\nIn dual ADC mode the start of conversion is triggered alternately or simultaneously by the\nADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0]\nbits in the ADC1_CR1 register.\nNote:\nIn dual mode, when configuring conversion to be triggered by an external event, the user\nmust set the trigger for the master only and set a software trigger for the slave to prevent\nspurious triggers to start unwanted slave conversion. However, external triggers must be\nenabled on both master and slave ADCs.\nThe following six possible modes are implemented:\n– Injected simultaneous mode\n– Regular simultaneous mode\n– Fast interleaved mode\n– Slow interleaved mode\n– Alternate trigger mode\n– Independent mode\nIt is also possible to use the previous modes combined in the following ways:\nNote:\n– Injected simultaneous mode + Regular simultaneous mode\n– Regular simultaneous mode + Alternate trigger mode\n– Injected simultaneous mode + Interleaved mode\nIn dual ADC mode, to read the slave converted data on the master data register, the DMA\nbit must be enabled even if it is not used to transfer converted regular channel data.\nDoc ID 13902 Rev 14\n219/1096 Analog-to-digital converter (ADC)\nRM0008\nFigure 29. Dual ADC block diagram (1)\nRegular data register\n(12\n(16 bits)\nbits)\nInjected data registers\n(4 x 16 bits)\nRegular\nchannels\nADC2 (Slave)\ninternal triggers\nRegular data register\n(16 bits) (2)\nInjected data registers\n(4 x 16 bits)\ninjected\nchannels\nADCx_IN0\nADCx_IN1\nRegular\nchannels\nGPIO\nPorts\nInjected\nchannels\nADCx_IN15\nTemp. sensor\nV REFINT\nDual mode\ncontrol\nEXTI_11\nADC1 (Master)\nStart trigger mux\n(regular group)\nEXTI_15\nStart trigger mux\n(injected group)\n220/1096\n1. External triggers are present on ADC2 but are not shown for the purposes of this diagram.\n2. In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over\nthe entire 32 bits.\nDoc ID 13902 Rev 14 RM0008\n11.9.1\nAnalog-to-digital converter (ADC)\nInjected simultaneous mode\nThis mode converts an injected channel group. The source of external trigger comes from\nthe injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2\nregister). A simultaneous trigger is provided to ADC2.\nNote:\nDo not convert the same channel on the two ADCs (no overlapping sampling times for the\ntwo ADCs when converting the same channel).\nAt the end of conversion event on ADC1 or ADC2:\nNote:\n● The converted data is stored in the ADC_JDRx registers of each ADC interface.\n● An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the\nADC1/ADC2 injected channels are all converted.\nIn simultaneous mode, one must convert sequences with the same length or ensure that the\ninterval between triggers is longer than the longest of the 2 sequences. Otherwise, the ADC\nwith the shortest sequence may restart while the ADC with the longest sequence is\ncompleting the previous conversions.\nFigure 30. Injected simultaneous mode on 4 channels\nSampling\nConversion\nADC2\nADC1\nCH0 CH1 CH2 CH3\nCH3 CH2 CH1 CH0\nTrigger\n11.9.2\nEnd of injected conversion on ADC1 and ADC2\nRegular simultaneous mode\nThis mode is performed on a regular channel group. The source of the external trigger\ncomes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the\nADC1_CR2 register). A simultaneous trigger is provided to the ADC2.\nNote:\nDo not convert the same channel on the two ADCs (no overlapping sampling times for the\ntwo ADCs when converting the same channel).\nAt the end of conversion event on ADC1 or ADC2:\nNote:\n● A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM\nthe ADC1_DR 32-bit register containing the ADC2 converted data in the upper\nhalfword and the ADC1 converted data in the lower halfword.\n● An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when\nADC1/ADC2 regular channels are all converted.\nIn regular simultaneous mode, one must convert sequences with the same length or ensure\nthat the interval between triggers is longer than the longest of the 2 sequences. Otherwise,\nthe ADC with the shortest sequence may restart while the ADC with the longest sequence is\ncompleting the previous conversions.\nDoc ID 13902 Rev 14\n221/1096 Analog-to-digital converter (ADC)\nRM0008\nFigure 31. Regular simultaneous mode on 16 channels\nSampling\nConversion\nADC1\nADC2\nCH0 CH1 CH2 CH3\nCH15 CH14 CH13 CH12\n...\n...\nCH15\nCH0\nEnd of conversion on ADC1 and ADC2\nTrigger\n11.9.3\nFast interleaved mode\nThis mode can be started only on a regular channel group (usually one channel). The\nsource of external trigger comes from the regular channel mux of ADC1. After an external\ntrigger occurs:\n● ADC2 starts immediately and\n● ADC1 starts after a delay of 7 ADC clock cycles.\nIf CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are\ncontinuously converted.\nAfter an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit\nDMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the\nADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the\nADC1 converted data in the lower halfword.\nNote:\nThe maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between\nADC1 and ADC2 sampling phases in the event that they convert the same channel.\nFigure 32. Fast interleaved mode on 1 channel in continuous conversion mode\nEnd of conversion on ADC2\nADC2\nADC1\n...\nCH0\nCH0\nTrigger\n...\nSampling\nConversion\nCH0\nCH0\nEnd of conversion on ADC1\n7 ADCCLK\ncycles\n11.9.4\nSlow interleaved mode\nThis mode can be started only on a regular channel group (only one channel). The source of\nexternal trigger comes from regular channel mux of ADC1. After external trigger occurs:\nNote:\n222/1096\n● ADC2 starts immediately and\n● ADC1 starts after a delay of 14 ADC clock cycles.\n● ADC2 starts after a second delay of 14 ADC cycles, and so on.\nThe maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the\nnext conversion.\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nAfter an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit\nDMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the\nADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the\nADC1 converted data in the lower halfword.\nA new ADC2 start is automatically generated after 28 ADC clock cycles\nCONT bit can not be set in the mode since it continuously converts the selected regular\nchannel.\nNote:\nThe application must ensure that no external trigger for injected channel occurs when\ninterleaved mode is enabled.\nFigure 33. Slow interleaved mode on 1 channel\nEnd of conversion on ADC2\nSampling\nConversion\nADC2\nADC1\nCH0\nCH0\nCH0\nTrigger\nCH0\nEnd of conversion on ADC1\n14 ADCCLK\ncycles\n28 ADCCLK\ncycles\n11.9.5\nAlternate trigger mode\nThis mode can be started only on an injected channel group. The source of external trigger\ncomes from the injected group mux of ADC1.\n● When the 1st trigger occurs, all injected group channels in ADC1 are converted.\n● When the 2nd trigger arrives, all injected group channels in ADC2 are converted\n● and so on.\nA JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are\nconverted.\nA JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are\nconverted.\nIf another external trigger occurs after all injected group channels have been converted then\nthe alternate trigger process restarts by converting ADC1 injected group channels.\nFigure 34. Alternate trigger: injected channel group of each ADC\n1st trigger\nEOC, JEOC\non ADC1\n3rd trigger\n(n)th trigger\nEOC, JEOC\non ADC1\nADC1\nSampling\nConversion\n. . .\nADC2\nEOC, JEOC\non ADC2\n2nd trigger\nEOC, JEOC\non ADC2\n4th trigger\nDoc ID 13902 Rev 14\n(n+1)th trigger\n223/1096 Analog-to-digital converter (ADC)\nRM0008\nIf the injected discontinuous mode is enabled for both ADC1 and ADC2:\n● When the 1st trigger occurs, the first injected channel in ADC1 is converted.\n● When the 2nd trigger arrives, the first injected channel in ADC2 are converted\n● and so on....\nA JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are\nconverted.\nA JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are\nconverted.\nIf another external trigger occurs after all injected group channels have been converted then\nthe alternate trigger process restarts.\nFigure 35. Alternate trigger: 4 injected channels (each ADC) in discontinuous model\n1st trigger\n3rd trigger\n5th trigger\n7th trigger\nSampling\nJEOC on ADC1\nConversion\nADC1\nADC2\nJEOC on ADC2\n2nd trigger\n11.9.6\n4th trigger\n6th trigger\n8th trigger\nIndependent mode\nIn this mode the dual ADC synchronization is bypassed and each ADC interfaces works\nindependently.\n11.9.7\nCombined regular/injected simultaneous mode\nIt is possible to interrupt simultaneous conversion of a regular group to start simultaneous\nconversion of an injected group.\nNote: In combined regular/injected simultaneous mode, one must convert sequences with the\nsame length or ensure that the interval between triggers is longer than the longest of the 2\nsequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with\nthe longest sequence is completing the previous conversions.\n11.9.8 Combined regular simultaneous + alternate trigger mode\nIt is possible to interrupt regular group simultaneous conversion to start alternate trigger\nconversion of an injected group. Figure 36 shows the behavior of an alternate trigger\ninterrupting a regular simultaneous conversion.\nThe injected alternate conversion is immediately started after the injected event arrives. If\nregular conversion is already running, in order to ensure synchronization after the injected\nconversion, the regular conversion of both (master/slave) ADCs is stopped and resumed\nsynchronously at the end of the injected conversion.\nNote:\n224/1096\nIn combined regular simultaneous + alternate trigger mode, one must convert sequences\nwith the same length or ensure that the interval between triggers is longer than the longest\nof the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while the\nADC with the longest sequence is completing the previous conversions.\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nFigure 36. Alternate + Regular simultaneous\n1st trig\nADC1 reg\nCH0\nCH1\nCH2\nCH3 CH3 CH4\nCH6 CH7 CH7 CH8\nCH0\nADC1 inj\nADC2 reg\nCH2\nCH3\nCH5\nCH6\nCH0\nADC2 inj\nsynchro not lost\n2nd trig\nIf a trigger occurs during an injected conversion that has interrupted a regular conversion, it\nwill be ignored. Figure 37 shows the behavior in this case (2nd trig is ignored).\nFigure 37. Case of trigger occurring during injected conversion\n1st trig\nADC1 reg\nCH0\nCH1\nCH2\nCH2 CH3\nCH6 CH7\nCH3 CH4\nCH0\nCH7 CH8\nCH0\nADC1 inj\nADC2 reg\n3rd trig\nCH3\nCH5\nCH6\nCH0\nADC2 inj\n4th trig\n2nd trig\n11.9.9\nCombined injected simultaneous + interleaved\nIt is possible to interrupt an interleaved conversion with an injected event. In this case the\ninterleaved conversion is interrupted and the injected conversion starts, at the end of the\ninjected sequence the interleaved conversion is resumed. Figure 38 shows the behavior\nusing an example.\nNote:\nWhen the ADC clock prescaler is set to 4, the interleaved mode does not recover with\nevenly spaced sampling periods: the sampling interval is 8 ADC clock periods followed by 6\nADC clock periods, instead of 7 clock periods followed by 7 clock periods.\nFigure 38. Interleaved single channel with injected sequence CH11, CH12\nSampling\nCH0\nADC1\nADC2\nCH0\nCH0\nCH0\nTrigger\nCH0\nConversion\nCH0\nCH11 CH12\nCH12 CH11\nCH0\nCH0\nDoc ID 13902 Rev 14\nCH0\nCH0\n225/1096 Analog-to-digital converter (ADC)\n11.10\nRM0008\nTemperature sensor\nThe temperature sensor can be used to measure the ambient temperature (T A ) of the\ndevice.\nThe temperature sensor is internally connected to the ADCx_IN16 input channel which is\nused to convert the sensor output voltage into a digital value. The recommended sampling\ntime for the temperature sensor is 17.1 µs.\nThe block diagram of the temperature sensor is shown in Figure 39.\nWhen not in use, this sensor can be put in power down mode.\nNote:\nThe TSVREFE bit must be set to enable both internal channels: ADCx_IN16 (temperature\nsensor) and ADCx_IN17 (V REFINT ) conversion.\nThe temperature sensor output voltage changes linearly with temperature. The offset of this\nline varies from chip to chip due to process variation (up to 45 °C from one chip to another).\nThe internal temperature sensor is more suited to applications that detect temperature\nvariations instead of absolute temperatures. If accurate temperature readings are needed,\nan external temperature sensor part should be used.\nFigure 39. Temperature sensor and V REFINT channel block diagram\nTSVREFE control bit\nV SENSE\nADCx_IN16\nSENSOR\nconverted data\nADC1\nINTERNAL\nPOWER\nBLOCK\n226/1096\nV REFINT\nADCx_IN17\nDoc ID 13902 Rev 14\nAddress/data\nTEMPERATURE RM0008\nAnalog-to-digital converter (ADC)\nReading the temperature\nTo use the sensor:\n1. Select the ADCx_IN16 input channel.\n2. Select a sample time of 17.1 µs\n3. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the\ntemperature sensor from power down mode.\n4. Start the ADC conversion by setting the ADON bit (or by external trigger).\n5. Read the resulting V SENSE data in the ADC data register\n6. Obtain the temperature using the following formula:\nTemperature (in °C) = {(V 25 - V SENSE ) / Avg_Slope} + 25.\nWhere,\nV 25 = V SENSE value for 25° C and\nAvg_Slope = Average Slope for curve between Temperature vs. V SENSE (given in\nmV/° C or µV/ °C).\nRefer to the Electrical characteristics section for the actual values of V 25 and\nAvg_Slope.\nNote: The sensor has a startup time after waking from power down mode before it can output\nV SENSE at the correct level. The ADC also has a startup time after power-on, so to minimize\nthe delay, the ADON and TSVREFE bits should be set at the same time.\n11.11 ADC interrupts\nAn interrupt can be produced on end of conversion for regular and injected groups and\nwhen the analog watchdog status bit is set. Separate interrupt enable bits are available for\nflexibility.\nNote:\nADC1 and ADC2 interrupts are mapped onto the same interrupt vector. ADC3 interrupts are\nmapped onto a separate interrupt vector.\nTwo other flags are present in the ADC_SR register, but there is no interrupt associated with\nthem:\n● JSTRT (Start of conversion for injected group channels)\n● STRT (Start of conversion for regular group channels)\nTable 71.\nADC interrupts\nInterrupt event\nEvent flag Enable Control bit\nEnd of conversion regular group EOC EOCIE\nEnd of conversion injected group JEOC JEOCIE\nAnalog watchdog status bit is set AWD AWDIE\nDoc ID 13902 Rev 14\n227/1096 Analog-to-digital converter (ADC)\n11.12\nRM0008\nADC registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers have to be accessed by words (32-bit).\n11.12.1\nADC status register (ADC_SR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nSTRT JSTRT JEOC EOC AWD\nrc_w0 rc_w0 rc_w0 rc_w0 rc_w0\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nReserved\nBits 31:5\nReserved, must be kept at reset value.\nBit 4 STRT: Regular channel Start flag\nThis bit is set by hardware when regular channel conversion starts. It is cleared by software.\n0: No regular channel conversion started\n1: Regular channel conversion has started\nBit 3 JSTRT: Injected channel Start flag\nThis bit is set by hardware when injected channel group conversion starts. It is cleared by\nsoftware.\n0: No injected group conversion started\n1: Injected group conversion has started\nBit 2 JEOC: Injected channel end of conversion\nThis bit is set by hardware at the end of all injected group channel conversion. It is cleared by\nsoftware.\n0: Conversion is not complete\n1: Conversion complete\nBit 1 EOC: End of conversion\nThis bit is set by hardware at the end of a group channel conversion (regular or injected). It is\ncleared by software or by reading the ADC_DR.\n0: Conversion is not complete\n1: Conversion complete\nBit 0 AWD: Analog watchdog flag\nThis bit is set by hardware when the converted voltage crosses the values programmed in\nthe ADC_LTR and ADC_HTR registers. It is cleared by software.\n0: No Analog watchdog event occurred\n1: Analog watchdog event occurred\n228/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.2\nADC control register 1 (ADC_CR1)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\n19\nAWDEN JAWDEN\nReserved\n15\n14\n13\nDISCNUM[2:0]\nrw\nrw\nrw\n18\n17\n16\nDUALMOD[3:0]\nReserved\n12 11 10 9\nJDISCE\nN DISC\nEN JAUTO AWD\nSGL\nrw rw rw rw\nrw rw\n7 6\n8\nSCAN JEOC IE AWDIE\nrw\nrw\nrw\n5\n4\nrw rw rw rw\n3 2 1 0\nrw rw\nEOCIE\nrw\nAWDCH[4:0]\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBit 23 AWDEN: Analog watchdog enable on regular channels\nThis bit is set/reset by software.\n0: Analog watchdog disabled on regular channels\n1: Analog watchdog enabled on regular channels\nBit 22 JAWDEN: Analog watchdog enable on injected channels\nThis bit is set/reset by software.\n0: Analog watchdog disabled on injected channels\n1: Analog watchdog enabled on injected channels\nBits 21:20\nReserved, must be kept at reset value.\nBits 19:16 DUALMOD[3:0]: Dual mode selection\nThese bits are written by software to select the operating mode.\n0000: Independent mode.\n0001: Combined regular simultaneous + injected simultaneous mode\n0010: Combined regular simultaneous + alternate trigger mode\n0011: Combined injected simultaneous + fast interleaved mode\n0100: Combined injected simultaneous + slow Interleaved mode\n0101: Injected simultaneous mode only\n0110: Regular simultaneous mode only\n0111: Fast interleaved mode only\n1000: Slow interleaved mode only\n1001: Alternate trigger mode only\nNote: These bits are reserved in ADC2 and ADC3.\nIn dual mode, a change of channel configuration generates a restart that can produce a\nloss of synchronization. It is recommended to disable dual mode before any\nconfiguration change.\nBits 15:13 DISCNUM[2:0]: Discontinuous mode channel count\nThese bits are written by software to define the number of regular channels to be converted\nin discontinuous mode, after receiving an external trigger.\n000: 1 channel\n001: 2 channels\n.......\n111: 8 channels\nDoc ID 13902 Rev 14\n229/1096 Analog-to-digital converter (ADC)\nRM0008\nBit 12 JDISCEN: Discontinuous mode on injected channels\nThis bit set and cleared by software to enable/disable discontinuous mode on injected group\nchannels\n0: Discontinuous mode on injected channels disabled\n1: Discontinuous mode on injected channels enabled\nBit 11 DISCEN: Discontinuous mode on regular channels\nThis bit set and cleared by software to enable/disable Discontinuous mode on regular\nchannels.\n0: Discontinuous mode on regular channels disabled\n1: Discontinuous mode on regular channels enabled\nBit 10 JAUTO: Automatic Injected Group conversion\nThis bit set and cleared by software to enable/disable automatic injected group conversion\nafter regular group conversion.\n0: Automatic injected group conversion disabled\n1: Automatic injected group conversion enabled\nBit 9 AWDSGL: Enable the watchdog on a single channel in scan mode\nThis bit set and cleared by software to enable/disable the analog watchdog on the channel\nidentified by the AWDCH[4:0] bits.\n0: Analog watchdog enabled on all channels\n1: Analog watchdog enabled on a single channel\nBit 8 SCAN: Scan mode\nThis bit is set and cleared by software to enable/disable Scan mode. In Scan mode, the\ninputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.\n0: Scan mode disabled\n1: Scan mode enabled\nNote: An EOC or JEOC interrupt is generated only on the end of conversion of the last\nchannel if the corresponding EOCIE or JEOCIE bit is set\nBit 7 JEOCIE: Interrupt enable for injected channels\nThis bit is set and cleared by software to enable/disable the end of conversion interrupt for\ninjected channels.\n0: JEOC interrupt disabled\n1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.\nBit 6 AWDIE: Analog watchdog interrupt enable\nThis bit is set and cleared by software to enable/disable the analog watchdog interrupt.\n0: Analog watchdog interrupt disabled\n1: Analog watchdog interrupt enabled\nBit 5 EOCIE: Interrupt enable for EOC\nThis bit is set and cleared by software to enable/disable the End of Conversion interrupt.\n0: EOC interrupt disabled\n1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.\n230/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nBits 4:0 AWDCH[4:0]: Analog watchdog channel select bits\nThese bits are set and cleared by software. They select the input channel to be guarded by\nthe Analog watchdog.\n00000: ADC analog Channel0\n00001: ADC analog Channel1\n....\n01111: ADC analog Channel15\n10000: ADC analog Channel16\n10001: ADC analog Channel17\nOther values reserved.\nNote: ADC1 analog Channel16 and Channel17 are internally connected to the temperature\nsensor and to V REFINT , respectively.\nADC2 analog inputs Channel16 and Channel17 are internally connected to V SS .\nADC3 analog inputs Channel9, Channel14, Channel15, Channel16 and Channel17 are\nconnected to V SS .\n11.12.3\nADC control register 2 (ADC_CR2)\nAddress offset: 0x08\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\nReserved\n15\n14\nJEXTT\nRIG\nrw\n13\n12\nJEXTSEL[2:0]\n11\nALIGN\n23\n22\n21\n10\n9\nReserved\n8\nrw\nBits 31:24\nrw\nrw\n19\nRes.\n18\n17\n16\nEXTSEL[2:0]\nRes.\nrw rw rw rw rw rw rw 7 6 5 4 3 2 1 0\nRST\nCAL CAL CONT ADON\nrw rw rw rw\nDMA\nReserved\nrw\n20\nTSVRE SWSTA JSWST EXTTR\nFE\nRT\nART\nIG\nrw\nReserved, must be kept at reset value.\nBit 23 TSVREFE: Temperature sensor and V REFINT enable\nThis bit is set and cleared by software to enable/disable the temperature sensor and V REFINT\nchannel. In devices with dual ADCs this bit is present only in ADC1.\n0: Temperature sensor and V REFINT channel disabled\n1: Temperature sensor and V REFINT channel enabled\nBit 22 SWSTART: Start conversion of regular channels\nThis bit is set by software to start conversion and cleared by hardware as soon as conversion\nstarts. It starts a conversion of a group of regular channels if SWSTART is selected as trigger\nevent by the EXTSEL[2:0] bits.\n0: Reset state\n1: Starts conversion of regular channels\nBit 21 JSWSTART: Start conversion of injected channels\nThis bit is set by software and cleared by software or by hardware as soon as the conversion\nstarts. It starts a conversion of a group of injected channels (if JSWSTART is selected as\ntrigger event by the JEXTSEL[2:0] bits.\n0: Reset state\n1: Starts conversion of injected channels\nDoc ID 13902 Rev 14\n231/1096 Analog-to-digital converter (ADC)\nRM0008\nBit 20 EXTTRIG: External trigger conversion mode for regular channels\nThis bit is set and cleared by software to enable/disable the external trigger used to start\nconversion of a regular channel group.\n0: Conversion on external event disabled\n1: Conversion on external event enabled\nBits 19:17 EXTSEL[2:0]: External event select for regular group\nThese bits select the external event used to trigger the start of conversion of a regular group:\nFor ADC1 and ADC2, the assigned triggers are:\n000: Timer 1 CC1 event\n001: Timer 1 CC2 event\n010: Timer 1 CC3 event\n011: Timer 2 CC2 event\n100: Timer 3 TRGO event\n101: Timer 4 CC4 event\n110: EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-\ndensity devices)\n111: SWSTART\nFor ADC3, the assigned triggers are:\n000: Timer 3 CC1 event\n001: Timer 2 CC3 event\n010: Timer 1 CC3 event\n011: Timer 8 CC1 event\n100: Timer 8 TRGO event\n101: Timer 5 CC1 event\n110: Timer 5 CC3 event\n111: SWSTART\nBit 16\nReserved, must be kept at reset value.\nBit 15 JEXTTRIG: External trigger conversion mode for injected channels\nThis bit is set and cleared by software to enable/disable the external trigger used to start\nconversion of an injected channel group.\n0: Conversion on external event disabled\n1: Conversion on external event enabled\n232/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\nBits 14:12 JEXTSEL[2:0]: External event select for injected group\nThese bits select the external event used to trigger the start of conversion of an injected\ngroup:\nFor ADC1 and ADC2 the assigned triggers are:\n000: Timer 1 TRGO event\n001: Timer 1 CC4 event\n010: Timer 2 TRGO event\n011: Timer 2 CC1 event\n100: Timer 3 CC4 event\n101: Timer 4 TRGO event\n110: EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-\ndensity devices)\n111: JSWSTART\nFor ADC3 the assigned triggers are:\n000: Timer 1 TRGO event\n001: Timer 1 CC4 event\n010: Timer 4 CC3 event\n011: Timer 8 CC2 event\n100: Timer 8 CC4 event\n101: Timer 5 TRGO event\n110: Timer 5 CC4 event\n111: JSWSTART\nBit 11 ALIGN: Data alignment\nThis bit is set and cleared by software. Refer to Figure 27.and Figure 28.\n0: Right Alignment\n1: Left Alignment\nBits 10:9\nReserved, must be kept at reset value.\nBit 8 DMA: Direct memory access mode\nThis bit is set and cleared by software. Refer to the DMA controller chapter for more details.\n0: DMA mode disabled\n1: DMA mode enabled\nOnly ADC1 and ADC3 can generate a DMA request.\nBits 7:4\nReserved, must be kept at reset value.\nBit 3 RSTCAL: Reset calibration\nThis bit is set by software and cleared by hardware. It is cleared after the calibration registers\nare initialized.\n0: Calibration register initialized.\n1: Initialize calibration register.\nNote: If RSTCAL is set when conversion is ongoing, additional cycles are required to clear the\ncalibration registers.\nBit 2 CAL: A/D Calibration\nThis bit is set by software to start the calibration. It is reset by hardware after calibration is\ncomplete.\n0: Calibration completed\n1: Enable calibration\nDoc ID 13902 Rev 14\n233/1096 Analog-to-digital converter (ADC)\nRM0008\nBit 1 CONT: Continuous conversion\nThis bit is set and cleared by software. If set conversion takes place continuously till this bit is\nreset.\n0: Single conversion mode\n1: Continuous conversion mode\nBit 0 ADON: A/D converter ON / OFF\nThis bit is set and cleared by software. If this bit holds a value of zero and a 1 is written to it\nthen it wakes up the ADC from Power Down state.\nConversion starts when this bit holds a value of 1 and a 1 is written to it. The application\nshould allow a delay of t STAB between power up and start of conversion. Refer to Figure 23.\n0: Disable ADC conversion/calibration and go to power down mode.\n1: Enable ADC and to start conversion\nNote: If any other bit in this register apart from ADON is changed at the same time, then\nconversion is not triggered. This is to prevent triggering an erroneous conversion.\n234/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.4\nADC sample time register 1 (ADC_SMPR1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20\nSMP17[2:0]\n19\n18\nSMP16[2:0]\n17\n16\nSMP15[2:1]\nReserved\n15\n14\nSMP\n15_0\nrw\n13\n12\n11\nSMP14[2:0]\nrw\nrw\n10\n9\n8\nSMP13[2:0]\nrw\nrw\nrw\nrw rw rw rw rw rw rw rw\n7 6 5 4 3 2 1 0\nSMP12[2:0]\nrw\nrw\nrw\nSMP11[2:0]\nrw\nrw\nrw\nSMP10[2:0]\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBits 23:0 SMPx[2:0]: Channel x Sample time selection\nThese bits are written by software to select the sample time individually for each channel.\nDuring sample cycles channel selection bits must remain unchanged.\n000: 1.5 cycles\n001: 7.5 cycles\n010: 13.5 cycles\n011: 28.5 cycles\n100: 41.5 cycles\n101: 55.5 cycles\n110: 71.5 cycles\n111: 239.5 cycles\nNote: ADC1 analog Channel16 and Channel 17 are internally connected to the temperature\nsensor and to V REFINT , respectively.\nADC2 analog input Channel16 and Channel17 are internally connected to V SS .\nADC3 analog inputs Channel14, Channel15, Channel16 and Channel17 are connected\nto V SS .\nDoc ID 13902 Rev 14\n235/1096 Analog-to-digital converter (ADC)\n11.12.5\nRM0008\nADC sample time register 2 (ADC_SMPR2)\nAddress offset: 0x10\nReset value: 0x0000 0000\n31\n30\n29\nReserved\n14\nSMP\n5_0\nrw\n27 26\nSMP9[2:0]\nRes.\n15\n28\n24 23\nSMP8[2:0]\n22\n21 20\nSMP7[2:0]\n19\n18 17\nSMP6[2:0]\n16\nSMP5[2:1]\nrw rw rw rw rw rw rw rw rw rw rw rw rw rw\n13 12 11 10 9 8 7 6 5 4 3 2 1 0\nSMP4[2:0]\nrw\n25\nrw\nSMP3[2:0]\nrw\nrw\nrw\nSMP2[2:0]\nrw\nrw\nrw\nSMP1[2:0]\nrw\nrw\nrw\nSMP0[2:0]\nrw\nrw\nrw\nrw\nBits 31:30 Reserved, must be kept at reset value.\nBits 29:0 SMPx[2:0]: Channel x Sample time selection\nThese bits are written by software to select the sample time individually for each channel.\nDuring sample cycles channel selection bits must remain unchanged.\n000: 1.5 cycles\n001: 7.5 cycles\n010: 13.5 cycles\n011: 28.5 cycles\n100: 41.5 cycles\n101: 55.5 cycles\n110: 71.5 cycles\n111: 239.5 cycles\nNote: ADC3 analog input Channel9 is connected to V SS .\n11.12.6\nADC injected channel data offset register x (ADC_JOFRx)(x=1..4)\nAddress offset: 0x14-0x20\nReset value: 0x0000 0000\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw rw rw\nReserved\n7\nJOFFSETx[11:0]\nReserved\nrw\nBits 31:12\nrw\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBits 11:0 JOFFSETx[11:0]: Data offset for injected channel x\nThese bits are written by software to define the offset to be subtracted from the raw\nconverted data when converting injected channels. The conversion result can be read from\nin the ADC_JDRx registers.\n236/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.7\nADC watchdog high threshold register (ADC_HTR)\nAddress offset: 0x24\nReset value: 0x0000 0FFF\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw rw rw\nReserved\n7\nHT[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 HT[11:0]: Analog watchdog high threshold\nThese bits are written by software to define the high threshold for the analog watchdog.\n11.12.8\nADC watchdog low threshold register (ADC_LTR)\nAddress offset: 0x28\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nLT[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits 11:0 LT[11:0]: Analog watchdog low threshold\nThese bits are written by software to define the low threshold for the analog watchdog.\nDoc ID 13902 Rev 14\n237/1096 Analog-to-digital converter (ADC)\n11.12.9\nRM0008\nADC regular sequence register 1 (ADC_SQR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23 22\n21 20 19 18 rw rw rw rw rw rw rw rw\n7 6 5 4 3 2 1 0\nrw rw\nL[3:0]\n17\n16\nSQ16[4:1]\nReserved\n15\n14\n13\nSQ16_0\nrw\n12\n11\n10\n9\n8\nSQ15[4:0]\nrw\nrw\nrw\nSQ14[4:0]\nrw\nrw\nrw\nrw\nrw\nSQ13[4:0]\nrw\nrw\nrw\nrw\nrw\nBits 31:24 Reserved, must be kept at reset value.\nBits 23:20 L[3:0]: Regular channel sequence length\nThese bits are written by software to define the total number of conversions in the regular\nchannel conversion sequence.\n0000: 1 conversion\n0001: 2 conversions\n.....\n1111: 16 conversions\nBits 19:15 SQ16[4:0]: 16th conversion in regular sequence\nThese bits are written by software with the channel number (0..17) assigned as the 16th in\nthe conversion sequence.\nBits 14:10 SQ15[4:0]: 15th conversion in regular sequence\nBits 9:5 SQ14[4:0]: 14th conversion in regular sequence\nBits 4:0 SQ13[4:0]: 13th conversion in regular sequence\n238/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.10 ADC regular sequence register 2 (ADC_SQR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n31\n30\n29 28\nrw rw\n13 12\n27\n26 25 24 23\nrw rw rw rw rw\n11 10 9 8 7\nSQ12[4:0]\n22\n21 20 19 18 rw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nrw rw\nSQ11[4:0]\n17\n16\nSQ10[4:1]\nReserved\n15\n14\nSQ10_\n0\nrw\nSQ9[4:0]\nrw\nrw\nBits 31:30\nrw\nSQ8[4:0]\nrw\nrw\nrw\nrw\nrw\nSQ7[4:0]\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBits 29:26 SQ12[4:0]: 12th conversion in regular sequence\nThese bits are written by software with the channel number (0..17) assigned as the 12th in the\nsequence to be converted.\nBits 24:20 SQ11[4:0]: 11th conversion in regular sequence\nBits 19:15 SQ10[4:0]: 10th conversion in regular sequence\nBits 14:10 SQ9[4:0]: 9th conversion in regular sequence\nBits 9:5 SQ8[4:0]: 8th conversion in regular sequence\nBits 4:0 SQ7[4:0]: 7th conversion in regular sequence\nDoc ID 13902 Rev 14\n239/1096 Analog-to-digital converter (ADC)\nRM0008\n11.12.11 ADC regular sequence register 3 (ADC_SQR3)\nAddress offset: 0x34\nReset value: 0x0000 0000\n31\n30\n29 28\nrw rw\n13 12\n27\n26 25 24 23\nrw rw rw rw rw\n11 10 9 8 7\nSQ6[4:0]\n22\n21 20 19 18 rw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nrw rw\nSQ5[4:0]\n17\n16\nSQ4[4:1]\nReserved\n15\n14\nSQ4_0\nrw\nSQ3[4:0]\nrw\nrw\nBits 31:30\nrw\nSQ2[4:0]\nrw\nrw\nrw\nrw\nrw\nSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBits 29:25 SQ6[4:0]: 6th conversion in regular sequence\nThese bits are written by software with the channel number (0..17) assigned as the 6th in the\nsequence to be converted.\nBits 24:20 SQ5[4:0]: 5th conversion in regular sequence\nBits 19:15 SQ4[4:0]: 4th conversion in regular sequence\nBits 14:10 SQ3[4:0]: 3rd conversion in regular sequence\nBits 9:5 SQ2[4:0]: 2nd conversion in regular sequence\nBits 4:0 SQ1[4:0]: 1st conversion in regular sequence\n240/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.12 ADC injected sequence register (ADC_JSQR)\nAddress offset: 0x38\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20 19 18 rw rw rw rw rw rw\n5 4 3 2 1 0\nrw rw\nJL[1:0]\n17\n16\nJSQ4[4:1]\nReserved\n15\n14\n13\nJSQ4_0\nrw\n12\n11\n10\n9\n8\nJSQ3[4:0]\nrw\nrw\nBits 31:22\nrw\n7\n6\nJSQ2[4:0]\nrw\nrw\nrw\nrw\nrw\nJSQ1[4:0]\nrw\nrw\nrw\nrw\nrw\nReserved, must be kept at reset value.\nBits 21:20 JL[1:0]: Injected sequence length\nThese bits are written by software to define the total number of conversions in the injected\nchannel conversion sequence.\n00: 1 conversion\n01: 2 conversions\n10: 3 conversions\n11: 4 conversions\nBits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0] = 3) (1)\nThese bits are written by software with the channel number (0..17) assigned as the 4th in\nthe sequence to be converted.\nNote: Unlike a regular conversion sequence, if JL[1:0] length is less than four, the channels\nare converted in a sequence starting from (4-JL). Example: ADC_JSQR[21:0] = 10\n00011 00011 00111 00010 means that a scan conversion will convert the following\nchannel sequence: 7, 3, 3. (not 2, 7, 3)\nBits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0] = 3)\nBits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0] = 3)\nBits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0] = 3)\n1. When JL=3 ( 4 injected conversions in the sequencer), the ADC converts the channels in this order:\nJSQ1[4:0] >> JSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]\nWhen JL=2 ( 3 injected conversions in the sequencer), the ADC converts the channels in this order:\nJSQ2[4:0] >> JSQ3[4:0] >> JSQ4[4:0]\nWhen JL=1 ( 2 injected conversions in the sequencer), the ADC converts the channels in this order:\nJSQ3[4:0] >> JSQ4[4:0]\nWhen JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0] channel\nDoc ID 13902 Rev 14\n241/1096 Analog-to-digital converter (ADC)\nRM0008\n11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4)\nAddress offset: 0x3C - 0x48\nReset value: 0x0000 0000\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nr r r r r r r\nReserved\n7\nJDATA[15:0]\nr\nr\nr\nBits 31:16\nr\nr\nr\nr\nr\nr\nReserved, must be kept at reset value.\nBits 15:0 JDATA[15:0]: Injected data\nThese bits are read only. They contain the conversion result from injected channel x. The\ndata is left or right-aligned as shown in Figure 27 and Figure 28.\n11.12.14 ADC regular data register (ADC_DR)\nAddress offset: 0x4C\nReset value: 0x0000 0000\n31 30 29 28 27 26 25\n24\nr r r r r r r r\n15 14 13 12 11 10 9 8\n23\n22 21 20 19 18 17 16\nr r r r r r r r\n7 6 5 4 3 2 1 0\nr r r r r r r\nADC2DATA[15:0]\nDATA[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 31:16 ADC2DATA[15:0]: ADC2 data\nIn ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to Section 11.9:\nDual ADC mode.\nIn ADC2 and ADC3: these bits are not used.\nBits 15:0 DATA[15:0]: Regular data\nThese bits are read only. They contain the conversion result from the regular channels. The\ndata is left or right-aligned as shown in Figure 27 and Figure 28.\n242/1096\nDoc ID 13902 Rev 14 RM0008\nAnalog-to-digital converter (ADC)\n11.12.15 ADC register map\nThe following table summarizes the ADC registers.\n0 0 0 0 0\n0x0C\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nADC_JOFR1\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nADC_JOFR2\nADC_JOFR3\n0\n0 0 0 0\n0 0 0 0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0\n0 0 0 0\n0 0 0 0\n0 0 0 0 0\n0 0 0 0 0\n0\n0\n0\n0\n0\n0\nSQ12[4:0] 12th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ6[4:0] 6th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\n0 0 0 0\nSQ11[4:0] 11th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ5[4:0] 5th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nJOFFSET4[11:0]\n0\n0\n0\n0\n0\n0\nHT[11:0]\n0\n0\n0\n0\n0\n0\nLT[11:0]\nReserved\nL[3:0]\n0\nJOFFSET3[11:0]\n0\nReserved\n0\nJOFFSET2[11:0]\nReserved\nADC_SQR1\nReset value\n0 0\n0\nADC_LTR\nADC_SQR3\n0 0\nReserved\n0x34\nReserved\n0 0\n0\nADC_HTR\nReset value\n0\nReserved\nADC_JOFR4\nADC_SQR2\n0\n0\nReset value\n0x30\n0\n0\nReserved\nReset value\n0x2C\n0\n0\nReset value\n0x28\n0\nJOFFSET1[11:0]\nReset value\n0x24\n0\nReserved\nReset value\n0x20\n0\nSample time bits SMPx_x\nReset value\n0x1C\n0\nAWDCH[4:0]\nSample time bits SMPx_x\nReset value\n0x18\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 JEXTSEL\n[2:0]\n0\nEXTSEL\n[2:0]\n0\nDISC\nNUM [2:0]\n0\n0\n0\n0\nADC_SMPR2\nReset value\n0x14\n0 0\nDUALMOD\n[3:0]\nADC_SMPR1\nReset value\n0x10\n0 0\nReset value\n0\nReserved\n0\nADC_CR2\n0\n0x08\n0 JSWSTART\nReset value\nReserved\nADC_CR1\nTSVREFE\n0x04\nSWSTART\nReset value\nReserved\nADC_SR\n0x00\nADC register map and reset values\nRegister\nOffset\nTable 72.\nSQ16[4:0] 16th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ10[4:0] 10th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ4[4:0] 4th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nDoc ID 13902 Rev 14\n0 0\nSQ15[4:0] 15th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ9[4:0] 9th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ3[4:0] 3rd\nconversion in\nregular sequence\nbits\n0 0 0 0 0\n0 0 0 0 0\nSQ14[4:0] 14th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ8[4:0] 8th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ2[4:0] 2nd\nconversion in\nregular sequence\nbits\n0 0 0 0 0\n0 0 0 0 0\nSQ13[4:0] 13th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ7[4:0] 7th\nconversion in\nregular sequence\nbits\n0 0 0 0 0\nSQ1[4:0] 1st\nconversion in\nregular sequence\nbits\n0 0 0 0 0\n243/1096 Analog-to-digital converter (ADC)\nOffset\n0x38\nADC register map and reset values (continued)\nRegister\nTable 72.\nRM0008\nADC_JSQR\nReserved\nReset value\n0x3C\nJSQ4[4:0] 4th\nJSQ3[4:0] 3rd\nJSQ2[4:0] 2nd\nJSQ1[4:0] 1st\nconversion in\nconversion in\nconversion in\nconversion in\ninjected sequence injected sequence injected sequence injected sequence\nbits\nbits\nbits\nbits\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nJL[1:0]\n0\nADC_JDR1\nJDATA[15:0]\nReserved\nReset value\n0x40\n0\nADC_JDR2\n0\nADC_JDR3\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nADC2DATA[15:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0\nRegular DATA[15:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nRefer to Table 1 on page 24 for the register boundary addresses.\n244/1096\n0\nJDATA[15:0]\nReserved\nADC_DR\n0\nJDATA[15:0]\n0\nADC_JDR4\nReset value\n0\nReserved\nReset value\n0x4C\n0\nJDATA[15:0]\nReset value\n0x48\n0\nReserved\nReset value\n0x44\n0\nDoc ID 13902 Rev 14\n0\n0\n0\n0\n0 RM0008\n12\nDigital-to-analog converter (DAC)\nDigital-to-analog converter (DAC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to connectivity line, high-density and XL-density STM32F101xx and\nSTM32F103xx devices only.\n12.1\nDAC introduction\nThe DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be\nconfigured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In\n12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each\nwith its own converter. In dual DAC channel mode, conversions could be done\nindependently or simultaneously when both channels are grouped together for synchronous\nupdate operation. An input reference pin V REF+ (shared with ADC) is available for better\nresolution.\n12.2\nDAC main features\n● Two DAC converters: one output channel each\n● Left or right data alignment in 12-bit mode\n● Synchronized update capability\n● Noise-wave generation\n● Triangular-wave generation\n● Dual DAC channel independent or simultaneous conversions\n● DMA capability for each channel\n● External triggers for conversion\n● Input voltage reference V REF+\nThe block diagram of a DAC channel is shown in Figure 40 and the pin description is given\nin Table 73.\nDoc ID 13902 Rev 14\n245/1096 Digital-to-analog converter (DAC)\nRM0008\nFigure 40. DAC channel block diagram\nDAC control register\nEXTI_9\nSWTR IGx\nTIM2_T RGO\nTIM4_T RGO\nTIM5_T RGO\nTIM6_T RGO\nTIM7_T RGO\nTIM8_T RGO (1)\nTSELx[2:0] bits\nDMAENx\nDM A req ue stx\n12-bit\nDHRx\nControl logicx\nLFSRx\ntrianglex\nTENx\nMAMPx[3:0] bits\nWAVENx[1:0] bits\n12-bit\nDORx\n12-bit\nV DDA\nDAC_ OU Tx\nDigital-to-analog\nconverterx\nV SSA\nV R EF+\nai14708c\n1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO .\nTable 73.\nName\nNote:\n246/1096\nDAC pins\nSignal type\nRemarks\nV REF+ Input, analog reference The higher/positive reference voltage for the DAC,\npositive\n2.4 V ≤ V REF + ≤ V DDA (3.3 V)\nV DDA Input, analog supply\nAnalog power supply\nV SSA Input, analog supply\nground\nGround for analog power supply\nDAC_OUTx Analog output signal\nDAC channelx analog output\nOnce the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is\nautomatically connected to the analog converter output (DAC_OUTx). In order to avoid\nparasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).\nDoc ID 13902 Rev 14 RM0008\nDigital-to-analog converter (DAC)\n12.3 DAC functional description\n12.3.1 DAC channel enable\nEach DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR\nregister. The DAC channel is then enabled after a startup time t WAKEUP .\nNote: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital\ninterface is enabled even if the ENx bit is reset.\n12.3.2 DAC output buffer enable\nThe DAC integrates two output buffers that can be used to reduce the output impedance,\nand to drive external loads directly without having to add an external operational amplifier.\nEach DAC channel output buffer can be enabled and disabled using the corresponding\nBOFFx bit in the DAC_CR register.\n12.3.3\nDAC data format\nDepending on the selected configuration mode, the data has to be written in the specified\nregister as described below:\n●\nSingle DAC channelx, there are three possibilities:\n– 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored\ninto DHRx[11:4] bits)\n– 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored\ninto DHRx[11:0] bits)\n– 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits\n(stored into DHRx[11:0] bits)\nDepending on the loaded DAC_DHRyyyx register, the data written by the user will be shifted\nand stored into the DHRx (Data Holding Registerx, that are internal non-memory-mapped\nregisters). The DHRx register will then be loaded into the DORx register either\nautomatically, by software trigger or by an external event trigger.\nDoc ID 13902 Rev 14\n247/1096 Digital-to-analog converter (DAC)\nRM0008\nFigure 41. Data registers in single DAC channel mode\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14710\n●\nDual DAC channels, there are three possibilities:\n– 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0]\nbits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into\nDAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits)\n– 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD\n[15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded\ninto DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits)\n– 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD\n[11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded\ninto DAC_DHR12LD [27:16] bits (stored into DHR2[11:0] bits)\nDepending on the loaded DAC_DHRyyyD register, the data written by the user will be\nshifted and stored into the DHR1 and DHR2 (Data Holding Registers, that are internal non-\nmemory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the\nDOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an\nexternal event trigger.\nFigure 42. Data registers in dual DAC channel mode\n31\n24\n15\n7\n0\n8-bit right aligned\n12-bit left aligned\n12-bit right aligned\nai14709\n12.3.4\nDAC conversion\nThe DAC_DORx cannot be written directly and any data transfer to the DAC channelx must\nbe performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx,\nDAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12LD).\nData stored into the DAC_DHRx register are automatically transferred to the DAC_DORx\nregister after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR\nregister is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR\nregister is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.\nWhen DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage\nbecomes available after a time of t SETTLING that depends on the power supply voltage and\nthe analog output load.\n248/1096\nDoc ID 13902 Rev 14 RM0008\nDigital-to-analog converter (DAC)\nFigure 43. Timing diagram for conversion with trigger disabled TEN = 0\nAPB1_CLK\nDHR\n0x1AC\nOutput voltage\navailable on DAC_OUT pin\n0x1AC\nDOR\nt SETTLING\nai14711b\n12.3.5\nDAC output voltage\nDigital inputs are converted to output voltages on a linear conversion between 0 and V REF+ .\nThe analog output voltages on each DAC channel pin are determined by the following\nequation:\nDOR\nDACoutput = V REF × --------------\n4095\n12.3.6\nDAC trigger selection\nIf the TENx control bit is set, conversion can then be triggered by an external event (timer\ncounter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possi-\nble events will trigger conversion as shown in Table 74.\nTable 74.\nExternal triggers\nSource\nType\nTSEL[2:0]\nTimer 6 TRGO event 000\nTimer 3 TRGO event in\nconnectivity line devices or\nTimer 8 TRGO in high-density\nand XL-density devices 001\nTimer 7 TRGO event\nInternal signal from on-chip\ntimers\n010\nTimer 5 TRGO event 011\nTimer 2 TRGO event 100\nTimer 4 TRGO event 101\nEXTI line9 External pin 110\nSWTRIG Software control bit 111\nEach time a DAC interface detects a rising edge on the selected timer TRGO output, or on\nthe selected external interrupt line 9, the last data stored into the DAC_DHRx register is\ntransferred into the DAC_DORx register. The DAC_DORx register is updated three APB1\ncycles after the trigger occurs.\nIf the software trigger is selected, the conversion starts once the SWTRIG bit is set.\nSWTRIG is reset by hardware once the DAC_DORx register has been loaded with the\nDAC_DHRx register contents.\nDoc ID 13902 Rev 14\n249/1096 Digital-to-analog converter (DAC)\nNote:\nRM0008\n1 TSELx[2:0] bit cannot be changed when the ENx bit is set.\n2 When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to-\nDAC_DORx register transfer.\n12.3.7\nDMA request\nEach DAC channel has a DMA capability. Two DMA channels are used to service DAC\nchannel DMA requests.\nA DAC DMA request is generated when an external trigger (but not a software trigger)\noccurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred\nto the DAC_DORx register.\nIn dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one\nDMA request is needed, you should set only the corresponding DMAENx bit. In this way, the\napplication can manage both DAC channels in dual mode by using one DMA request and a\nunique DMA channel.\nThe DAC DMA request is not queued so that if a second external trigger arrives before the\nacknowledgement of the last request, then the new request will not be serviced and no error\nis reported\n12.3.8\nNoise generation\nIn order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift Register is\navailable. The DAC noise generation is selected by setting WAVEx[1:0] to “01”. The\npreloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles\nafter each trigger event, following a specific calculation algorithm.\nFigure 44. DAC LFSR register calculation algorithm\nXOR\nX 6\nX\nX 4\nX 0\nX\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\n12\nNOR\nai14713b\nThe LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in\nthe DAC_CR register, is added up to the DAC_DHRx contents without overflow and this\nvalue is then stored into the DAC_DORx register.\nIf LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism).\nIt is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.\n250/1096\nDoc ID 13902 Rev 14 RM0008\nDigital-to-analog converter (DAC)\nFigure 45. DAC conversion (SW trigger enabled) with LFSR wave generation\nAPB1_CLK\nDHR\n0x00\n0xD55\n0xAAA\nDOR\nSWTRIG\nai14714\nNote: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR\nregister.\n12.3.9 Triangle-wave generation\nIt is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.\nDAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is\nconfigured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter\nis incremented three APB1 clock cycles after each trigger event. The value of this counter is\nthen added to the DAC_DHRx register without overflow and the sum is stored into the\nDAC_DORx register. The triangle counter is incremented while it is less than the maximum\namplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the\ncounter is decremented down to 0, then incremented again and so on.\nIt is possible to reset triangle wave generation by resetting WAVEx[1:0] bits.\nFigure 46. DAC triangle wave generation\n-!-0X;\u0013\u001a\u0010= Digital-to-analog converter (DAC)\nRM0008\nFigure 47. DAC conversion (SW trigger enabled) with triangle wave generation\nAPB1_CLK\nDHR\nDOR\n0xABE\n0xABE\n0xABF\n0xAC0\nSWTRIG\nai14714\nNote:\n1 DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR\nregister.\n2 MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be\nchanged.\n12.4\nDual DAC channel conversion\nTo efficiently use the bus bandwidth in applications that require the two DAC channels at the\nsame time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A\nunique register access is then required to drive both DAC channels at the same time.\nEleven possible conversion modes are possible using the two DAC channels and these dual\nregisters. All the conversion modes can nevertheless be obtained using separate DHRx\nregisters if needed.\nAll modes are described in the paragraphs below.\n12.4.1\nIndependent trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure different trigger sources by setting different values in the TSEL1[2:0] and\nTSEL2[2:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1\n(three APB1 clock cycles later).\nWhen a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2\n(three APB1 clock cycles later).\n252/1096\nDoc ID 13902 Rev 14 RM0008\n12.4.2\nDigital-to-analog converter (DAC)\nIndependent trigger with same LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure different trigger sources by setting different values in the TSEL1[2:0] and\nTSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask\nvalue in the MAMPx[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD\nor DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to\nthe DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles\nlater). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to\nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles\nlater). Then the LFSR2 counter is updated.\n12.4.3\nIndependent trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure different trigger sources by setting different values in the TSEL1[2:0] and\nTSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks\nvalues in the MAMP1[3:0] and MAMP2[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by\nMAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1\n(three APB1 clock cycles later). Then the LFSR1 counter is updated.\nWhen a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by\nMAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2\n(three APB1 clock cycles later). Then the LFSR2 counter is updated.\n12.4.4\nIndependent trigger with same triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure different trigger sources by setting different values in the TSEL1[2:0] and\nTSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum\namplitude value in the MAMPx[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same\ntriangle amplitude, is added to the DHR1 register and the sum is transferred into\nDoc ID 13902 Rev 14\n253/1096 Digital-to-analog converter (DAC)\nRM0008\nDAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then\nupdated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same\ntriangle amplitude, is added to the DHR2 register and the sum is transferred into\nDAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then\nupdated.\n12.4.5\nIndependent trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure different trigger sources by setting different values in the TSEL1[2:0] and\nTSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum\namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle\namplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is\ntransferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle\ncounter is then updated.\nWhen a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle\namplitude configured by MAMP2[3:0], is added to the DHR2 register part and the sum is\ntransferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle\ncounter is then updated.\n12.4.6\nSimultaneous software start\nTo configure the DAC in this conversion mode, the following sequence is required:\n●\nLoad the dual DAC channel data to the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nIn this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are\ntransferred into DAC_DOR1 and DAC_DOR2, respectively.\n12.4.7\nSimultaneous trigger without wave generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure the same trigger source for both DAC channels by setting the same value in\nthe TSEL1[2:0] and TSEL2[2:0] bits\n● Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and\nDAC_DOR2, respectively (after three APB1 clock cycles).\n254/1096\nDoc ID 13902 Rev 14 RM0008\n12.4.8\nDigital-to-analog converter (DAC)\nSimultaneous trigger with same LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure the same trigger source for both DAC channels by setting the same value in\nthe TSEL1[2:0] and TSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask\nvalue in the MAMPx[3:0] bits\n● Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or\nDHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1\nregister and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The\nLFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,\nis added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock\ncycles later). The LFSR2 counter is then updated.\n12.4.9\nSimultaneous trigger with different LFSR generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure the same trigger source for both DAC channels by setting the same value in\nthe TSEL1[2:0] and TSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks\nvalues using the MAMP1[3:0] and MAMP2[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is\nadded to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock\ncycles later). The LFSR1 counter is then updated.\nAt the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to\nthe DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles\nlater). The LFSR2 counter is then updated.\n12.4.10\nSimultaneous trigger with same triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure the same trigger source for both DAC channels by setting the same value in\nthe TSEL1[2:0] and TSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum\namplitude value using the MAMPx[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with the same triangle amplitude,\nis added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock\ncycles later). The DAC channel1 triangle counter is then updated.\nAt the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is\nDoc ID 13902 Rev 14\n255/1096 Digital-to-analog converter (DAC)\nRM0008\nadded to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock\ncycles later). The DAC channel2 triangle counter is then updated.\n12.4.11\nSimultaneous trigger with different triangle generation\nTo configure the DAC in this conversion mode, the following sequence is required:\n● Set the two DAC channel trigger enable bits TEN1 and TEN2\n● Configure the same trigger source for both DAC channels by setting the same value in\nthe TSEL1[2:0] and TSEL2[2:0] bits\n● Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum\namplitude values in the MAMP1[3:0] and MAMP2[3:0] bits\n● Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,\nDAC_DHR12LD or DAC_DHR8RD)\nWhen a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude\nconfigured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into\nDAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is\nupdated.\nAt the same time, the DAC channel2 triangle counter, with a triangle amplitude configured\nby MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2\n(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.\n12.5\nDAC registers\nThe peripheral registers have to be accessed by words (32-bit).\n12.5.1\nDAC control register (DAC_CR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\nReserved\n15\n14\nReserved\n28\n27\nDMA\nEN2\n13\n26\n25\n24\nMAMP2[3:0]\n23\n22\nWAVE2[1:0]\n20\n19\nTSEL2[2:0]\n18 17 16\nTEN2 BOFF2 EN2\nrw rw rw rw rw rw rw rw rw rw rw rw rw\n12 11 10 9 8 7 6 5 4 3 2 1 0\nTEN1 BOFF1 EN1\nrw rw rw\nDMA\nEN1\nrw\nMAMP1[3:0]\nrw\nrw\nrw\nWAVE1[1:0]\nrw\nrw\nrw\nBits 31:29 Reserved.\nBit 28 DMAEN2: DAC channel2 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel2 DMA mode disabled\n1: DAC channel2 DMA mode enabled\n256/1096\n21\nDoc ID 13902 Rev 14\nTSEL1[2:0]\nrw\nrw\nrw RM0008\nDigital-to-analog converter (DAC)\nBit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in\ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095\nBit 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable\nThese bits are set/reset by software.\n00: wave generation disabled\n01: Noise wave generation enabled\n1x: Triangle wave generation enabled\nNote: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)\nBits 21:19 TSEL2[2:0]: DAC channel2 trigger selection\nThese bits select the external event used to trigger DAC channel2\n000: Timer 6 TRGO event\n001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and\nXL-density devices\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger\nNote: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)\nBit 18 TEN2: DAC channel2 trigger enable\nThis bit set and cleared by software to enable/disable DAC channel2 trigger\n0: DAC channel2 trigger disabled and data written into DAC_DHRx register is transferred\none APB1 clock cycle later to the DAC_DOR2 register.\n1: DAC channel2 trigger enabled and data transfer from DAC_DHRx register is transferred\nthree APB1 clock cycles later to the DAC_DOR2 register.\nNote: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to\nDAC_DOR2 register transfer.\nBit 17 BOFF2: DAC channel2 output buffer disable\nThis bit set and cleared by software to enable/disable DAC channel2 output buffer.\n0: DAC channel2 output buffer enabled\n1: DAC channel2 output buffer disabled\nBit 16 EN2: DAC channel2 enable\nThis bit set and cleared by software to enable/disable DAC channel2.\n0: DAC channel2 disabled\n1: DAC channel2 enabled\nDoc ID 13902 Rev 14\n257/1096 Digital-to-analog converter (DAC)\nRM0008\nBits 15:13 Reserved.\nBit 12 DMAEN1: DAC channel1 DMA enable\nThis bit is set and cleared by software.\n0: DAC channel1 DMA mode disabled\n1: DAC channel1 DMA mode enabled\nBits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector\nThese bits are written by software to select mask in wave generation mode or amplitude in\ntriangle generation mode.\n0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1\n0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3\n0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7\n0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15\n0100: Unmask bits[4:0] of LFSR/ Triangle Amplitude equal to 31\n0101: Unmask bits[5:0] of LFSR/ Triangle Amplitude equal to 63\n0110: Unmask bits[6:0] of LFSR/ Triangle Amplitude equal to 127\n0111: Unmask bits[7:0] of LFSR/ Triangle Amplitude equal to 255\n1000: Unmask bits[8:0] of LFSR/ Triangle Amplitude equal to 511\n1001: Unmask bits[9:0] of LFSR/ Triangle Amplitude equal to 1023\n1010: Unmask bits[10:0] of LFSR/ Triangle Amplitude equal to 2047\n≥ 1011: Unmask bits[11:0] of LFSR/ Triangle Amplitude equal to 4095\nBits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable\nThese bits are set/reset by software.\n00: wave generation disabled\n01: Noise wave generation enabled\n1x: Triangle wave generation enabled\nNote: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)\nBits 5:3 TSEL1[2:0]: DAC channel1 trigger selection\nThese bits select the external event used to trigger DAC channel1\n000: Timer 6 TRGO event\n001: Timer 3 TRGO event in connectivity line devices, Timer 8 TRGO in high-density and\nXL-density devices\n010: Timer 7 TRGO event\n011: Timer 5 TRGO event\n100: Timer 2 TRGO event\n101: Timer 4 TRGO event\n110: External line9\n111: Software trigger\nNote: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)\nBit 2 TEN1: DAC channel1 trigger enable\nThis bit set and cleared by software to enable/disable DAC channel1 trigger\n0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred\none APB1 clock cycle later to the DAC_DOR1 register.\n1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred\nthree APB1 clock cycles later to the DAC_DOR1 register.\nNote: When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx to\nDAC_DOR1 register transfer.\n258/1096\nDoc ID 13902 Rev 14 RM0008\nDigital-to-analog converter (DAC)\nBit 1 BOFF1: DAC channel1 output buffer disable\nThis bit set and cleared by software to enable/disable DAC channel1 output buffer.\n0: DAC channel1 output buffer enabled\n1: DAC channel1 output buffer disabled\nBit 0 EN1: DAC channel1 enable\nThis bit set and cleared by software to enable/disable DAC channel1.\n0: DAC channel1 disabled\n1: DAC channel1 enabled\n12.5.2\nDAC software trigger register (DAC_SWTRIGR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18\n6 5 4 3 2\n17\n16\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nReserved\n1 0\nSWTRI\nG2 SWTRI\nG1\nw w\nBits 31:2 Reserved.\nBit 1 SWTRIG2: DAC channel2 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR2 register\nvalue is loaded to the DAC_DOR2 register.\nBit 0 SWTRIG1: DAC channel1 software trigger\nThis bit is set and cleared by software to enable/disable the software trigger.\n0: Software trigger disabled\n1: Software trigger enabled\nNote: This bit is reset by hardware (one APB1 clock cycle later) once the DAC_DHR1 register\nvalue is loaded to the DAC_DOR1 register.\nDoc ID 13902 Rev 14\n259/1096 Digital-to-analog converter (DAC)\n12.5.3\nRM0008\nDAC channel1 12-bit right-aligned data holding register\n(DAC_DHR12R1)\nAddress offset: 0x08\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved.\nBit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel1.\n12.5.4\nDAC channel1 12-bit left aligned data holding register\n(DAC_DHR12L1)\nAddress offset: 0x0C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n3 2 1 0\nReserved\n15 14 13 12 11\nrw rw rw rw rw\n10\n9\n8 7 6 5 4\nrw rw rw rw rw\nDACC1DHR[11:0]\nReserved\nrw\nrw\nBits 31:16 Reserved.\nBit 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel1.\nBits 3:0 Reserved.\n12.5.5\nDAC channel1 8-bit right aligned data holding register\n(DAC_DHR8R1)\nAddress offset: 0x10\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n7 6 5 4 3 2 1 0\nrw rw rw rw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\nDACC1DHR[7:0]\nReserved\nrw\nrw\nBits 31:8 Reserved.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data\nThese bits are written by software which specify 8-bit data for DAC channel1.\n260/1096\nDoc ID 13902 Rev 14 RM0008\nDigital-to-analog converter (DAC)\n12.5.6\nDAC channel2 12-bit right aligned data holding register\n(DAC_DHR12R2)\nAddress offset: 0x14\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nrw rw rw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nDACC2DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved.\nBits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel2.\n12.5.7\nDAC channel2 12-bit left aligned data holding register\n(DAC_DHR12L2)\nAddress offset: 0x18\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n3 2 1 0\nReserved\n15 14 13 12 11\nrw rw rw rw rw\n10\n9\n8 7 6 5 4\nrw rw rw rw rw\nDACC2DHR[11:0]\nReserved\nrw\nrw\nBits 31:16 Reserved.\nBits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel2.\nBits 3:0 Reserved.\n12.5.8\nDAC channel2 8-bit right-aligned data holding register\n(DAC_DHR8R2)\nAddress offset: 0x1C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n7 6 5 4 3 2 1 0\nrw rw rw rw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\nDACC2DHR[7:0]\nReserved\nrw\nrw\nBits 31:8 Reserved.\nBits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specify 8-bit data for DAC channel2.\nDoc ID 13902 Rev 14\n261/1096 Digital-to-analog converter (DAC)\n12.5.9\nRM0008\nDual DAC 12-bit right-aligned data holding register\n(DAC_DHR12RD)\nAddress offset: 0x20\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22\n21\n20 19 18 17 16\nDACC2DHR[11:0]\nReserved\n15\n14\n13\n12\nrw rw rw rw rw rw rw rw rw rw rw rw\n11 10 9 8 7 6 5 4 3 2 1 0\nrw rw rw rw rw\n17 16\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:28 Reserved.\nBits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel2.\nBits 15:12 Reserved.\nBits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel1.\n12.5.10\nDUAL DAC 12-bit left aligned data holding register\n(DAC_DHR12LD)\nAddress offset: 0x24\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24 23 22 21 20\n19\n18\nDACC2DHR[11:0]\nReserved\nrw rw rw rw rw\n15 14 13 12 11\nrw rw rw rw rw rw rw\n10 9 8 7 6 5 4\nrw rw rw rw rw\n3\n2\n1\nDACC1DHR[11:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel2.\nBits 19:16 Reserved.\nBits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data\nThese bits are written by software which specify 12-bit data for DAC channel1.\nBits 3:0 Reserved.\n262/1096\nDoc ID 13902 Rev 14\n0 RM0008\nDigital-to-analog converter (DAC)\n12.5.11\nDUAL DAC 8-bit right aligned data holding register\n(DAC_DHR8RD)\nAddress offset: 0x28\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21\n6 5\n20 19 18 17 16\n4 3 2 1 0\nrw rw rw\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nDACC2DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nDACC1DHR[7:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:16 Reserved.\nBits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data\nThese bits are written by software which specify 8-bit data for DAC channel2.\nBits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data\nThese bits are written by software which specify 8-bit data for DAC channel1.\n12.5.12\nDAC channel1 data output register (DAC_DOR1)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nr r r r r\nReserved\n15\n14\n13\n12\n11 10 9 8 7\nr r r r r\nDACC1DOR[11:0]\nReserved\nr\nr\nBits 31:12 Reserved.\nBit 11:0 DACC1DOR[11:0]: DAC channel1 data output\nThese bits are read only, they contain data output for DAC channel1.\n12.5.13\nDAC channel2 data output register (DAC_DOR2)\nAddress offset: 0x30\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nr r r r r\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nDACC2DOR[11:0]\nReserved\nr\nr\nr\nr\nr\nr\nr\nBits 31:12 Reserved.\nBit 11:0 DACC2DOR[11:0]: DAC channel2 data output\nThese bits are read only, they contain data output for DAC channel2.\nDoc ID 13902 Rev 14\n263/1096 Digital-to-analog converter (DAC)\n12.5.14\nRM0008\nDAC register map\nThe following table summarizes the DAC registers.\nDAC register map\n0x04 DAC_SWTRIG\nR\n0x08 DAC_DHR12R\n1\n0\n0\n0\n0\n0 0 0\n0\n0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\nTSEL1\n[2:0]\n0 0 0\nReserved\n0\n0\nWAVE\n1[2:0]\n0 MAMP1[3:0] 0\nReset value\nReserved\nWAVE\nTSEL2[2:0]\n2[2:0]\nMAMP2[3:0]\nReserved\nDAC_CR\n0x00\nRegister\nDMAEN2\nOffset\n31\nTable 75.\n0 0\n0 0\nReset value\nDACC1DHR[11:0]\nReserved\nReset value\n0x0C\n0\nDAC_DHR12L\n1\n0\nDAC_DHR8R1\n0x14 0x18 DAC_DHR12L\n2\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0\n0 0 0 0\n0 0\n0\nReserved\n0\n0\n0\n0\n0\n0\n0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0\n0 0 0 0\n0 0 0 0\nReserved\nDAC_DHR8R2\nDACC2DHR[7:0]\n0x1C\nReserved\n0x20 DAC_DHR12R\nD\n0x24 DAC_DHR12L\nD\nDACC2DHR[11:0]\nReserved\nReset value\nReset value\n0x30\n0\nDACC2DHR[11:0]\nReserved\nReset value\n0x2C\n0\nDACC2DHR[11:0]\nReserved\nReset value\n0x28\n0\nDACC1DHR[7:0]\nReserved\nReset value\nDAC_DHR12R\n2\n0\nDACC1DHR[11:0]\nReserved\nReset value\n0x10\n0\nDAC_DHR8RD\nReset value\nDAC_DOR1\nReset value\nDAC_DOR2\nReset value\nNote:\n264/1096\n0\n0\n0\n0\n0\n0 0 0\n0 0 0\nDACC2DHR[11:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\nReserved\nReserved\n0\n0 0\n0 0\n0\n0\n0\n0\n0\n0\n0 0 0\n0 0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\n0 0 0 0\n0 0 0 0\nDACC2DHR[7:0]\nDACC1DHR[7:0]\n0\n0\n0 0 0 0\n0 0 0 0\n0 0 0 0\nDACC1DOR[11:0]\n0\n0\n0\n0\n0\n0\n0\n0\nDACC2DOR[11:0]\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n0\nDACC1DHR[11:0]\nReserved\n0\nDACC1DHR[11:0]\nReserved\n0\n0\n0\n0\n0\n0 RM0008\n13\nDirect memory access controller (DMA)\nDirect memory access controller (DMA)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F10xxx family, unless otherwise specified.\n13.1\nDMA introduction\nDirect memory access (DMA) is used in order to provide high-speed data transfer between\nperipherals and memory as well as memory to memory. Data can be quickly moved by DMA\nwithout any CPU actions. This keeps CPU resources free for other operations.\nThe two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each\ndedicated to managing memory access requests from one or more peripherals. It has an\narbiter for handling the priority between DMA requests.\n13.2\nDMA main features\n● 12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2\n● Each of the 12 channels is connected to dedicated hardware DMA requests, software\ntrigger is also supported on each channel. This configuration is done by software.\n● Priorities between requests from channels of one DMA are software programmable (4\nlevels consisting of very high, high, medium, low) or hardware in case of equality\n(request 1 has priority over request 2, etc.)\n● Independent source and destination transfer size (byte, half word, word), emulating\npacking and unpacking. Source/destination addresses must be aligned on the data\nsize.\n● Support for circular buffer management\n● 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)\nlogically ORed together in a single interrupt request for each channel\n● Memory-to-memory transfer\n● Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral\ntransfers\n● Access to Flash, SRAM, APB1, APB2 and AHB peripherals as source and destination\n● Programmable number of data to be transferred: up to 65536\nDoc ID 13902 Rev 14\n265/1096 Direct memory access controller (DMA)\nRM0008\nThe block diagram is shown in Figure 48.\nFigure 48. DMA block diagram in connectivity line devices\n)#ODE\n&LASH\n&,)4&\n$#ODE\n#ORTEX\r-\u0013\n3YS TEM\n$-!\u0011\n#H\u000e\u0011\n$-!\n#H\u000e\u0012\n32!-\n2ESET RM0008\nDirect memory access controller (DMA)\nFigure 49. DMA block diagram in low-, medium- high- and XL-density devices\nICode\nFlash\nFLITF\nDCode\nCortex-M3\nSys tem\nCh.1\nDMA\nCh.2\nSRAM\nDMA1\nFSMC\nSDIO\nAHB System\nCh.7\nBridge 2\nBridge 1\nDMA\nArbiter\nDMA request\nAHB Slave\nDMA2\nCh.1\nDMA request\nCh.2\nAPB1\nAPB2\nUSART2 TIM2 USART1\nUSART3 TIM3 SPI1\nUART4\nTIM 4 ADC1\nSPI/I2S2 TIM5 ADC3\nSPI/I2S3 TIM6 TIM1\nI2C1\nTIM7 TIM8\nI2C2\nCh.5\nDMA request\nArbiter\nAHB Slave\nReset & clock control\n(RCC)\nai14801b\n1. The DMA2 controller is available only in high-density and XL-density devices.\n1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in high-\ndensity devices\n13.3\nDMA functional description\nThe DMA controller performs direct memory transfer by sharing the system bus with the\nCortex™-M3 core. The DMA request may stop the CPU access to the system bus for some\nbus cycles, when the CPU and DMA are targeting the same destination (memory or\nperipheral). The bus matrix implements round-robin scheduling, thus ensuring at least half\nof the system bus bandwidth (both to memory and peripheral) for the CPU.\n13.3.1\nDMA transactions\nAfter an event, the peripheral sends a request signal to the DMA Controller. The DMA\ncontroller serves the request depending on the channel priorities. As soon as the DMA\nController accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA\nController. The peripheral releases its request as soon as it gets the Acknowledge from the\nDMA Controller. Once the request is deasserted by the peripheral, the DMA Controller\nrelease the Acknowledge. If there are more requests, the peripheral can initiate the next\ntransaction.\nDoc ID 13902 Rev 14\n267/1096 Direct memory access controller (DMA)\nRM0008\nIn summary, each DMA transfer consists of three operations:\n13.3.2\n● The loading of data from the peripheral data register or a location in memory\naddressed through an internal current peripheral/memory address register. The start\naddress used for the first transfer is the base peripheral/memory address programmed\nin the DMA_CPARx or DMA_CMARx register\n● The storage of the data loaded to the peripheral data register or a location in memory\naddressed through an internal current peripheral/memory address register. The start\naddress used for the first transfer is the base peripheral/memory address programmed\nin the DMA_CPARx or DMA_CMARx register\n● The post-decrementing of the DMA_CNDTRx register, which contains the number of\ntransactions that have still to be performed.\nArbiter\nThe arbiter manages the channel requests based on their priority and launches the\nperipheral/memory access sequences.\nThe priorities are managed in two stages:\n●\n●\nSoftware: each channel priority can be configured in the DMA_CCRx register. There\nare four levels:\n– Very high priority\n– High priority\n– Medium priority\n– Low priority\nHardware: if 2 requests have the same software priority level, the channel with the\nlowest number will get priority versus the channel with the highest number. For\nexample, channel 2 gets priority over channel 4.\nNote: In high-density, XL-density and connectivity line devices, the DMA1 controller has priority\nover the DMA2 controller.\n13.3.3 DMA channels\nEach channel can handle DMA transfer between a peripheral register located at a fixed\naddress and a memory address. The amount of data to be transferred (up to 65535) is\nprogrammable. The register which contains the amount of data items to be transferred is\ndecremented after each transaction.\nProgrammable data sizes\nTransfer data sizes of the peripheral and memory are fully programmable through the PSIZE\nand MSIZE bits in the DMA_CCRx register.\nPointer incrementation\nPeripheral and memory pointers can optionally be automatically post-incremented after\neach transaction depending on the PINC and MINC bits in the DMA_CCRx register. If\nincremented mode is enabled, the address of the next transfer will be the address of the\nprevious one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer\naddress is the one programmed in the DMA_CPARx/DMA_CMARx registers. During\ntransfer operations, these registers keep the initially programmed value. The current transfer\n268/1096\nDoc ID 13902 Rev 14 RM0008\nDirect memory access controller (DMA)\naddresses (in the current internal peripheral/memory address register) are not accessible by\nsoftware.\nIf the channel is configured in noncircular mode, no DMA request is served after the last\ntransfer (that is once the number of data items to be transferred has reached zero). In order\nto reload a new number of data items to be transferred into the DMA_CNDTRx register, the\nDMA channel must be disabled.\nNote:\nIf a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers\n(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during\nthe channel configuration phase.\nIn circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded\nwith the initially programmed value. The current internal address registers are reloaded with\nthe base address values from the DMA_CPARx/DMA_CMARx registers.\nChannel configuration procedure\nThe following sequence should be followed to configure a DMA channelx (where x is the\nchannel number).\n1. Set the peripheral register address in the DMA_CPARx register. The data will be\nmoved from/ to this address to/ from the memory after the peripheral event.\n2. Set the memory address in the DMA_CMARx register. The data will be written to or\nread from this memory after the peripheral event.\n3. Configure the total number of data to be transferred in the DMA_CNDTRx register.\nAfter each peripheral event, this value will be decremented.\n4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register\n5. Configure data transfer direction, circular mode, peripheral & memory incremented\nmode, peripheral & memory data size, and interrupt after half and/or full transfer in the\nDMA_CCRx register\n6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.\nAs soon as the channel is enabled, it can serve any DMA request from the peripheral\nconnected on the channel.\nOnce half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is\ngenerated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,\nthe Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer\nComplete Interrupt Enable bit (TCIE) is set.\nCircular mode\nCircular mode is available to handle circular buffers and continuous data flows (e.g. ADC\nscan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.\nWhen circular mode is activated, the number of data to be transferred is automatically\nreloaded with the initial value programmed during the channel configuration phase, and the\nDMA requests continue to be served.\nMemory-to-memory mode\nThe DMA channels can also work without being triggered by a request from a peripheral.\nThis mode is called Memory to Memory mode.\nIf the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as\nsoon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register.\nDoc ID 13902 Rev 14\n269/1096 Direct memory access controller (DMA)\nRM0008\nThe transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory\nmode may not be used at the same time as Circular mode.\n13.3.4\nProgrammable data width, data alignment and endians\nWhen PSIZE and MSIZE are not equal, the DMA performs some data alignments as\ndescribed in Table 76: Programmable data width & endian behavior (when bits PINC =\nMINC = 1).\nTable 76.\nProgrammable data width & endian behavior (when bits PINC = MINC = 1)\nNumber\nSource\nof data\nDestination\nport\nitems to\nport width\nwidth\ntransfer\n(NDT)\nSource content:\naddress / data\nTransfer operations\nDestination\ncontent:\naddress / data\n8 8 4 @0x0 / B0\n@0x1 / B1\n@0x2 / B2\n@0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0\n2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1\n3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2\n4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0\n@0x1 / B1\n@0x2 / B2\n@0x3 / B3\n8 16 4 @0x0 / B0\n@0x1 / B1\n@0x2 / B2\n@0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0\n2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2\n3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4\n4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0\n@0x2 / 00B1\n@0x4 / 00B2\n@0x6 / 00B3\n8 32 4 @0x0 / B0\n@0x1 / B1\n@0x2 / B2\n@0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0\n2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4\n3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8\n4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0\n@0x4 / 000000B1\n@0x8 / 000000B2\n@0xC / 000000B3\n16 8 4 @0x0 / B1B0\n@0x2 / B3B2\n@0x4 / B5B4\n@0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0\n2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1\n3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2\n4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0\n@0x1 / B2\n@0x2 / B4\n@0x3 / B6\n16 16 4 @0x0 / B1B0\n@0x2 / B3B2\n@0x4 / B5B4\n@0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0\n2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2\n3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4\n4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0\n@0x2 / B3B2\n@0x4 / B5B4\n@0x6 / B7B6\n16 32 4 @0x0 / B1B0\n@0x2 / B3B2\n@0x4 / B5B4\n@0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0\n2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4\n3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8\n4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0\n@0x4 / 0000B3B2\n@0x8 / 0000B5B4\n@0xC / 0000B7B6\n32 8 4 @0x0 / B3B2B1B0\n@0x4 / B7B6B5B4\n@0x8 / BBBAB9B8\n@0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0\n2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1\n3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2\n4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0\n@0x1 / B4\n@0x2 / B8\n@0x3 / BC\n32 16 4 @0x0 / B3B2B1B0\n@0x4 / B7B6B5B4\n@0x8 / BBBAB9B8\n@0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0\n2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1\n3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2\n4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3 @0x0 / B1B0\n@0x2 / B5B4\n@0x4 / B9B8\n@0x6 / BDBC\n32 32 4 @0x0 / B3B2B1B0\n@0x4 / B7B6B5B4\n@0x8 / BBBAB9B8\n@0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0\n2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4\n3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8\n4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0x0 / B3B2B1B0\n@0x4 / B7B6B5B4\n@0x8 / BBBAB9B8\n@0xC / BFBEBDBC\nAddressing an AHB peripheral that does not support byte or halfword write\noperations\nWhen the DMA initiates an AHB byte or halfword write operation, the data are duplicated on\nthe unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does\nnot support byte or halfword write operations (when HSIZE is not used by the peripheral)\n270/1096\nDoc ID 13902 Rev 14 RM0008\nDirect memory access controller (DMA)\nand does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two\nexamples below:\n● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD”\nwith HSIZE = HalfWord\n● To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with\nHSIZE = Byte\nAssuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the\nHSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit\nAPB operation in the following manner:\n● an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be\nconverted to an APB word write operation of the data “0xB0B0B0B0” to 0x0\n● an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be\nconverted to an APB word write operation of the data “0xB1B0B1B0” to 0x0\nFor instance, if you want to write the APB backup registers (16-bit registers aligned to a 32-\nbit address boundary), you must configure the memory source size (MSIZE) to “16-bit” and\nthe peripheral destination size (PSIZE) to “32-bit”.\n13.3.5\nError management\nA DMA transfer error can be generated by reading from or writing to a reserved address\nspace. When a DMA transfer error occurs during a DMA read or a write access, the faulty\nchannel is automatically disabled through a hardware clear of its EN bit in the corresponding\nChannel configuration register (DMA_CCRx). The channel's transfer error interrupt flag\n(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error\ninterrupt enable bit (TEIE) in the DMA_CCRx register is set.\n13.3.6\nInterrupts\nAn interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each\nDMA channel. Separate interrupt enable bits are available for flexibility.\nTable 77.\nDMA interrupt requests\nInterrupt event\nNote:\nEvent flag Enable Control bit\nHalf-transfer HTIF HTIE\nTransfer complete TCIF TCIE\nTransfer error TEIF TEIE\nIn high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are\nmapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and\nDMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2\nChannel interrupts have their own interrupt vector.\nDoc ID 13902 Rev 14\n271/1096 Direct memory access controller (DMA)\n13.3.7\nRM0008\nDMA request mapping\nDMA1 controller\nThe 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and\nUSARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only\none request must be enabled at a time. Refer to Figure 50: DMA1 request mapping.\nThe peripheral DMA requests can be independently activated/de-activated by programming\nthe DMA control bit in the registers of the corresponding peripheral.\nFigure 50. DMA1 request mapping\nFixed hardware priority\nPeripheral\nrequest signals\nHigh priority\nADC1\nTIM2_CH3\nTIM4_CH1\nUSART3_TX\nTIM1_CH1\nTIM2_UP\nTIM3_CH3\nSPI1_RX\nUSART3_RX\nTIM1_CH2\nTIM3_CH4\nTIM3_UP\nSPI1_TX\nUSART1_TX\nTIM1_CH4\nTIM1_TRIG\nTIM1_COM\nTIM4_CH2\nSPI/I2S2_RX\nI2C2_TX\nHW request 1\nChannel 1\nSW trigger (MEM2MEM bit)\nChannel 1 EN bit\nHW request 2\nChannel 2\nSW trigger (MEM2MEM bit)\nChannel 2 EN bit\nHW request 3\nChannel 3\nSW trigger (MEM2MEM bit)\ninternal\nChannel 3 EN bit\nDMA1\nHW request 4\nrequest\nChannel 4\nSW trigger (MEM2MEM bit)\nChannel 4 EN bit\nUSART1_RX\nTIM1_UP\nSPI/I2S2_TX\nTIM2_CH1\nTIM4_CH3\nI2C2_RX\nHW request 5\nChannel 5\nSW trigger (MEM2MEM bit)\nChannel 5 EN bit\nUSART2_RX\nTIM1_CH3\nTIM3_CH1\nTIM3_TRIG\nI2C1_TX\nHW REQUEST 6\nChannel 6\nSW TRIGGER (MEM2MEM bit)\nChannel 6 EN bit\nUSART2_TX\nTIM2_CH2\nTIM2_CH4\nTIM4_UP\nI2C1_RX\nHW request 7\nLow priority\nSW trigger (MEM2MEM bit)\nChannel 7 EN bit\n272/1096\nChannel 7\nDoc ID 13902 Rev 14 RM0008\nDirect memory access controller (DMA)\nTable 78 lists the DMA requests for each channel.\nTable 78.\nSummary of DMA1 requests for each channel\nPeripherals Channel 1\nADC1\nChannel 2 Channel 3\nSPI1_RX SPI1_TX\nChannel 4\nChannel 5\nChannel 6\nADC1\nSPI/I 2 S\nUSART\nSPI2/I2S2_R SPI2/I2S2_T\nX\nX\nUSART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX\n2 I C I2C2_TX I2C2_RX I2C1_TX\nTIM1 TIM1_CH4\nTIM1_TRIG\nTIM1_COM TIM1_UP TIM1_CH3\nTIM2\nTIM1_CH1\nTIM2_CH3\nTIM3\nTIM4\nChannel 7\nTIM1_CH2\nTIM2_UP\nTIM3_CH3\nTIM4_CH1\nTIM2_CH2\nTIM2_CH4\nTIM2_CH1\nTIM3_CH4\nTIM3_UP\nI2C1_RX\nTIM3_CH1\nTIM3_TRIG\nTIM4_CH2\nTIM4_CH3\nTIM4_UP\nDMA2 controller\nThe 5 requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4,\nDAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this\nmeans that only one request must be enabled at a time. Refer to Figure 51: DMA2 request\nmapping.\nThe peripheral DMA requests can be independently activated/de-activated by programming\nthe DMA control bit in the registers of the corresponding peripheral.\nNote:\nThe DMA2 controller and its relative requests are available only in high-density, XL-density\nand connectivity line devices.\nDoc ID 13902 Rev 14\n273/1096 Direct memory access controller (DMA)\nRM0008\nFigure 51. DMA2 request mapping\nPeripheral request signals\nTIM5_CH4\nTIM5_TRIG\nTIM8_CH3\nTIM8_UP\nSPI/I2S3_RX\nFixed hardware priority\nHIGH PRIORITY\nHW request 1\nChannel 1\nSW trigger (MEM2MEM bit)\nChannel 1 EN bit\nTIM8_CH4\nTIM8_TRIG\nTIM8_COM\nTIM5_CH3\nTIM5_UP\nSPI/I2S3_TX\nTIM8_CH1\nUART4_RX\nTIM6_UP/DAC_Channel1\nHW request 2\nChannel 2\nSW trigger (MEM2MEM bit)\nChannel 2 EN bit\nHW request 3\nChannel 3\nSW trigger (MEM2MEM bit)\ninternal\nChannel 3 EN bit\nDMA2\nTIM5_CH2\nSDIO\nTIM7_UP/DAC_Channel2\nHW request 4\nrequest\nChannel 4\nSW trigger (MEM2MEM bit)\nChannel 4 EN bit\nADC3\nTIM8_CH2\nTIM5_CH1\nUART4_TX\nHW request 5\nChannel 5\nLOW PRIORITY\nSW trigger (MEM2MEM bit)\nChannel 5 EN bit\nTable 79 lists the DMA2 requests for each channel.\nTable 79.\nSummary of DMA2 requests for each channel\nPeripherals\nChannel 1\nChannel 2\nChannel 3\nChannel 4\nChannel 5\nADC3 (1)\nSPI/I2S3\nADC3\nSPI/I2S3_RX\nSPI/I2S3_TX\nUART4\nSDIO\nUART4_RX\n(1)\nTIM5\nSDIO\nTIM5_CH4\nTIM5_TRIG\nTIM5_CH3\nTIM5_UP\nTIM6/\nDAC_Channel1\nTIM5_CH2\nTIM5_CH1\nTIM6_UP/\nDAC_Channel1\nTIM7_UP/\nDAC_Channel2\nTIM7\nTIM8\nUART4_TX\nTIM8_CH3\nTIM8_UP\nTIM8_CH4\nTIM8_TRIG\nTIM8_COM\nTIM8_CH1\nTIM8_CH2\n1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices.\n274/1096\nDoc ID 13902 Rev 14 RM0008\nDirect memory access controller (DMA)\n13.4\nDMA registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nNote:\nIn the following registers, all bits related to channel6 and channel7 are not relevant for DMA2\nsince it has only 5 channels.\nThe peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-\nbit).\n13.4.1\nDMA interrupt status register (DMA_ISR)\nAddress offset: 0x00\nReset value: 0x0000 0000\n31\n30\n29\n28\n27 26 25 24 23 22 21 20 19 18 17 16\nTEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5\nr r r r r r r r r r r r\nReserved\n15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0\nTEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1\nr r r r r r r r r r r r r r r r\nBits 31:28\nReserved, must be kept at reset value.\nBits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7)\n11, 7, 3\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the\nDMA_IFCR register.\n0: No transfer error (TE) on channel x\n1: A transfer error (TE) occurred on channel x\nBits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7)\n10, 6, 2\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the\nDMA_IFCR register.\n0: No half transfer (HT) event on channel x\n1: A half transfer (HT) event occurred on channel x\nBits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7)\n9, 5, 1\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the\nDMA_IFCR register.\n0: No transfer complete (TC) event on channel x\n1: A transfer complete (TC) event occurred on channel x\nBits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7)\n8, 4, 0\nThis bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the\nDMA_IFCR register.\n0: No TE, HT or TC event on channel x\n1: A TE, HT or TC event occurred on channel x\nDoc ID 13902 Rev 14\n275/1096 Direct memory access controller (DMA)\n13.4.2\nRM0008\nDMA interrupt flag clear register (DMA_IFCR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\nCTEIF7 CHTIF7 CTCIF7\nCGIF7\n23\n22\n21\n20\nCTEIF6 CHTIF6 CTCIF6 CGIF6\n19\n18\n17\nCTEIF5 CHTIF5 CTCIF5\n16\nCGIF5\nReserved\n15\n14\n13\n12\nw w w w w w w w w w w w\n11 10 9 8 7 6 5 4 3 2 1 0\nCTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3\nw\nw\nw\nBits 31:28\nw\nw\nw\nw\nCGIF3\nw\nCTEIF2 CHTIF2 CTCIF2 CGIF2\nw\nw\nw\nw\nCTEIF1 CHTIF1 CTCIF1\nw\nReserved, must be kept at reset value.\nBits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1 ..7)\n11, 7, 3\nThis bit is set and cleared by software.\n0: No effect\n1: Clears the corresponding TEIF flag in the DMA_ISR register\nBits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1 ..7)\n10, 6, 2\nThis bit is set and cleared by software.\n0: No effect\n1: Clears the corresponding HTIF flag in the DMA_ISR register\nBits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1 ..7)\n9, 5, 1\nThis bit is set and cleared by software.\n0: No effect\n1: Clears the corresponding TCIF flag in the DMA_ISR register\nBits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1 ..7)\n8, 4, 0\nThis bit is set and cleared by software.\n0: No effect\n1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register\n276/1096\nDoc ID 13902 Rev 14\nw\nw\nCGIF1\nw RM0008\nDirect memory access controller (DMA)\n13.4.3\nDMA channel x configuration register (DMA_CCRx) (x = 1..7,\nwhere x = channel number)\nAddress offset: 0x08 + 0d20 × (channel number – 1)\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n7 6 5 4 3 2 1 0\nMINC PINC CIRC DIR TEIE HTIE TCIE EN\nrw rw rw rw rw rw rw rw\nReserved\n15 14\nRes. MEM2\nMEM\nrw\n13\n12\nPL[1:0]\nrw\nBits 31:15\nrw\n11\n10\n9\n8\nMSIZE[1:0] PSIZE[1:0]\nrw rw\nrw\nrw\nReserved, must be kept at reset value.\nBit 14 MEM2MEM: Memory to memory mode\nThis bit is set and cleared by software.\n0: Memory to memory mode disabled\n1: Memory to memory mode enabled\nBits 13:12 PL[1:0]: Channel priority level\nThese bits are set and cleared by software.\n00: Low\n01: Medium\n10: High\n11: Very high\nBits 11:10 MSIZE[1:0]: Memory size\nThese bits are set and cleared by software.\n00: 8-bits\n01: 16-bits\n10: 32-bits\n11: Reserved\nBits 9:8 PSIZE[1:0]: Peripheral size\nThese bits are set and cleared by software.\n00: 8-bits\n01: 16-bits\n10: 32-bits\n11: Reserved\nBit 7 MINC: Memory increment mode\nThis bit is set and cleared by software.\n0: Memory increment mode disabled\n1: Memory increment mode enabled\nBit 6 PINC: Peripheral increment mode\nThis bit is set and cleared by software.\n0: Peripheral increment mode disabled\n1: Peripheral increment mode enabled\nBit 5 CIRC: Circular mode\nThis bit is set and cleared by software.\n0: Circular mode disabled\n1: Circular mode enabled\nDoc ID 13902 Rev 14\n277/1096 Direct memory access controller (DMA)\nRM0008\nBit 4 DIR: Data transfer direction\nThis bit is set and cleared by software.\n0: Read from peripheral\n1: Read from memory\nBit 3 TEIE: Transfer error interrupt enable\nThis bit is set and cleared by software.\n0: TE interrupt disabled\n1: TE interrupt enabled\nBit 2 HTIE: Half transfer interrupt enable\nThis bit is set and cleared by software.\n0: HT interrupt disabled\n1: HT interrupt enabled\nBit 1 TCIE: Transfer complete interrupt enable\nThis bit is set and cleared by software.\n0: TC interrupt disabled\n1: TC interrupt enabled\nBit 0 EN: Channel enable\nThis bit is set and cleared by software.\n0: Channel disabled\n1: Channel enabled\n13.4.4\nDMA channel x number of data register (DMA_CNDTRx) (x = 1..7),\nwhere x = channel number)\nAddress offset: 0x0C + 0d20 × (channel number – 1)\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw rw\nReserved\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\nNDT\nBits 31:16\nReserved, must be kept at reset value.\nBits 15:0 NDT[15:0]: Number of data to transfer\nNumber of data to be transferred (0 up to 65535). This register can only be written when the\nchannel is disabled. Once the channel is enabled, this register is read-only, indicating the\nremaining bytes to be transmitted. This register decrements after each DMA transfer.\nOnce the transfer is completed, this register can either stay at zero or be reloaded\nautomatically by the value previously programmed if the channel is configured in auto-reload\nmode.\nIf this register is zero, no transaction can be served whether the channel is enabled or not.\n278/1096\nDoc ID 13902 Rev 14 RM0008\nDirect memory access controller (DMA)\n13.4.5\nDMA channel x peripheral address register (DMA_CPARx) (x = 1..7),\nwhere x = channel number)\nAddress offset: 0x10 + 0d20 × (channel number – 1)\nReset value: 0x0000 0000\nThis register must not be written when the channel is enabled.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9 8 7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw rw rw rw\nPA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 PA[31:0]: Peripheral address\nBase address of the peripheral data register from/to which the data will be read/written.\nWhen PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-\nword address.\nWhen PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word\naddress.\n13.4.6\nDMA channel x memory address register (DMA_CMARx) (x = 1..7),\nwhere x = channel number)\nAddress offset: 0x14 + 0d20 × (channel number – 1)\nReset value: 0x0000 0000\nThis register must not be written when the channel is enabled.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9 8 7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw rw rw rw\nMA\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:0 MA[31:0]: Memory address\nBase address of the memory area from/to which the data will be read/written.\nWhen MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a\nhalf-word address.\nWhen MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word\naddress.\nDoc ID 13902 Rev 14\n279/1096 Direct memory access controller (DMA)\n13.4.7\nRM0008\nDMA register map\nThe following table gives the DMA register map and the reset values.\nDMA register map and reset values\n0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR1\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\nPA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR2\nReset value\n0\n0\nDMA_CPAR2\nReset value\n0\nNDT[15:0]\nReserved\nReset value\n0\nDMA_CNDTR2\nReserved\n0\n0\nMA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\nPA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR3\nReset value\n0\nReset value\n0\n0\nDMA_CPAR3\n0x038\n0\nNDT[15:0]\nReserved\nReset value\n0\nReset value\nDMA_CNDTR3\nReserved\nDMA_CCR3\n0x030\nReserved\n0x02C\n0\n0\nMA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n280/1096\nDoc ID 13902 Rev 14\n0\nReserved\n0\nReset value\n0\nReset value\nDMA_CNDTR4\nReserved\nDMA_CCR4\n0x044\nReserved\n0x040\n0x048\n0\n0\nSIZE\nDMA_CCR2\n0x024\n0x03C\n0 0\nReset value\n0x034\n0\nReserved\n0x01C\n0x028\n0\nMA[31:0]\n0x018\n0x020\n0\nReset value\n0\nPA[31:0]\n0x014\n0\nDMA_CPAR1\n0x010\n0\n0\nNDT[15:0]\nReserved\nReset value\n0\n0\n0\n0x00C\n0\n0 0 0\n0\nReset value\nDMA_CNDTR1\n0 PL\n[1:0]\nReserved\n0 0\n0 0\nDMA_CCR1\n0x008\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nReset value\n0\nReserved\n0 CTCIF7\nDMA_IFCR\n0x004\nReserved\nReset value\nDMA_ISR\n0x000\nCTEIF7\nRegister\nCHTIF7\nOffset\n31\nTable 80.\n0 0 0 0 0 0 0\n0 0 0 0 0 0\nNDT[15:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 RM0008\nDirect memory access controller (DMA)\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR4\nReset value\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\nMA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0x088\n0x08C\n0x090\n0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\n0\n0\n0\n0\n0\n0\nDMA_CNDTR6\n0\nDMA_CPAR6\nReset value\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPL\n[1:0] 0 0 0 0 0\nPA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR6\nReset value\n0\nNDT[15:0]\nReserved\nReset value\n0\nReserved\nDMA_CCR6\n0\n0\nMA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CNDTR7\n0\nDMA_CPAR7\nReset value\n0\n0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\nPA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDMA_CMAR7\nReset value\n0\nNDT[15:0]\nReserved\nReset value\n0\nReserved\nCIRC\nDMA_CCR7\nPINC\nReserved\nReset value\n0x084\n0\nReserved\n0x07C\n0x080\n0\n0x078\n0\n0x074\n0 0\nReset value\n0x070\n0\nMA[31:0]\n0x068\n0x06C\n0\nDMA_CMAR5\nReset value\n0\nReset value\n0\nPA[31:0]\n0x064\n0\nDMA_CPAR5\n0x060\n0\nNDT[15:0]\nReserved\nReset value\n0\n0x05C\n0\nReset value\nDMA_CNDTR5\nReserved\nDMA_CCR5\nReserved\n0x054\n0x058\n0\nPA[31:0]\n0\n0x050\nReset value\n0x04C\nRegister\nDMA_CPAR4\nOffset\nDMA register map and reset values (continued)\nTable 80.\n0\n0\nMA[31:0]\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\nRefer to for the register boundary addresses.\nDoc ID 13902 Rev 14\n281/1096 Advanced-control timers (TIM1&TIM8)\n14\nRM0008\nAdvanced-control timers (TIM1&TIM8)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nLow- and medium-density STM32F103xx devices, and the STM32F105xx/STM32F107xx\nconnectivity line devices, contain one advanced-control timer (TIM1) whereas high-density\nand XL-density STM32F103xx devices feature two advance-control timers (TIM1 and TIM8).\n14.1\nTIM1&TIM8 introduction\nThe advanced-control timers (TIM1&TIM8) consist of a 16-bit auto-reload counter driven by\na programmable prescaler.\nIt may be used for a variety of purposes, including measuring the pulse lengths of input\nsignals (input capture) or generating output waveforms (output compare, PWM,\ncomplementary PWM with dead-time insertion).\nPulse lengths and waveform periods can be modulated from a few microseconds to several\nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe advanced-control (TIM1&TIM8) and general-purpose (TIMx) timers are completely\nindependent, and do not share any resources. They can be synchronized together as\ndescribed in Section 14.3.20.\n282/1096\nDoc ID 13902 Rev 14 RM0008\n14.2\nAdvanced-control timers (TIM1&TIM8)\nTIM1&TIM8 main features\nTIM1&TIM8 timer features include:\n● 16-bit up, down, up/down auto-reload counter.\n● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock\nfrequency either by any factor between 1 and 65535.\n● Up to 4 independent channels for:\n– Input Capture\n– Output Compare\n– PWM generation (Edge and Center-aligned Mode)\n– One-pulse mode output\n● Complementary outputs with programmable dead-time\n● Synchronization circuit to control the timer with external signals and to interconnect\nseveral timers together.\n● Repetition counter to update the timer registers only after a given number of cycles of\nthe counter.\n● Break input to put the timer’s output signals in reset state or in a known state.\n● Interrupt/DMA generation on the following events:\n– Update: counter overflow/underflow, counter initialization (by software or\ninternal/external trigger)\n– Trigger event (counter start, stop, initialization or count by internal/external trigger)\n– Input capture\n– Output compare\n– Break input\n● Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning\npurposes\n● Trigger input for external clock or cycle-by-cycle current management\nDoc ID 13902 Rev 14\n283/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 52. Advanced-control timer block diagram\nInternal Clock (CK_INT)\nCK_TIM18 from RCC\nETRF\nTrigger\nController\nETRP\nETR\nTIMx_ETR\nPolarity Selection & Edge\nDetector & Prescaler\nTRGO\nInput Filter\nITR0\nITR2\nto other timers\nto DAC/ADC\nTGI\nITR\nITR1\nTRC\nTRGI\nITR3\nSlave\nMode\nController\nReset, Enable, Up/Down, Count\nTI1F_ED\nTI1FP1\nEncoder\nInterface\nTI2FP2\nREP Register\nU\nUI\nAutoReload Register\nRepetition\ncounter\nStop, Clear or Up/Down\nCK_PSC\nPSC\nCK_CNT\nPrescaler\nXOR\nTI1\nInput Filter &\nEdge detector\nTI2\nInput Filter &\nEdge detector\nTI2FP1\nTI2FP2\nCOUNTER\nCC1I\nCC1I\nIC1\nPrescaler\nTRC\nTIMx_CH1\nTIMx_CH2\nTI1FP1\nTI1FP2\n+/-\nIC1PS U\nCapture/Compare 1 Register\nPrescaler\nIC2PS U\nDTG registers\nOC1REF\nTIMx_CH1\nDTG\nCapture/Compare 2 Register\nInput Filter &\nEdge detector\nTI3FP3\nTI3FP4\nIC3\nPrescaler\nTRC\nTIMx_CH4\nTI4\nInput Filter &\nEdge detector\nTI4FP3\nTI4FP4\nOC2REF\nTIMx_CH2\nDTG\nIC3PS\nU\nCapture/Compare 3 Register\nPolarity Selection\nTIMx_CH2N\nIC4\nPrescaler\nIC4PS\nOC3REF\nTIMx_CH3\nDTG\noutput OC3\ncontrol\nTIMx_CH3N\nCC4I\nTIMx_CH4\nU\nCapture/Compare 4 Register\nBI\nClock failure event from clock controller\nCSS (Clock Security system\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nevent\ninterrupt & DMA output\n284/1096\ncontrol\nOC3N\nCC4I\nETRF\nBRK\noutput OC2\nCC3I\nTRC\nTIMx_BKIN\nTIMx_CH1N\nOC2N\nCC3I\nTI3\ncontrol\nCC2I\nTRC\nTIMx_CH3\noutput OC1\nOC1N\nCC2I\nIC2\nU\nCNT\nDoc ID 13902 Rev 14\nOC4REF\noutput\ncontrol OC4 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.3 TIM1&TIM8 functional description\n14.3.1 Time-base unit\nThe main block of the programmable advanced-control timer is a 16-bit counter with its\nrelated auto-reload register. The counter can count up, down or both up and down. The\ncounter clock can be divided by a prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by\nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n● Counter register (TIMx_CNT)\n● Prescaler register (TIMx_PSC)\n● Auto-reload register (TIMx_ARR)\n● Repetition counter register (TIMx_RCR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register\naccesses the preload register. The content of the preload register are transferred into the\nshadow register permanently or at each update event (UEV), depending on the auto-reload\npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter\nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the\nTIMx_CR1 register. It can also be generated by software. The generation of the update\nevent is described in detailed for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the\ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller\ndescription to get more details on counter enabling).\nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1\nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It\nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).\nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is\ntaken into account at the next update event.\nFigure 54 and Figure 55 give some examples of the counter behavior when the prescaler\nratio is changed on the fly:\nDoc ID 13902 Rev 14\n285/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 53. Counter timing diagram with prescaler division change from 1 to 2\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\n02\n03\nUpdate event (UEV)\nPrescaler control register\n0\n1\nWrite a new value in TIMx_PSC\nPrescaler buffer 0\nPrescaler counter 0\n1\n0\n1\n0\n1\n0\n1\n0\n1\nFigure 54. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\nUpdate event (UEV)\nPrescaler control register\n0\n3\nWrite a new value in TIMx_PSC\n14.3.2\nPrescaler buffer 0\nPrescaler counter 0\n3\n0\n1\n2\n3\n0\n1\n2\n3\nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the\nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nIf the repetition counter is used, the update event (UEV) is generated after upcounting is\nrepeated for the number of times programmed in the repetition counter register\n(TIMx_RCR). Else the update event is generated at each counter overflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode\ncontroller) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\n286/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\npreload registers. Then no update event occurs until the UDIS bit has been written to 0.\nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the\nprescale rate does not change). In addition, if the URS bit (update request selection) in\nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without\nsetting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating\nboth update and capture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The repetition counter is reloaded with the content of TIMx_RCR register,\n● The auto-reload shadow register is updated with the preload value (TIMx_ARR),\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister).\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR=0x36.\nFigure 55. Counter timing diagram, internal clock divided by 1\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 56. Counter timing diagram, internal clock divided by 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035 0036\n0000\n0001\n0002\n0003\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n287/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 57. Counter timing diagram, internal clock divided by 4\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0035\n0000\n0036\n0001\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 58. Counter timing diagram, internal clock divided by N\nCK_PSC\nTimer clock = CK_CNT\nCounter register\n1F\n00\n20\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\nWrite a new value in TIMx_ARR\n288/1096\nDoc ID 13902 Rev 14\n36 RM0008\nAdvanced-control timers (TIM1&TIM8)\nFigure 60. Counter timing diagram, update event when ARPE=1\n(TIMx_ARR preloaded)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF0\nF1 F2 F3 F4 F5 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register F5 36\nAuto-reload shadow register F5 36\nWrite a new value in TIMx_ARR\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the\nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a\ncounter underflow event.\nIf the repetition counter is used, the update event (UEV) is generated after downcounting is\nrepeated for the number of times programmed in the repetition counter register\n(TIMx_RCR). Else the update event is generated at each counter underflow.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode\ncontroller) also generates an update event.\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\npreload registers. Then no update event occurs until UDIS bit has been written to 0.\nHowever, the counter restarts from the current auto-reload value, whereas the counter of the\nprescaler restarts from 0 (but the prescale rate doesn’t change).\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the\nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or\nDMA request is sent). This is to avoid generating both update and capture interrupts when\nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The repetition counter is reloaded with the content of TIMx_RCR register\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister)\n● The auto-reload active register is updated with the preload value (content of the\nTIMx_ARR register). Note that the auto-reload is updated before the counter is\nreloaded, so that the next period is the expected one\nDoc ID 13902 Rev 14\n289/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR=0x36.\nFigure 61. Counter timing diagram, internal clock divided by 1\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n04 03 02 01 00 36 35 34 33 32 31 30 2F\n05\nCounter underflow (cnt_udf)\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 62. Counter timing diagram, internal clock divided by 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0002\n0001 0000\n0036\n0035\n0034\n0033\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 63. Counter timing diagram, internal clock divided by 4\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0001\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n290/1096\nDoc ID 13902 Rev 14\n0000\n0036\n0035 RM0008\nAdvanced-control timers (TIM1&TIM8)\nFigure 64. Counter timing diagram, internal clock divided by N\nCK_PSC\nTimer clock = CK_CNT\nCounter register\n20\n1F\n00\n36\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 65. Counter timing diagram, update event when repetition counter\nis not used\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\n05\n04 03 02 01 00 36 35 34 33 32 31 30 2F\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\n36\nWrite a new value in TIMx_ARR\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the\nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting\nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to\n'00'. The Output compare interrupt flag of channels configured in output is set when: the\ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center\naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3,\nCMS = \"11\").\nIn this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated\nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow\nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode\ncontroller) also generates an update event. In this case, the counter restarts counting from\n0, as well as the counter of the prescaler.\nDoc ID 13902 Rev 14\n291/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nThe UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\npreload registers. Then no update event occurs until UDIS bit has been written to 0.\nHowever, the counter continues counting up and down, based on the current auto-reload\nvalue.\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the\nUG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or\nDMA request is sent). This is to avoid generating both update and capture interrupts when\nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The repetition counter is reloaded with the content of TIMx_RCR register\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister)\n● The auto-reload active register is updated with the preload value (content of the\nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected\none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock\nfrequencies.\nFigure 66. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n04\n03 02 01 00 01 02 03 04 05 06 05 04 03\nCounter underflow\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n1. Here, center-aligned mode 1 is used (for more details refer to Section 14.4: TIM1&TIM8 registers on page 323).\n292/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nFigure 67. Counter timing diagram, internal clock divided by 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0003\n0002 0001\n0000\n0001\n0002\n0003\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035\n0036\n0035\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n1. Center-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 69. Counter timing diagram, internal clock divided by N\nCK_PSC\nTimer clock = CK_CNT\nCounter register\n20\n1F\n01\n00\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n293/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 70. Counter timing diagram, update event with ARPE=1 (counter underflow)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\n06\n05 04 03 02 01 00 01 02 03 04 05 06 07\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register\nFD\n36\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\nFigure 71. Counter timing diagram, Update event with ARPE=1 (counter overflow)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC 36 35 34 33 32 31 30 2F\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register\nFD\n36\nWrite a new value in TIMx_ARR\nAuto-reload active register\n14.3.3\nFD\n36\nRepetition counter\nSection 14.3.1: Time-base unit describes how the update event (UEV) is generated with\nrespect to the counter overflows/underflows. It is actually generated only when the repetition\ncounter has reached zero. This can be useful when generating PWM signals.\nThis means that data are transferred from the preload registers to the shadow registers\n(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx\ncapture/compare registers in compare mode) every N counter overflows or underflows,\nwhere N is the value in the TIMx_RCR repetition counter register.\n294/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nThe repetition counter is decremented:\n● At each counter overflow in upcounting mode,\n● At each counter underflow in downcounting mode,\n● At each counter overflow and at each counter underflow in center-aligned mode.\nAlthough this limits the maximum number of repetition to 128 PWM cycles, it makes it\npossible to update the duty cycle twice per PWM period. When refreshing compare\nregisters only once per PWM period in center-aligned mode, maximum resolution is\n2xT ck , due to the symmetry of the pattern.\nThe repetition counter is an auto-reload type; the repetition rate is maintained as defined by\nthe TIMx_RCR register value (refer to Figure 72). When the update event is generated by\nsoftware (by setting the UG bit in TIMx_EGR register) or by hardware through the slave\nmode controller, it occurs immediately whatever the value of the repetition counter is and the\nrepetition counter is reloaded with the content of the TIMx_RCR register.\nIn center-aligned mode, for odd values of RCR, the update event occurs either on the\noverflow or on the underflow depending on when the RCR register was written and when the\ncounter was started. If the RCR was written before starting the counter, the UEV occurs on\nthe overflow. If the RCR was written after starting the counter, the UEV occurs on the\nunderflow. For example for RCR = 3, the UEV is generated on each 4th overflow or\nunderflow event depending on when RCR was written.\nFigure 72. Update rate examples depending on mode and TIMx_RCR register\nsettings\nCenter-aligned mode\nEdge-aligned mode\nUpcounting\nDowncounting\nCounter\nTIMx_CNT\nTIMx_RCR = 0 UEV\nTIMx_RCR = 1 UEV\nTIMx_RCR = 2 UEV\nTIMx_RCR = 3 UEV\nTIMx_RCR = 3\nand\nre-synchronization\nUEV\n(by SW)\nUEV\n(by SW)\n(by SW)\nUpdate Event: Preload registers transferred to active registers and update interrupt generated\nDoc ID 13902 Rev 14\n295/1096 Advanced-control timers (TIM1&TIM8)\n14.3.4\nRM0008\nClock selection\nThe counter clock can be provided by the following clock sources:\n● Internal clock (CK_INT)\n● External clock mode1: external input pin\n● External clock mode2: external trigger input ETR\n● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for\nexample, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Using\none timer as prescaler for another for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1\nregister) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed\nonly by software (except UG which remains cleared automatically). As soon as the CEN bit\nis written to 1, the prescaler is clocked by the internal clock CK_INT.\nFigure 73 shows the behavior of the control circuit and the upcounter in normal mode,\nwithout prescaler.\nFigure 73. Control circuit in normal mode, internal clock divided by 1\nInternal clock\nCEN=CNT_EN\nUG\nCNT_INIT\nCounter clock = CK_CNT = CK_PSC\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count\nat each rising or falling edge on a selected input.\nFigure 74. TI2 external clock connection example\nTIMx_SMCR\nTS[2:0]\nor\nITRx\nTI2F_Rising\nTI2\nFilter\nICF[3:0]\nTIMx_CCMR1\nEdge\nDetector TI2F_Falling\n0\n1\nTI2F\nTI1F\nor\nor\n0xx\nencoder\nmode\nTI1_ED 100\nTI1FP1 101 TRGI external clock\nmode 1\nCK_PSC\nTI2FP2 110\nETRF 111 ETRF external clock\nmode 2\nCC2P\nTIMx_CCER\nCK_INT\ninternal clock\nmode\n(internal clock)\nECE SMS[2:0]\nTIMx_SMCR\n296/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nFor example, to configure the upcounter to count in response to a rising edge on the TI2\ninput, use the following procedure:\nNote:\n1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in\nthe TIMx_CCMR1 register.\n2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1\nregister (if no filter is needed, keep IC2F=0000).\n3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.\n4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR\nregister.\n5. Select TI2 as the trigger input source by writing TS=110 in the TIMx_SMCR register.\n6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe capture prescaler is not used for triggering, so you don’t need to configure it.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the\nresynchronization circuit on TI2 input.\nFigure 75. Control circuit in external clock mode 1\nTI2\nCNT_EN\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35\n36\nTIF\nWrite TIF=0\nExternal clock source mode 2\nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 76 gives an overview of the external trigger input block.\nFigure 76. External trigger input block\nor\nETR pin\nETR\n0\n1\ndivider\n/1, /2, /4, /8\nETRP\nf DTS\nfilter\ndowncounter\nTI2F\nTI1F\nor\nor\nencoder\nmode\nTRGI external clock\nmode 1\nCK_PSC\nETRF external clock\nmode 2\nCK_INT internal clock\nmode\n(internal clock)\nETP\nTIMx_SMCR\nETPS[1:0]\nETF[3:0]\nTIMx_SMCR\nDoc ID 13902 Rev 14\nTIMx_SMCR\nECE SMS[2:0]\nTIMx_SMCR\n297/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the\nfollowing procedure:\n1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register\n3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR\nregister\n4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the\nresynchronization circuit on the ETRP signal.\nFigure 77. Control circuit in external clock mode 2\nf CK_INT\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = CK_CNT = CK_PSC\nCounter register\n14.3.5\n34\n35\n36\nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a\nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and\nan output stage (with comparator and output control).\nFigure 78 to Figure 81 give an overview of one Capture/Compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF.\nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be\nused as trigger input by the slave mode controller or as the capture command. It is\nprescaled before the capture register (ICxPS).\n298/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nFigure 78. Capture/compare channel (example: channel 1 input stage)\nTI1F_ED\nto the slave mode controller\nTI1\nf DTS\nfilter\ndowncounter\nTI1F\nTI1F_Rising\nEdge\nDetector\nTI1F_Falling\nICF[3:0] CC1P/CC1NP\nTIMx_CCMR1 TIMx_CCER\nTI2F_rising\n(from channel 2)\nTI2F_falling\n(from channel 2)\n0\nTI1FP1\n1\n01\nTI2FP1\n10\nIC1\ndivider\n/1, /2, /4, /8\nIC1PS\nTRC\n11\n(from slave mode\ncontroller)\n0\nCC1S[1:0] ICPS[1:0]\n1\nTIMx_CCMR1\nCC1E\nTIMx_CCER\nThe output stage generates an intermediate waveform which is then used for reference:\nOCxRef (active high). The polarity acts at the end of the chain.\nFigure 79. Capture/compare channel 1 main circuit\nAPB Bus\nread CCR1L\nread_in_progress\nCC1S[0]\nIC1PS\nwrite_in_progress\nCapture/compare preload register\ninput\nmode\ncompare_transfer\noutput\nmode\ncomparator\nCC1E\nwrite CCR1L\nCC1S[1]\nCC1S[0]\nOC1PE\nCapture/compare shadow register\ncapture\nS write CCR1H\nR\nR\ncapture_transfer\nCC1S[1]\n8\nread CCR1H S\n8\nMCU-peripheral interface\nOC1PE\nUEV\nTIM1_CCMR1\n(from time\nbase unit)\nCNT>CCR1\nCounter\nCC1G\nCNT=CCR1\nTIM1_EGR\nDoc ID 13902 Rev 14\n299/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 80. Output stage of capture/compare channel (channel 1 to 3)\nETR\n0\n‘0’\nOC1_DT\nCNT>CCR1\nOutput mode OC1REF\nCNT=CCR1\ncontroller\nDead-time\ngenerator\nx0\n10 1\n11 CC1P\nOutput\nenable\ncircuit OC1\nOutput\nenable\ncircuit OC1N\nTIM1_CCER\nOC1N_DT\n11\n0\n10\n‘0’\n0x\n1\nCC1NE CC1E TIM1_CCER\nOC1CE OC1M[2:0]\nTIM1_CCMR1\nDTG[7:0]\nCC1NE CC1E\nTIM1_BDTR\nTIM1_CCER\nCC1NP MOE OSSI OSSR TIM1_BDTR\nTIM1_CCER\nFigure 81. Output stage of capture/compare channel (channel 4)\nETR\nTo the master mode\ncontroller\n0\n1\nOutput\nenable\ncircuit\nOC4\nCC4P\nCNT > CCR4\nOutput mode OC4 REF\nCNT = CCR4 controller\nTIM1_CCER\nCC4E TIM1_CCER\nOC2M[2:0]\nMOE OSSI TIM1_BDTR\nTIM1_CCMR2\nOIS4 TIM1_CR2\nThe capture/compare block is made of one preload register and one shadow register. Write\nand read always access the preload register.\nIn capture mode, captures are actually done in the shadow register, which is copied into the\npreload register.\nIn compare mode, the content of the preload register is copied into the shadow register\nwhich is compared to the counter.\n14.3.6\nInput capture mode\nIn Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the\nvalue of the counter after a transition detected by the corresponding ICx signal. When a\ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or\na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was\nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be\ncleared by software by writing it to ‘0’ or by reading the captured data stored in the\nTIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.\n300/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1\ninput rises. To do this, use the following procedure:\n● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S\nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,\nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\n● Program the input filter duration you need with respect to the signal you connect to the\ntimer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s\nimagine that, when toggling, the input signal is not stable during at must 5 internal clock\ncycles. We must program a filter duration longer than these 5 clock cycles. We can\nvalidate a transition on TI1 when 8 consecutive samples with the new level have been\ndetected (sampled at f DTS frequency). Then write IC1F bits to 0011 in the\nTIMx_CCMR1 register.\n● Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in\nthe TIMx_CCER register (rising edge in this case).\n● Program the input prescaler. In our example, we wish the capture to be performed at\neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the\nTIMx_CCMR1 register).\n● Enable capture from the counter into the capture register by setting the CC1E bit in the\nTIMx_CCER register.\n● If needed, enable the related interrupt request by setting the CC1IE bit in the\nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the\nTIMx_DIER register.\nWhen an input capture occurs:\n● The TIMx_CCR1 register gets the value of the counter on the active transition.\n● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures\noccurred whereas the flag was not cleared.\n● An interrupt is generated depending on the CC1IE bit.\n● A DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the\novercapture flag. This is to avoid missing an overcapture which could happen after reading\nthe flag and before reading the data.\nNote: IC interrupt and/or DMA requests can be generated by software by setting the\ncorresponding CCxG bit in the TIMx_EGR register.\n14.3.7 PWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n● Two ICx signals are mapped on the same TIx input.\n● These 2 ICx signals are active on edges with opposite polarity.\n● One of the two TIxFP signals is selected as trigger input and the slave mode controller\nis configured in reset mode.\nDoc ID 13902 Rev 14\n301/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFor example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in\nTIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending\non CK_INT frequency and prescaler value):\n● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1\nregister (TI1 selected).\n● Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter\nclear): write the CC1P bit to ‘0’ (active on rising edge).\n● Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1\nregister (TI1 selected).\n● Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P\nbit to ‘1’ (active on falling edge).\n● Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register\n(TI1FP1 selected).\n● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the\nTIMx_SMCR register.\n● Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 82. PWM input mode timing\nTI1\nTIMx_CNT\n0004\n0000\n0001\n0002\nTIMx_CCR1 0004\nTIMx_CCR2 0002\nIC1 capture\nIC2 capture\nreset counter\n0003\n0004\nIC2 capture\npulse width\nmeasurement\n0000\nIC1 capture\nperiod\nmeasurement\nai15413\n1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only\nTI1FP1 and TI2FP2 are connected to the slave mode controller.\n14.3.8\nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal\n(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,\nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, you just need to write\n101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced\nhigh (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.\nFor example: CCxP=0 (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx\nregister.\n302/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still\nperformed and allows the flag to be set. Interrupt and DMA requests can be sent\naccordingly. This is described in the output compare mode section below.\n14.3.9\nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has\nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output\ncompare function:\n● Assigns the corresponding output pin to a programmable value defined by the output\ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP\nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set\nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n● Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the\nTIMx_DIER register).\n● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the\nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request\nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the\nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output.\nThe timing resolution is one count of the counter. Output compare mode can also be used to\noutput a single pulse (in One Pulse mode).\nProcedure:\n1.\nSelect the counter clock (internal, external, prescaler).\n2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. Set the CCxIE bit if an interrupt request is to be generated.\n4. Select the output mode. For example:\n5.\n– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx\n– Write OCxPE = 0 to disable preload register\n– Write CCxP = 0 to select active high polarity\n– Write CCxE = 1 to enable the output\nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\nThe TIMx_CCRx register can be updated at any time by software to control the output\nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx\nshadow register is updated only at the next update event UEV). An example is given in\nFigure 83.\nDoc ID 13902 Rev 14\n303/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 83. Output compare mode, toggle on OC1.\nWrite B201h in the CC1R register\nTIM1_CNT\nTIM1_CCR1\n0039\n003A\n003B\n003A\nB200\nB201\nB201\noc1ref=OC1\nMatch detected on CCR1\nInterrupt generated if enabled\n14.3.10\nPWM mode\nPulse Width Modulation mode allows you to generate a signal with a frequency determined\nby the value of the TIMx_ARR register and a duty cycle determined by the value of the\nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx\noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the\nTIMx_CCMRx register. You must enable the corresponding preload register by setting the\nOCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in\nupcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event\noccurs, before starting the counter, you have to initialize all the registers by setting the UG\nbit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It\ncan be programmed as active high or active low. OCx output is enabled by a combination of\nthe CCxE, CCxNE, MOE, OSSI and OSSR bits (TIMx_CCER and TIMx_BDTR registers).\nRefer to the TIMx_CCER register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine\nwhether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction\nof the counter).\nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode\ndepending on the CMS bits in the TIMx_CR1 register.\n304/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nPWM edge-aligned mode\n●\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to\nSection : Upcounting mode on page 286.\nIn the following example, we consider PWM mode 1. The reference PWM signal\nOCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the\ncompare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)\nthen OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.\nFigure 84 shows some edge-aligned PWM waveforms in an example where\nTIMx_ARR=8.\nFigure 84. Edge-aligned PWM waveforms (ARR=8)\nCounter register\nCCRx=4\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCRx=8\nCCxIF\nOCXREF ‘1’\nCCRx>8\nCCxIF\nOCXREF ‘0’\nCCRx=0\nCCxIF\n●\nDowncounting configuration\nDowncounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :\nDowncounting mode on page 289\nIn PWM mode 1, the reference signal OCxRef is low as long as\nTIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is\ngreater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM\nis not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from\n‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).\nThe compare flag is set when the counter counts up, when it counts down or both when it\ncounts up and down depending on the CMS bits configuration. The direction bit (DIR) in the\nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to\nSection : Center-aligned mode (up/down counting) on page 291.\nFigure 85 shows some center-aligned PWM waveforms in an example where:\n● TIMx_ARR=8,\n● PWM mode is the PWM mode 1,\n● The flag is set when the counter counts down corresponding to the center-aligned\nmode 1 selected for CMS=01 in TIMx_CR1 register.\nDoc ID 13902 Rev 14\n305/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 85. Center-aligned PWM waveforms (ARR=8)\n#OUNTER RM0008\n14.3.11\nAdvanced-control timers (TIM1&TIM8)\nComplementary outputs and dead-time insertion\nThe advanced-control timers (TIM1&TIM8) can output two complementary signals and\nmanage the switching-off and the switching-on instants of the outputs.\nThis time is generally known as dead-time and you have to adjust it depending on the\ndevices you have connected to the outputs and their characteristics (intrinsic delays of level-\nshifters, delays due to power switches...)\nYou can select the polarity of the outputs (main output OCx or complementary OCxN)\nindependently for each output. This is done by writing to the CCxP and CCxNP bits in the\nTIMx_CCER register.\nThe complementary signals OCx and OCxN are activated by a combination of several\ncontrol bits: the CCxE and CCxNE bits in the TIMx_CCER register and the MOE, OISx,\nOISxN, OSSI and OSSR bits in the TIMx_BDTR and TIMx_CR2 registers. Refer to Table 83:\nOutput control bits for complementary OCx and OCxN channels with break feature on\npage 340 for more details. In particular, the dead-time is activated when switching to the\nIDLE state (MOE falling down to 0).\nDead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the\nbreak circuit is present. There is one 10-bit dead-time generator for each channel. From a\nreference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are\nactive high:\n● The OCx output signal is the same as the reference signal except for the rising edge,\nwhich is delayed relative to the reference rising edge.\n● The OCxN output signal is the opposite of the reference signal except for the rising\nedge, which is delayed relative to the reference falling edge.\nIf the delay is greater than the width of the active output (OCx or OCxN) then the\ncorresponding pulse is not generated.\nThe following figures show the relationships between the output signals of the dead-time\ngenerator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,\nCCxE=1 and CCxNE=1 in these examples)\nFigure 86. Complementary output with dead-time insertion.\nOCxREF\nOCx\ndelay\nOCxN\ndelay\nFigure 87. Dead-time waveforms with delay greater than the negative pulse.\nOCxREF\nOCx\ndelay\nOCxN\nDoc ID 13902 Rev 14\n307/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 88. Dead-time waveforms with delay greater than the positive pulse.\nOCxREF\nOCx\nOCxN\ndelay\nThe dead-time delay is the same for each of the channels and is programmable with the\nDTG bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and dead-\ntime register (TIMx_BDTR) on page 344 for delay calculation.\nRe-directing OCxREF to OCx or OCxN\nIn output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx\noutput or to OCxN output by configuring the CCxE and CCxNE bits in the TIMx_CCER\nregister.\nThis allows you to send a specific waveform (such as PWM or static active level) on one\noutput while the complementary remains at its inactive level. Other alternative possibilities\nare to have both outputs at inactive level or both outputs active and complementary with\ndead-time.\nNote: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes\nactive as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the\nother hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes\nactive when OCxREF is high whereas OCxN is complemented and becomes active when\nOCxREF is low.\n14.3.12 Using the break function\nWhen using the break function, the output enable signals and inactive levels are modified\naccording to additional control bits (MOE, OSSI and OSSR bits in the TIMx_BDTR register,\nOISx and OISxN bits in the TIMx_CR2 register). In any case, the OCx and OCxN outputs\ncannot be set both to active level at a given time. Refer to Table 83: Output control bits for\ncomplementary OCx and OCxN channels with break feature on page 340 for more details.\nThe break source can be either the break input pin or a clock failure event, generated by the\nClock Security System (CSS), from the Reset Clock Controller. For further information on\nthe Clock Security System, refer to Section 7.2.7: Clock security system (CSS) on page 94.\nWhen exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable\nthe break function by setting the BKE bit in the TIMx_BDTR register. The break input\npolarity can be selected by configuring the BKP bit in the same register. BKE and BKP can\nbe modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB\nclock cycle is applied before the writing is effective. Consequently, it is necessary to wait 1\nAPB clock period to correctly read back the bit after the write operation.\nBecause MOE falling edge can be asynchronous, a resynchronization circuit has been\ninserted between the actual signal (acting on the outputs) and the synchronous control bit\n(accessed in the TIMx_BDTR register). It results in some delays between the asynchronous\nand the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you\n308/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nmust insert a delay (dummy instruction) before reading it correctly. This is because you write\nthe asynchronous signal and read the synchronous signal.\nWhen a break occurs (selected level on the break input):\nNote:\n● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state\nor in reset state (selected by the OSSI bit). This feature functions even if the MCU\noscillator is off.\n● Each output channel is driven with the level programmed in the OISx bit in the\nTIMx_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable\noutput else the enable output remains high.\n● When complementary outputs are used:\n– The outputs are first put in reset state inactive state (depending on the polarity).\nThis is done asynchronously so that it works even if no clock is provided to the\ntimer.\n– If the timer clock is still present, then the dead-time generator is reactivated in\norder to drive the outputs with the level programmed in the OISx and OISxN bits\nafter a dead-time. Even in this case, OCx and OCxN cannot be driven to their\nactive level together. Note that because of the resynchronization on MOE, the\ndead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).\n– If OSSI=0 then the timer releases the enable outputs else the enable outputs\nremain or become high as soon as one of the CCxE or CCxNE bits is high.\n● The break status flag (BIF bit in the TIMx_SR register) is set. An interrupt can be\ngenerated if the BIE bit in the TIMx_DIER register is set. A DMA request can be sent if\nthe BDE bit in the TIMx_DIER register is set.\n● If the AOE bit in the TIMx_BDTR register is set, the MOE bit is automatically set again\nat the next update event UEV. This can be used to perform a regulation, for instance.\nElse, MOE remains low until you write it to ‘1’ again. In this case, it can be used for\nsecurity and you can connect the break input to an alarm from power drivers, thermal\nsensors or any security components.\nThe break inputs is acting on level. Thus, the MOE cannot be set while the break input is\nactive (neither automatically nor by software). In the meantime, the status flag BIF cannot be\ncleared.\nThe break can be generated by the BRK input which has a programmable polarity and an\nenable bit BKE in the TIMx_BDTR Register.\nIn addition to the break input and the output management, a write protection has been\nimplemented inside the break circuit to safeguard the application. It allows you to freeze the\nconfiguration of several parameters (dead-time duration, OCx/OCxN polarities and state\nwhen disabled, OCxM configurations, break enable and polarity). You can choose from 3\nlevels of protection selected by the LOCK bits in the TIMx_BDTR register. Refer to\nSection 14.4.18: TIM1&TIM8 break and dead-time register (TIMx_BDTR) on page 344. The\nLOCK bits can be written only once after an MCU reset.\nFigure 89 shows an example of behavior of the outputs in response to a break.\nDoc ID 13902 Rev 14\n309/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 89. Output behavior in response to a break.\nBREAK (MOE\n)\nOCxREF\nOCx\n(OCxN not implemented, CCxP=0, OISx=1)\nOCx\n(OCxN not implemented, CCxP=0, OISx=0)\nOCx\n(OCxN not implemented, CCxP=1, OISx=1)\nOCx\n(OCxN not implemented, CCxP=1, OISx=0)\nOCx\ndelay\ndelay\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)\ndelay\nOCx\ndelay\ndelay\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)\ndelay\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)\ndelay\nOCx\nOCxN\n(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)\ndelay\nOCx\nOCxN\n(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)\n310/1096\nDoc ID 13902 Rev 14 RM0008\n14.3.13\nAdvanced-control timers (TIM1&TIM8)\nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be driven Low by applying a High level to the\nETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The\nOCxREF signal remains Low until the next update event, UEV, occurs.\nThis function can only be used in output compare and PWM modes, and does not work in\nforced mode.\nFor example, the OCxREF signal) can be connected to the output of a comparator to be\nused for current handling. In this case, the ETR must be configured as follow:\n1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR\nregister set to ‘00’.\n2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to\n‘0’.\n3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be\nconfigured according to the user needs.\nFigure 90 shows the behavior of the OCxREF signal when the ETRF Input becomes High,\nfor both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in\nPWM mode.\nFigure 90. Clearing TIMx OCxREF\n(CCRx)\ncounter (CNT)\nETRF\nOCxREF\n(OCxCE=’0’)\nOCxREF\n(OCxCE=’1’)\nOCREF_CLR\nbecomes high\nDoc ID 13902 Rev 14\nOCREF_CLR\nstill high\n311/1096 Advanced-control timers (TIM1&TIM8)\n14.3.14\nRM0008\n6-step PWM generation\nWhen complementary outputs are used on a channel, preload bits are available on the\nOCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the\nCOM commutation event. Thus you can program in advance the configuration for the next\nstep and change the configuration of all the channels at the same time. COM can be\ngenerated by software by setting the COM bit in the TIMx_EGR register or by hardware (on\nTRGI rising edge).\nA flag is set when the COM event occurs (COMIF bit in the TIMx_SR register), which can\ngenerate an interrupt (if the COMIE bit is set in the TIMx_DIER register) or a DMA request\n(if the COMDE bit is set in the TIMx_DIER register).\nFigure 91 describes the behavior of the OCx and OCxN outputs when a COM event occurs,\nin 3 different examples of programmed configurations.\nFigure 91. 6-step generation, COM example (OSSR=1)\ncounter (CNT)\n(CCRx)\nOCxREF\nWrite COM to 1\nCOM event\nExample 1\nCCxE=1\nwrite OCxM to 100\nCCxNE=0\nOCxM=100 (forced inactive) CCxE=1\nCCxNE=0\nOCxM=100\nWrite CCxNE to 1\nand OCxM to 101\nCCxE=1\nCCxNE=0\nOCxM=100 (forced inactive) CCxE=0\nCCxNE=1\nOCxM=101\nOCx\nOCxN\nOCx\nExample 2\nOCxN\nwrite CCxNE to 0\nCCxE=1\nand OCxM to 100\nCCxNE=0\nOCxM=100 (forced inactive)\nExample 3\nCCxE=1\nCCxNE=0\nOCxM=100\nOCx\nOCxN\nai14910\n312/1096\nDoc ID 13902 Rev 14 RM0008\nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to\nbe started in response to a stimulus and to generate a pulse with a programmable length\nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the\nwaveform can be done in output compare mode or PWM mode. You select One-pulse mode\nby setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically\nat the next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter\ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must\nbe:\n● In upcounting: CNT < CCRx ≤ ARR (in particular, 0 < CCRx)\n● In downcounting: CNT > CCRx\nFigure 92. Example of one pulse mode.\nTI2\nOC1REF\nOC1\n14.3.15\nAdvanced-control timers (TIM1&TIM8)\nTIM1_ARR\nTIM1_CCR1\n0\nt DELAY\nt PULSE\nt\nFor example you may want to generate a positive pulse on OC1 with a length of t PULSE and\nafter a delay of t DELAY as soon as a positive edge is detected on the TI2 input pin.\nLet’s use TI2FP2 as trigger 1:\n● Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n● TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.\n● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in\nthe TIMx_SMCR register.\n● TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register\n(trigger mode).\nDoc ID 13902 Rev 14\n313/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nThe OPM waveform is defined by writing the compare registers (taking into account the\nclock frequency and the counter prescaler).\n● The t DELAY is defined by the value written in the TIMx_CCR1 register.\n● The t PULSE is defined by the difference between the auto-reload value and the compare\nvalue (TIMx_ARR - TIMx_CCR1).\n● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare\nmatch occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload\nvalue. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1\nregister. You can optionally enable the preload registers by writing OC1PE=’1’ in the\nTIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to\nwrite the compare value in the TIMx_CCR1 register, the auto-reload value in the\nTIMx_ARR register, generate an update by setting the UG bit and wait for external\ntrigger event on TI2. CC1P is written to ‘0’ in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nYou only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1\nregister to stop the counter at the next update event (when the counter rolls over from the\nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the\nRepetitive Mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the\ncounter. Then the comparison between the counter and the compare value makes the\noutput toggle. But several clock cycles are needed for these operations and it limits the\nminimum delay t DELAY min we can get.\nIf you want to output a waveform with the minimum delay, you can set the OCxFE bit in the\nTIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,\nwithout taking in account the comparison. Its new level is the same as if a compare match\nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n14.3.16\nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the\ncounter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and\nSMS=’011’ if it is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER\nregister. When needed, you can program the input filter as well.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to\nTable 81. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2\nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,\nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in\nTIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated\nand generates count pulses as well as the direction signal. Depending on the sequence the\ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware\naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever\nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This\nmeans that the counter just counts continuously between 0 and the auto-reload value in the\nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must\nconfigure TIMx_ARR before starting. in the same way, the capture, compare, prescaler,\n314/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nrepetition counter, trigger output features continue to work as normal. Encoder mode and\nExternal clock mode 2 are not compatible and must not be selected together.\nIn this mode, the counter is modified automatically following the speed and the direction of\nthe incremental encoder and its content, therefore, always represents the encoder’s\nposition. The count direction correspond to the rotation direction of the connected sensor.\nThe table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the\nsame time.\nTable 81.\nCounting direction versus encoder signals\nActive edge\nLevel on\nopposite\nsignal (TI1FP1\nfor TI2, TI2FP2\nfor TI1)\nTI1FP1 signal\nTI2FP2 signal\nRising Falling Rising Falling\nCounting on\nTI1 only High Down Up No Count No Count\nLow Up Down No Count No Count\nCounting on\nTI2 only High No Count No Count Up Down\nLow No Count No Count Down Up\nCounting on\nTI1 and TI2 High Down Up Up Down\nLow Up Down Down Up\nAn external incremental encoder can be connected directly to the MCU without external\ninterface logic. However, comparators are normally be used to convert the encoder’s\ndifferential outputs to digital signals. This greatly increases noise immunity. The third\nencoder output which indicate the mechanical zero position, may be connected to an\nexternal interrupt input and trigger a counter reset.\nFigure 93 gives an example of counter operation, showing count signal generation and\ndirection control. It also shows how input jitter is compensated where both edges are\nselected. This might occur if the sensor is positioned near to one of the switching points. For\nthis example we assume that the configuration is the following:\n● CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).\n● CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).\n● CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).\n● CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).\n● SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling\nedges).\n● CEN=’1’ (TIMx_CR1 register, Counter enabled).\nDoc ID 13902 Rev 14\n315/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nFigure 93. Example of counter operation in encoder interface mode.\nforward\njitter\nbackward\njitter\nforward\nTI1\nTI2\nCounter\ndown\nup\nup\nFigure 94 gives an example of counter behavior when TI1FP1 polarity is inverted (same\nconfiguration as above except CC1P=’1’).\nFigure 94. Example of encoder interface mode with TI1FP1 polarity inverted.\nforward\njitter\nbackward\njitter\nforward\nTI1\nTI2\nCounter\ndown\nup\ndown\nThe timer, when configured in Encoder Interface mode provides information on the sensor’s\ncurrent position. You can obtain dynamic information (speed, acceleration, deceleration) by\nmeasuring the period between two encoder events using a second timer configured in\ncapture mode. The output of the encoder which indicates the mechanical zero can be used\nfor this purpose. Depending on the time between two events, the counter can also be read\nat regular times. You can do this by latching the counter value into a third input capture\nregister if available (then the capture signal must be periodic and can be generated by\nanother timer). when available, it is also possible to read its value through a DMA request\ngenerated by a real-time clock.\n316/1096\nDoc ID 13902 Rev 14 RM0008\n14.3.17\nAdvanced-control timers (TIM1&TIM8)\nTimer input XOR function\nThe TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to\nthe output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and\nTIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input\ncapture. An example of this feature used to interface Hall sensors is given in Section 14.3.18\nbelow.\n14.3.18\nInterfacing with Hall sensors\nThis is done using the advanced-control timers (TIM1 or TIM8) to generate PWM signals to\ndrive the motor and another timer TIMx (TIM2, TIM3, TIM4 or TIM5) referred to as\n“interfacing timer” in Figure 95. The “interfacing timer” captures the 3 timer input pins (CC1,\nCC2, CC3) connected through a XOR to the TI1 input channel (selected by setting the TI1S\nbit in the TIMx_CR2 register).\nThe slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,\neach time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a\ntime base triggered by any change on the Hall inputs.\nOn the “interfacing timer”, capture/compare channel 1 is configured in capture mode,\ncapture signal is TRC (see Figure 78: Capture/compare channel (example: channel 1 input\nstage) on page 299). The captured value, which corresponds to the time elapsed between 2\nchanges on the inputs, gives information about motor speed.\nThe “interfacing timer” can be used in output mode to generate a pulse which changes the\nconfiguration of the channels of the advanced-control timer (TIM1 or TIM8) (by triggering a\nCOM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do this,\nthe interfacing timer channel must be programmed so that a positive pulse is generated after\na programmed delay (in output compare or PWM mode). This pulse is sent to the advanced-\ncontrol timer (TIM1 or TIM8) through the TRGO output.\nExample: you want to change the PWM configuration of your advanced-control timer TIM1\nafter a programmed delay each time a change occurs on the Hall inputs connected to one of\nthe TIMx timers.\n● Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the\nTIMx_CR2 register to ‘1’,\n● Program the time base: write the TIMx_ARR to the max value (the counter must be\ncleared by the TI1 change. Set the prescaler to get a maximum counter period longer\nthan the time between 2 changes on the sensors,\n● Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the\nTIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed,\n● Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to\n‘111’ and the CC2S bits to ‘00’ in the TIMx_CCMR1 register,\n● Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\nregister to ‘101’,\nIn the advanced-control timer TIM1, the right ITR input must be selected as trigger input, the\ntimer is programmed to generate PWM signals, the capture/compare control signals are\npreloaded (CCPC=1 in the TIMx_CR2 register) and the COM event is controlled by the\ntrigger input (CCUS=1 in the TIMx_CR2 register). The PWM control bits (CCxE, OCxM) are\nDoc ID 13902 Rev 14\n317/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nwritten after a COM event for the next step (this can be done in an interrupt subroutine\ngenerated by the rising edge of OC2REF).\nFigure 95 describes this example.\nFigure 95. Example of hall sensor interface\nTIH1\nTIH2\nTIH3\ncounter (CNT)\n(CCR2)\nCCR1\nC7A3\nC7A8\nC794\nC7A5\nC7AB\nC796\nTRGO=OC2REF\nCOM\nOC1\nOC1N\nOC2\nOC2N\nOC3\nOC3N\nWrite CCxE, CCxNE\nand OCxM for next step\n318/1096\nai17335\nDoc ID 13902 Rev 14 RM0008\n14.3.19\nAdvanced-control timers (TIM1&TIM8)\nTIMx and external trigger synchronization\nThe TIMx timer can be synchronized with an external trigger in several modes: Reset mode,\nGated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input.\nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is\ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n● Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write\nCC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).\n● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n● Start the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising\nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the\ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA\nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.\nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the\nresynchronization circuit on TI1 input.\nFigure 96. Control circuit in reset mode\nTI1\nUG\nCounter clock = ck_cnt = ck_psc\nCounter register\n30 31 32 33 34 35 36 00 01 02 03 00 01 02 03\nTIF\nDoc ID 13902 Rev 14\n319/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write\nCC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).\n● Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n● Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the\ncounter doesn’t start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as\nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts\nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the\nresynchronization circuit on TI1 input.\nFigure 97. Control circuit in gated mode\nTI1\ncnt_en\nCounter clock = ck_cnt = ck_psc\nCounter register\n30 31 32 33\nTIF\nWrite TIF=0\n320/1096\nDoc ID 13902 Rev 14\n34\n35 36 37 38 RM0008\nAdvanced-control timers (TIM1&TIM8)\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC2F=0000). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are\nconfigured to select the input capture source only, CC2S=01 in TIMx_CCMR1 register.\nWrite CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level\nonly).\n● Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select\nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the\nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the\nresynchronization circuit on TI2 input.\nFigure 98. Control circuit in trigger mode\nTI2\ncnt_en\nCounter clock = ck_cnt = ck_psc\nCounter register\n34\n35 36 37 38\nTIF\nSlave mode: external clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external\nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock\ninput, and another input can be selected as trigger input (in reset mode, gated mode or\ntrigger mode). It is recommended not to select ETR as TRGI through the TS bits of\nTIMx_SMCR register.\nIn the following example, the upcounter is incremented at each rising edge of the ETR signal\nas soon as a rising edge of TI1 occurs:\n1.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as\nfollows:\n– ETF = 0000: no filter\n– ETPS=00: prescaler disabled\n– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock\nmode 2.\nDoc ID 13902 Rev 14\n321/1096 Advanced-control timers (TIM1&TIM8)\n2.\n3.\nRM0008\nConfigure the channel 1 as follows, to detect rising edges on TI:\n– IC1F=0000: no filter.\n– The capture prescaler is not used for triggering and does not need to be\nconfigured.\n– CC1S=01in TIMx_CCMR1 register to select only the input capture source\n– CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge\nonly).\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on\nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is\ndue to the resynchronization circuit on ETRP input.\nFigure 99. Control circuit in external clock mode 2 + trigger mode\nTI1\nCEN/CNT_EN\nETR\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35\n36\nTIF\n14.3.20\nTimer synchronization\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to\nSection 15.3.15: Timer synchronization on page 382 for details.\n14.3.21\nDebug mode\nWhen the microcontroller enters debug mode (Cortex™-M3 core halted), the TIMx counter\neither continues to work normally or stops, depending on DBG_TIMx_STOP configuration\nbit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,\nwatchdog, bxCAN and I2C.\n322/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4\nTIM1&TIM8 registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n14.4.1\nTIM1&TIM8 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\nCKD[1:0]\n7\n6\nARPE\n5\nCMS[1:0]\n4 3 2 1 0\nDIR OPM URS UDIS CEN\nrw rw rw rw rw\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD[1:0]: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the\ndead-time and sampling clock (t DTS )used by the dead-time generators and the digital filters\n(ETR, TIx),\n00: t DTS =t CK_INT\n01: t DTS =2*t CK_INT\n10: t DTS =4*t CK_INT\n11: Reserved, do not program this value\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS[1:0]: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit\n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as\nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder\nmode.\nBit 3 OPM: One pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\nDoc ID 13902 Rev 14\n323/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled.\nThese events can be:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if\nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value\n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is\nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been\npreviously set by software. However trigger mode can set the CEN bit automatically by\nhardware.\n14.4.2\nTIM1&TIM8 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n15\n14 13 12 11 10 9 8 7\nOIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S\nrw rw rw rw rw rw rw rw\n6\n5\n4\nMMS[2:0]\n3 2\nCCDS CCUS\nrw rw\nRes.\n0\nCCPC\nRes.\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 OIS4: Output Idle state 4 (OC4 output)\nrefer to OIS1 bit\nBit 13 OIS3N: Output Idle state 3 (OC3N output)\nrefer to OIS1N bit\nBit 12 OIS3: Output Idle state 3 (OC3 output)\nrefer to OIS1 bit\nBit 11 OIS2N: Output Idle state 2 (OC2N output)\nrefer to OIS1N bit\n324/1096\n1\nDoc ID 13902 Rev 14\nrw\nrw\nrw RM0008\nAdvanced-control timers (TIM1&TIM8)\nBit 10 OIS2: Output Idle state 2 (OC2 output)\nrefer to OIS1 bit\nBit 9 OIS1N: Output Idle state 1 (OC1N output)\n0: OC1N=0 after a dead-time when MOE=0\n1: OC1N=1 after a dead-time when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed\n(LOCK bits in TIMx_BDTR register).\nBit 8 OIS1: Output Idle state 1 (OC1 output)\n0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0\n1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0\nNote: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed\n(LOCK bits in TIMx_BDTR register).\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)\nBits 6:4 MMS[1:0]: Master mode selection\nThese bits allow to select the information to be sent in master mode to slave timers for\nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the\nreset is generated by the trigger input (slave mode controller configured in reset mode) then\nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO). It is\nuseful to start several timers at the same time or to control a window in which a slave timer is\nenable. The Counter Enable signal is generated by a logic OR between CEN control bit and\nthe trigger input when configured in gated mode. When the Counter Enable signal is\ncontrolled by the trigger input, there is a delay on TRGO, except if the master/slave mode is\nselected (see the MSM bit description in TIMx_SMCR register).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master\ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be\nset (even if it was already high), as soon as a capture or a compare match occurred.\n(TRGO).\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\nDoc ID 13902 Rev 14\n325/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBit 2 CCUS: Capture/compare control update selection\n0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting\nthe COMG bit only\n1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting\nthe COMG bit or when an rising edge occurs on TRGI\nNote: This bit acts only on channels that have a complementary output.\nBit 1 Reserved, must be kept at reset value.\nBit 0 CCPC: Capture/compare preloaded control\n0: CCxE, CCxNE and OCxM bits are not preloaded\n1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated\nonly when COM bit is set.\nNote: This bit acts only on channels that have a complementary output.\n326/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4.3\nTIM1&TIM8 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n15 14\nETP ECE\nrw rw\n13\n12\n11\nETPS[1:0]\nrw\nrw\n10\n9\n8\nETF[3:0]\nrw\nrw\n7\n6\nMSM\nrw\nrw\nrw\n5\n4\nTS[2:0]\nrw\nrw\n3\n2\nRes.\nrw\nRes.\n1\n0\nSMS[2:0]\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is non-inverted, active at high level or rising edge.\n1: ETR is inverted, active at low level or falling edge.\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF\nsignal.\nNote: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with\nTRGI connected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave\nmodes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be\nconnected to ETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time,\nthe external clock input is ETRF.\nBits 13:12 ETPS[1:0]: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A\nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external\nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\nDoc ID 13902 Rev 14\n327/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the\ndigital filter applied to ETRP. The digital filter is made of an event counter in which N events\nare needed to validate a transition on the output:\n0000: No filter, sampling is done at f DTS\n0001: f SAMPLING =f CK_INT , N=2\n0010: f SAMPLING =f CK_INT , N=4\n0011: f SAMPLING =f CK_INT , N=8\n0100: f SAMPLING =f DTS /2, N=6\n0101: f SAMPLING =f DTS /2, N=8\n0110: f SAMPLING =f DTS /4, N=6\n0111: f SAMPLING =f DTS /4, N=8\n1000: f SAMPLING =f DTS /8, N=6\n1001: f SAMPLING =f DTS /8, N=8\n1010: f SAMPLING =f DTS /16, N=5\n1011: f SAMPLING =f DTS /16, N=6\n1100: f SAMPLING =f DTS /16, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n1111: f SAMPLING =f DTS /32, N=8\nBit 7 MSM: Master/slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect\nsynchronization between the current timer and its slaves (through TRGO). It is useful if we\nwant to synchronize several timers on a single external event.\nBits 6:4 TS[2:0]: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 82: TIMx Internal trigger connection on page 329 for more details on ITRx meaning\nfor each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to\navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\n328/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to\nthe polarity selected on the external input (see Input Control register and Control Register\ndescription.\n000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal\nclock.\n001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1\nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2\nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges\ndepending on the level of the other input.\n100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter\nand generates an update of the registers.\n101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The\ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of\nthe counter are controlled.\n110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not\nreset). Only the start of the counter is controlled.\n111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input\n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the\ngated mode checks the level of the trigger signal.\nTable 82.\nTIMx Internal trigger connection (1)\nSlave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011)\nTIM1 TIM5 TIM2 TIM3 TIM4\nTIM8 TIM1 TIM2 TIM4 TIM5\n1. When a timer is not present in the product, the corresponding trigger ITRx is not available.\n14.4.4\nTIM1&TIM8 DMA/interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n15\n14\nTDE\n13\n12\n11\n10\n9\nCOMDE CC4DE CC3DE CC2DE CC1DE\n8 7 6 5 4 3 2 1 0\nUDE BIE TIE COMIE CC4IE CC3IE CC2IE CC1IE UIE\nrw rw rw rw rw rw rw rw rw\nRes.\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 Reserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled\n1: Trigger DMA request enabled\nBit 13 COMDE: COM DMA request enable\n0: COM DMA request disabled\n1: COM DMA request enabled\nDoc ID 13902 Rev 14\n329/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled\n1: CC4 DMA request enabled\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled\n1: CC3 DMA request enabled\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled\n1: CC2 DMA request enabled\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled\n1: CC1 DMA request enabled\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled\n1: Update DMA request enabled\nBit 7 BIE: Break interrupt enable\n0: Break interrupt disabled\n1: Break interrupt enabled\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled\n1: Trigger interrupt enabled\nBit 5 COMIE: COM interrupt enable\n0: COM interrupt disabled\n1: COM interrupt enabled\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled\n1: CC4 interrupt enabled\nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled\n1: CC3 interrupt enabled\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled\n1: CC2 interrupt enabled\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n330/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4.5\nTIM1&TIM8 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\nCC4OF CC3OF CC2OF CC1OF\n8 7 6 5 4 3 2 1 0\nRes. BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF\nRes. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0\nReserved\nrc_w0\nrc_w0\nrc_w0\nrc_w0\nBits 15:13 Reserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/Compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input\ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was\nalready set\nBit 8 Reserved, must be kept at reset value.\nBit 7 BIF: Break interrupt flag\nThis flag is set by hardware as soon as the break input goes active. It can be cleared by\nsoftware if the break input is not active.\n0: No break event occurred.\n1: An active level has been detected on the break input.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the\nslave mode controller is enabled in all modes but gated mode, both edges in case gated\nmode is selected). It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBit 5 COMIF: COM interrupt flag\nThis flag is set by hardware on COM event (when Capture/compare Control bits - CCxE,\nCCxNE, OCxM - have been updated). It is cleared by software.\n0: No COM event occurred.\n1: COM interrupt pending.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\nDoc ID 13902 Rev 14\n331/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/Compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some\nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register\ndescription). It is cleared by software.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.\nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF\nbit goes high on the counter overflow (in upcounting and up/down-counting modes) or\nunderflow (in downcounting mode)\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the\nTIMx_CCR1 register.\n0: No input capture occurred\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been\ndetected on IC1 which matches the selected polarity)\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–At overflow or underflow regarding the repetition counter value (update if repetition\ncounter = 0) and if the UDIS=0 in the TIMx_CR1 register.\n–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0\nand UDIS=0 in the TIMx_CR1 register.\n–When CNT is reinitialized by a trigger event (refer to Section 14.4.3: TIM1&TIM8 slave\nmode control register (TIMx_SMCR)), if URS=0 and UDIS=0 in the TIMx_CR1 register.\n14.4.6\nTIM1&TIM8 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7 6 5 4 3 2 1 0\nBG TG COMG CC4G CC3G CC2G CC1G UG\nw w w w w w w w\nReserved\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 BG: Break generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or\nDMA transfer can occur if enabled.\n332/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if\nenabled.\nBit 5 COMG: Capture/Compare control update generation\nThis bit can be set by software, it is automatically cleared by hardware\n0: No action\n1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits\nNote: This bit acts only on channels having a complementary output.\nBit 4 CC4G: Capture/Compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/Compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/Compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/Compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,\nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the\nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Reinitialize the counter and generates an update of the registers. Note that the prescaler\ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if\nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload\nvalue (TIMx_ARR) if DIR=1 (downcounting).\nDoc ID 13902 Rev 14\n333/1096 Advanced-control timers (TIM1&TIM8)\n14.4.7\nRM0008\nTIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The\ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other\nbits of this register have a different function in input and in output mode. For a given bit,\nOCxx describes its function when the channel is configured in output, ICxx describes its\nfunction when the channel is configured in input. So you must take care that the same bit\ncan have a different meaning for the input stage and for the output stage.\n15\n14\nOC2\nCE\n13\n12\nOC2M[2:0]\nIC2F[3:0]\nrw\nrw\nrw\n11 10\nOC2\nPE OC2\nFE\n9\n8\nCC2S[1:0]\n7\nIC2PSC[1:0]\nrw\nrw\nrw\n6\nOC1\nCE\n5\n4\nOC1M[2:0]\nIC1F[3:0]\nrw\nrw\nrw\nrw\nrw\n3 2\nOC1\nPE OC1\nFE\n1\n0\nCC1S[1:0]\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode:\nBit 15 OC2CE: Output Compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output Compare 2 mode\nBit 11 OC2PE: Output Compare 2 preload enable\nBit 10 OC2FE: Output Compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBit 7 OC1CE: Output Compare 1 clear enable\nOC1CE: Output Compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF Input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\n334/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nBits 6:4 OC1M: Output Compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and\nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on\nCC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the\ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing\nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter\nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the\ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1\nelse inactive. In downcounting, channel 1 is inactive (OC1REF=‘0’) as long as\nTIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1\nelse active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else\ninactive.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed\n(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in\noutput).\n2: In PWM mode 1 or 2, the OCREF level changes only when the result of the\ncomparison changes or when the output compare mode switches from “frozen” mode\nto “PWM” mode.\nBit 3 OC1PE: Output Compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the\nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload\nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed\n(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in\noutput).\n2: The PWM mode can be used without validating the preload register only in one\npulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.\nBit 2 OC1FE: Output Compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is\nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is\n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is\nset to the compare level independently from the result of the comparison. Delay to sample\nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if\nthe channel is configured in PWM1 or PWM2 mode.\nDoc ID 13902 Rev 14\n335/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an\ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = ‘0’ in TIMx_CCER).\nBits 7:4 IC1F[3:0]: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied\nto TI1. The digital filter is made of an event counter in which N events are needed to validate a\ntransition on the output:\n0000: No filter, sampling is done at f DTS\n0001: f SAMPLING =f CK_INT , N=2\n0010: f SAMPLING =f CK_INT , N=4\n0011: f SAMPLING =f CK_INT , N=8\n0100: f SAMPLING =f DTS /2, N=6\n0101: f SAMPLING =f DTS /2, N=8\n0110: f SAMPLING =f DTS /4, N=6\n0111: f SAMPLING =f DTS /4, N=8\n1000: f SAMPLING =f DTS /8, N=6\n1001: f SAMPLING =f DTS /8, N=8\n1010: f SAMPLING =f DTS /16, N=5\n1011: f SAMPLING =f DTS /16, N=6\n1100: f SAMPLING =f DTS /16, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n1111: f SAMPLING =f DTS /32, N=8\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\n336/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nBits 1:0 CC1S: Capture/Compare 1 Selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an\ninternal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = ‘0’ in TIMx_CCER).\n14.4.8\nTIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nReset value: 0x0000\nRefer to the above CCMR1 register description.\n15\n14\nOC4\nCE\n13\n12\nOC4M[2:0]\nIC4F[3:0]\nrw\nrw\nrw\n11 10\nOC4\nPE OC4\nFE\n9\n8\nCC4S[1:0]\n7\n6\nOC3\nCE.\nrw\nrw\n4\nOC3M[2:0]\nIC4PSC[1:0]\nrw\n5\nIC3F[3:0]\nrw\nrw\nrw\nrw\nrw\n3 2\nOC3\nPE OC3\nFE\n1\n0\nCC3S[1:0]\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\nDoc ID 13902 Rev 14\n337/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nInput capture mode\nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only\nif an internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = ‘0’ in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only\nif an internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = ‘0’ in TIMx_CCER).\n14.4.9\nTIM1&TIM8 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n15\n14\n13 12\nCC4P CC4E\nrw rw\n11\n10\nCC3NP CC3NE\n9 8\nCC3P CC3E\nrw rw\n7\n6\nCC2NP CC2NE\n5 4\nCC2P CC2E\nrw rw\n3\n2\nCC1NP CC1NE\n1 0\nCC1P CC1E\nrw rw\nReserved\nrw\nrw\nrw\nrw\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output polarity\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable\nrefer to CC1E description\nBit 11 CC3NP: Capture/Compare 3 complementary output polarity\nrefer to CC1NP description\nBit 10 CC3NE: Capture/Compare 3 complementary output enable\nrefer to CC1NE description\nBit 9 CC3P: Capture/Compare 3 output polarity\nrefer to CC1P description\nBit 8 CC3E: Capture/Compare 3 output enable\nrefer to CC1E description\n338/1096\nDoc ID 13902 Rev 14\nrw\nrw RM0008\nAdvanced-control timers (TIM1&TIM8)\nBit 7 CC2NP: Capture/Compare 2 complementary output polarity\nrefer to CC1NP description\nBit 6 CC2NE: Capture/Compare 2 complementary output enable\nrefer to CC1NE description\nBit 5 CC2P: Capture/Compare 2 output polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output polarity\n0: OC1N active high.\n1: OC1N active low.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits\nin TIMx_BDTR register) and CC1S=”00” (the channel is configured in output).\nBit 2 CC1NE: Capture/Compare 1 complementary output enable\n0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1, OIS1N\nand CC1E bits.\n1: On - OC1N signal is output on the corresponding output pin depending on MOE, OSSI,\nOSSR, OIS1, OIS1N and CC1E bits.\nBit 1 CC1P: Capture/Compare 1 output polarity\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nThis bit selects whether IC1 or IC1 is used for trigger or capture operations.\n0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1\nis non-inverted.\n1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is\ninverted.\nNote: This bit is not writable as soon as LOCK level 2 or 3 has been programmed (LOCK bits\nin TIMx_BDTR register).\nBit 0 CC1E: Capture/Compare 1 output enable\nCC1 channel configured as output:\n0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N\nand CC1NE bits.\n1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI,\nOSSR, OIS1, OIS1N and CC1NE bits.\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input\ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\nDoc ID 13902 Rev 14\n339/1096 Advanced-control timers (TIM1&TIM8)\nTable 83.\nRM0008\nOutput control bits for complementary OCx and OCxN channels with\nbreak feature\nOutput states (1)\nControl bits\nMOE\nbit\nOSSI\nbit\n1\n0\nOSSR\nbit CCxE\nbit\nCCxNE\nOCx output state\nbit\n0 0 0 Output Disabled (not driven by Output Disabled (not driven by the\nthe timer)\ntimer)\nOCx=0, OCx_EN=0\nOCxN=0, OCxN_EN=0\n0 0 1 Output Disabled (not driven by\nOCxREF + Polarity OCxN=OCxREF\nthe timer)\nxor CCxNP, OCxN_EN=1\nOCx=0, OCx_EN=0\n0 1 0 OCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\n0 1 1 Complementary to OCREF (not\nOCREF + Polarity + dead-time\nOCREF) + Polarity + dead-time\nOCx_EN=1\nOCxN_EN=1\n1 0 0 Output Disabled (not driven by Output Disabled (not driven by the\ntimer)\nthe timer)\nOCxN=CCxNP, OCxN_EN=0\nOCx=CCxP, OCx_EN=0\n1 0 1 Off-State (output enabled with\ninactive state)\nOCx=CCxP, OCx_EN=1\nOCxREF + Polarity\nOCxN=OCxREF xor CCxNP,\nOCxN_EN=1\n1 1 0 OCxREF + Polarity\nOCx=OCxREF xor CCxP,\nOCx_EN=1\nOff-State (output enabled with\ninactive state)\nOCxN=CCxNP, OCxN_EN=1\n1 1 1 Complementary to OCREF (not\nOCREF + Polarity + dead-time\nOCREF) + Polarity + dead-time\nOCx_EN=1\nOCxN_EN=1\n0 0 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1\nOCxN output state\nOutput Disabled (not driven by the\ntimer)\nOCxN=0, OCxN_EN=0\nX\n1\nX\nOutput Disabled (not driven by the timer)\nAsynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,\nOCxN_EN=0\nThen if the clock is present: OCx=OISx and OCxN=OISxN after a\ndead-time, assuming that OISx and OISxN do not correspond to OCX\nand OCxN both in active state.\nOff-State (output enabled with inactive state)\nAsynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,\nOCxN_EN=1\nThen if the clock is present: OCx=OISx and OCxN=OISxN after a\ndead-time, assuming that OISx and OISxN do not correspond to OCX\nand OCxN both in active state\n1. When both outputs of a channel are not used (CCxE = CCxNE = 0), the OISx, OISxN, CCxP and CCxNP bits must be kept\ncleared.\nNote:\n340/1096\nThe state of the external I/O pins connected to the complementary OCx and OCxN\nchannels depends on the OCx and OCxN channel state and the GPIO and AFIO registers.\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4.10\nTIM1&TIM8 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCNT[15:0]\nrw\nrw\nrw\nBits 15:0\n14.4.11\nrw\nrw\nrw\nrw\nrw\nrw\nCNT[15:0]: Counter value\nTIM1&TIM8 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7\nPSC[15:0]\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency (CK_CNT) is equal to f CK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event\n(including when the counter is cleared through UG bit of TIMx_EGR register or through\ntrigger controller when configured in “reset mode”).\n14.4.12\nTIM1&TIM8 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Prescaler value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 14.3.1: Time-base unit on page 285 for more details about ARR update\nand behavior.\nThe counter is blocked while the auto-reload value is null.\nDoc ID 13902 Rev 14\n341/1096 Advanced-control timers (TIM1&TIM8)\n14.4.13\nRM0008\nTIM1&TIM8 repetition counter register (TIMx_RCR)\nAddress offset: 0x30\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2 1 0\nrw rw rw\nREP[7:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBits 7:0 REP[7:0]: Repetition counter value\nThese bits allow the user to set-up the update rate of the compare registers (i.e. periodic\ntransfers from preload to active registers) when preload registers are enable, as well as the\nupdate interrupt generation rate, if this interrupt is enable.\nEach time the REP_CNT related downcounter reaches zero, an update event is generated\nand it restarts counting from REP value. As REP_CNT is reloaded with REP value only at\nthe repetition update event U_RC, any write to the TIMx_RCR register is not taken in\naccount until the next repetition update event.\nIt means in PWM mode (REP+1) corresponds to:\n–\nthe number of PWM periods in edge-aligned mode\n–\nthe number of half PWM period in center-aligned mode.\n14.4.14\nTIM1&TIM8 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR1[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register\n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signaled on OC1 output.\nIf channel CC1 is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1).\n342/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4.15\nTIM1&TIM8 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR2[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register\n(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2).\n14.4.16\nTIM1&TIM8 capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR3[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR3[15:0]: Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register\n(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC3 output.\nIf channel CC3 is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3).\nDoc ID 13902 Rev 14\n343/1096 Advanced-control timers (TIM1&TIM8)\n14.4.17\nRM0008\nTIM1&TIM8 capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR4[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR4[15:0]: Capture/Compare value\nIf channel CC4 is configured as output:\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register\n(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC4 output.\nIf channel CC4 is configured as input:\nCCR4 is the counter value transferred by the last input capture 4 event (IC4).\n14.4.18\nTIM1&TIM8 break and dead-time register (TIMx_BDTR)\nAddress offset: 0x44\nReset value: 0x0000\n15 14 13 12 11 10\nMOE AOE BKP BKE OSSR OSSI\nrw rw rw rw rw rw\nNote:\n9\n8\n7\n6\n5\nLOCK[1:0]\nrw\nrw\n4\n3\n2 1 0\nrw rw rw\nDTG[7:0]\nrw\nrw\nrw\nrw\nrw\nAs the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on\nthe LOCK configuration, it can be necessary to configure all of them during the first write\naccess to the TIMx_BDTR register.\nBit 15 MOE: Main output enable\nThis bit is cleared asynchronously by hardware as soon as the break input is active. It is set\nby software or automatically depending on the AOE bit. It is acting only on the channels\nwhich are configured in output.\n0: OC and OCN outputs are disabled or forced to idle state.\n1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in\nTIMx_CCER register).\nSee OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8\ncapture/compare enable register (TIMx_CCER) on page 338).\nBit 14 AOE: Automatic output enable\n0: MOE can be set only by software\n1: MOE can be set by software or automatically at the next update event (if the break input is\nnot be active)\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits\nin TIMx_BDTR register).\n344/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\nBit 13 BKP: Break polarity\n0: Break input BRK is active low\n1: Break input BRK is active high\nNote: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits\nin TIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 12 BKE: Break enable\n0: Break inputs (BRK and CCS clock failure event) disabled\n1; Break inputs (BRK and CCS clock failure event) enabled\nNote: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in\nTIMx_BDTR register).\nNote: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective.\nBit 11 OSSR: Off-state selection for Run mode\nThis bit is used when MOE=1 on channels having a complementary output which are\nconfigured as outputs. OSSR is not implemented if no complementary output is implemented\nin the timer.\nSee OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8\ncapture/compare enable register (TIMx_CCER) on page 338).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1\nor CCxNE=1. Then, OC/OCN enable output signal=1\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK\nbits in TIMx_BDTR register).\nBit 10 OSSI: Off-state selection for Idle mode\nThis bit is used when MOE=0 on channels configured as outputs.\nSee OC/OCN enable description for more details (Section 14.4.9: TIM1&TIM8\ncapture/compare enable register (TIMx_CCER) on page 338).\n0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).\n1: When inactive, OC/OCN outputs are forced first with their idle level as soon as CCxE=1 or\nCCxNE=1. OC/OCN enable output signal=1)\nNote: This bit can not be modified as soon as the LOCK level 2 has been programmed (LOCK\nbits in TIMx_BDTR register).\nBits 9:8 LOCK[1:0]: Lock configuration\nThese bits offer a write protection against software errors.\n00: LOCK OFF - No bit is write protected.\n01: LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2\nregister and BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.\n10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER\nregister, as long as the related channel is configured in output through the CCxS bits) as well\nas OSSR and OSSI bits can no longer be written.\n11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in\nTIMx_CCMRx registers, as long as the related channel is configured in output through the\nCCxS bits) can no longer be written.\nNote: The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register\nhas been written, their content is frozen until the next reset.\nDoc ID 13902 Rev 14\n345/1096 Advanced-control timers (TIM1&TIM8)\nRM0008\nBits 7:0 DTG[7:0]: Dead-time generator setup\nThis bit-field defines the duration of the dead-time inserted between the complementary\noutputs. DT correspond to this duration.\nDTG[7:5]=0xx => DT=DTG[7:0]x t dtg with t dtg =t DTS .\nDTG[7:5]=10x => DT=(64+DTG[5:0])xt dtg with T dtg =2xt DTS .\nDTG[7:5]=110 => DT=(32+DTG[4:0])xt dtg with T dtg =8xt DTS .\nDTG[7:5]=111 => DT=(32+DTG[4:0])xt dtg with T dtg =16xt DTS .\nExample if T DTS =125ns (8MHz), dead-time possible values are:\n0 to 15875 ns by 125 ns steps,\n16 us to 31750 ns by 250 ns steps,\n32 us to 63us by 1 us steps,\n64 us to 126 us by 2 us steps\nNote: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed\n(LOCK bits in TIMx_BDTR register).\n14.4.19\nTIM1&TIM8 DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\nDBL[4:0]\n2\n1 0\nrw rw\nDBA[4:0]\nReserved\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer\nwhen a read or a write access is done t\nthe TIMx_DMAR address)\n00000: 1 transfer\n00001: 2 transfers\n00010: 3 transfers\n...\n10001: 18 transfers\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bits vector defines the base-address for DMA transfers (when read/write access are\ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the\naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers and DBA = TIMx_CR1. In\nthis case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.\n346/1096\nDoc ID 13902 Rev 14 RM0008\nAdvanced-control timers (TIM1&TIM8)\n14.4.20\nTIM1&TIM8 DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nDMAB[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 DMAB[15:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4\nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base\naddress configured in TIMx_DCR register, DMA index is automatically controlled by the\nDMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx\nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.\nThis is done in the following steps:\n1.\nNote:\nConfigure the corresponding DMA channel as follows:\n– DMA channel peripheral address is the DMAR register address\n– DMA channel memory address is the address of the buffer in the RAM containing\nthe data to be transferred by DMA into CCRx registers.\n– Number of data to transfer = 3 (See note below).\n– Circular mode disabled.\n2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:\nDBL = 3 transfers, DBA = 0xE.\n3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).\n4. Enable TIMx\n5. Enable the DMA channel\nThis example is for the case where every CCRx register to be updated once. If every CCRx\nregister is to be updated twice for example, the number of data to transfer should be 6. Let's\ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and\ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA\nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to\nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is\ntransferred to CCR3 and data6 is transferred to CCR4.\nDoc ID 13902 Rev 14\n347/1096 Advanced-control timers (TIM1&TIM8)\n14.4.21\nRM0008\nTIM1&TIM8 register map\nTIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table\nbelow:\nTIM1&TIM8 register map and reset values\nTIMx_CNT\nTIMx_PSC\nTIMx_ARR\nTIMx_RCR\n0 0 0 0\n0 0 0 0\n0\n0\nOC4M\n[2:0]\nReserved\n0 0\n0\n0\nOC2FE\n0 CC1S\n[1:0]\nOC1M\n[2:0]\n0 0 0 0 0 0 0 0\nIC2\nCC2S\nPSC\nIC1F[3:0]\n[1:0]\n[1:0]\n0 0 0 0 0 0 0 0\nCC4S\n[1:0]\nOC3M\n[2:0]\n0 0 0 0 0\n0\n0\n0 0 0 0\nIC1\nCC1S\nPSC\n[1:0]\n[1:0]\n0 0 0 0\nCC3S\n[1:0]\n0 0 0 0\nIC3\nCC3S\nPSC\n[1:0]\n[1:0]\n0 0 0 0\n0\n0\n0\n0 0 0 0 0 0 0 0 0\nIC4\nCC4S\nPSC\nIC3F[3:0]\n[1:0]\n[1:0]\n0 0 0 0 0 0 0 0\nIC4F[3:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\n0\n0\n0\n0\n0\n0\n0\nCC2S\n[1:0]\n0\n0\nOC2M\n[2:0]\n0 0 0 0 0\n0 0 0 0 0\nSMS[2:0]\n0\nTS[2:0]\n0\nIC2F[3:0]\nReserved\n0 0 0 0 0 0 0 0 0\nCNT[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\n0 0 0\nPSC[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nARR[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nREP[7:0]\nReserved\nReset value\n348/1096\n0 0\n0\nReset value\n0x30\n0 0\nReserved\nReset value\n0x2C\n0 0\nETF[3:0]\nReserved\nReset value\n0x28\n0 0\nReserved\n0\n0 0\nReset value\n0x24\n0\n0\nTIMx_CCER\n0\n0\n0x20\n0\n0x1C\n0 0\n0x18\nReset value\nTIMx_CCMR1\nOutput Compare\nmode\nReset value\nTIMx_CCMR1\nInput Capture\nmode\nReset value\nTIMx_CCMR2\nOutput Compare\nmode\nReset value\nTIMx_CCMR2\nInput Capture\nmode\nReset value\n0 0\n0\nReserved\nTIMx_EGR\n0 0\nReset value\n0x14\nMMS[2:0] 0\nOC2PE\nTIMx_SR\n0\n0\nReset value\n0x10\n0 ETPS\n[1:0]\nTIMx_DIER\n0x0C\n0\nReset value\n0\nReserved\n0\n0\nTIMx_SMCR\n0\n0 0\nReset value\n0x08\n0\nReserved\n0 0\nTIMx_CR2\n0x04\nReset value\nCMS\n[1:0] CKD\n[1:0]\nReserved\nTIMx_CR1\n0x00\nRegister\nOffset\n30\nTable 84.\n0\nDoc ID 13902 Rev 14\n0\n0\n0\n0 RM0008\nAdvanced-control timers (TIM1&TIM8)\nReset value\nTIMx_CCR2\n0\nTIMx_CCR3\n0\n0\n0\n0\nTIMx_BDTR 0 0\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0\nLOCK\n[1:0]\n0 0 0 0 0\n0\n0\nDBL[4:0]\nReserved\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0\nDT[7:0]\n0\n0\n0\n0\nDBA[4:0]\nReserved\n0\n0\n0 0 0 0 0\n0 0 0 0 0\nDMAB[15:0]\nReserved\nReset value\n0\nCCR4[15:0]\n0\nTIMx_DMAR\n0\nReserved\nReset value\n0x4C\n0\nCCR3[15:0]\nReset value\nTIMx_DCR\n0\nReserved\nReset value\n0x48\n0\n0x44\nTIMx_CCR4\n0\nCCR2[15:0]\n0\nReset value\n0x40\n0\nReserved\nReset value\n0x3C\n0\n0x38\nCCR1[15:0]\nReserved\nTIMx_CCR1\n0x34\nRegister\nOffset\nTIM1&TIM8 register map and reset values (continued)\nTable 84.\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n349/1096 General-purpose timers (TIM2 to TIM5)\n15\nRM0008\nGeneral-purpose timers (TIM2 to TIM5)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis Section applies to the whole STM32F10xxx family, unless otherwise specified.\n15.1\nTIM2 to TIM5 introduction\nThe general-purpose timers consist of a 16-bit auto-reload counter driven by a\nprogrammable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input\nsignals (input capture) or generating output waveforms (output compare and PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several\nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe timers are completely independent, and do not share any resources. They can be\nsynchronized together as described in Section 15.3.15.\n350/1096\nDoc ID 13902 Rev 14 RM0008\n15.2\nGeneral-purpose timers (TIM2 to TIM5)\nTIMx main features\nGeneral-purpose TIMx timer features include:\n● 16-bit up, down, up/down auto-reload counter.\n● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock\nfrequency by any factor between 1 and 65535.\n● Up to 4 independent channels for:\n– Input capture\n– Output compare\n– PWM generation (Edge- and Center-aligned modes)\n– One-pulse mode output\n● Synchronization circuit to control the timer with external signals and to interconnect\nseveral timers.\n● Interrupt/DMA generation on the following events:\n– Update: counter overflow/underflow, counter initialization (by software or\ninternal/external trigger)\n– Trigger event (counter start, stop, initialization or count by internal/external trigger)\n– Input capture\n– Output compare\n● Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning\npurposes\n● Trigger input for external clock or cycle-by-cycle current management\nDoc ID 13902 Rev 14\n351/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 100. General-purpose timer block diagram\nInternal Clock (CK_INT)\nTIMxCLK from RCC\nETRF\nETRP\nETR\nTIMx_ETR\nPolarity selection & edge\ndetector & prescaler\nInput filter\nTRGO\nITR0\nITR1\nTGI\nITR\nITR2\nTRC\nTRGI\nITR3\nTI1F_ED\nTI1FP1\nTrigger\ncontroller\nSlave\nmode\ncontroller\nU\nAutoreload register\nStop, clear or up/down\nPSC\nCK_CNT\nPrescaler\nTI1\nInput filter &\nedge detector\nTI1FP1\nTI1FP2\nIC1\nPrescaler\nTRC\nTIMx_CH1\nTI2\nTIMx_CH2\nInput filter &\nedge detector\nTI2FP1\nTI2FP2\nIC1PS U\ncounter\nCC1I\nCapture/compare 1 register\nOC1REF\noutput\nOC1\ncontrol\nCC2I\nIC2\nUI\nU\nCNT\n+/-\nCC1I\nXOR\nReset, enable, up/down, count,\nEncoder\nInterface\nTI2FP2\nCK_PSC\nto other timers\nto DAC/ADC\nCC2I\nIC2PS U\nPrescaler\nTIMx_CH1\nCapture/compare 2 register\nOC2REF\noutput\nOC2\ncontrol\nTIMx_CH2\nTRC\nCC3I\nTI3\nTIMx_CH3\nInput filter &\nedge detector\nTI3FP3\nTI3FP4\nIC3\nPrescaler\nTRC\nTI4\nTIMx_CH4\nInput filter &\nedge detector\nTI4FP3\nTI4FP4\nIC3PS\nCC3I\nU\nCapture/compare 3 register\nCC4I\nIC4\nIC4PS\nPrescaler\nOC3REF\noutput\nOC3\nTIMx_CH3\ncontrol\nCC4I\nU\nCapture/compare 4 register\nOC4REF\noutput\ncontrol\nOC4\nTIMx_CH4\nTRC\nETRF\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nevent\ninterrupt & DMA output\n15.3 TIMx functional description\n15.3.1 Time-base unit\nThe main block of the programmable timer is a 16-bit counter with its related auto-reload\nregister. The counter can count up, down or both up and down. The counter clock can be\ndivided by a prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by\nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n352/1096\n● Counter Register (TIMx_CNT)\n● Prescaler Register (TIMx_PSC):\n● Auto-Reload Register (TIMx_ARR)\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register\naccesses the preload register. The content of the preload register are transferred into the\nshadow register permanently or at each update event (UEV), depending on the auto-reload\npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter\nreaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the\nTIMx_CR1 register. It can also be generated by software. The generation of the update\nevent is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the\ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller\ndescription to get more details on counter enabling).\nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It\nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).\nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is\ntaken into account at the next update event.\nFigure 101 and Figure 102 give some examples of the counter behavior when the prescaler\nratio is changed on the fly:\nFigure 101. Counter timing diagram with prescaler division change from 1 to 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\n02\n03\nUpdate event (UEV)\nPrescaler control register\n0\n1\nWrite a new value in TIMx_PSC\nPrescaler buffer 0\nPrescaler counter 0\nDoc ID 13902 Rev 14\n1\n0\n1\n0\n1\n0\n1\n0\n1\n353/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 102. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\nUpdate event (UEV)\nPrescaler control register\n0\n3\nWrite a new value in TIMx_PSC\n15.3.2\nPrescaler buffer 0\nPrescaler counter 0\n3\n0\n1\n2\n3\n0\n1\n2\n3\nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the\nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nAn Update event can be generated at each counter overflow or by setting the UG bit in the\nTIMx_EGR register (by software or by using the slave mode controller).\nThe UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.\nThis is to avoid updating the shadow registers while writing new values in the preload\nregisters. Then no update event occurs until the UDIS bit has been written to 0. However,\nthe counter restarts from 0, as well as the counter of the prescaler (but the prescale rate\ndoes not change). In addition, if the URS bit (update request selection) in TIMx_CR1\nregister is set, setting the UG bit generates an update event UEV but without setting the UIF\nflag (thus no interrupt or DMA request is sent). This is to avoid generating both update and\ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister)\n● The auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR=0x36.\n354/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 103. Counter timing diagram, internal clock divided by 1\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n32 33 34 35 36 00 01 02 03 04 05 06 07\n31\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 104. Counter timing diagram, internal clock divided by 2\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035 0036\n0000\n0001\n0002\n0003\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 105. Counter timing diagram, internal clock divided by 4\nCK_INT\nCNT_EN\nTImer clock = CK_CNT\nCounter register\n0035\n0036\n0000\n0001\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n355/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 106. Counter timing diagram, internal clock divided by N\nCK_INT\nTimer clock = CK_CNT\nCounter register\n1F\n00\n20\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not\npreloaded)\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\nWrite a new value in TIMx_ARR\n356/1096\nDoc ID 13902 Rev 14\n36 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR\npreloaded)\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF0\nF1 F2 F3 F4 F5 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register F5 36\nAuto-reload shadow register F5 36\nWrite a new value in TIMx_ARR\nDowncounting mode\nIn downcounting mode, the counter counts from the auto-reload value (content of the\nTIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a\ncounter underflow event.\nAn Update event can be generate at each counter underflow or by setting the UG bit in the\nTIMx_EGR register (by software or by using the slave mode controller)\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\npreload registers. Then no update event occurs until UDIS bit has been written to 0.\nHowever, the counter restarts from the current auto-reload value, whereas the counter of the\nprescaler restarts from 0 (but the prescale rate doesn’t change).\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the\nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or\nDMA request is sent). This is to avoid generating both update and capture interrupts when\nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister).\n● The auto-reload active register is updated with the preload value (content of the\nTIMx_ARR register). Note that the auto-reload is updated before the counter is\nreloaded, so that the next period is the expected one.\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR=0x36.\nDoc ID 13902 Rev 14\n357/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 109. Counter timing diagram, internal clock divided by 1\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n04 03 02 01 00 36 35 34 33 32 31 30 2F\n05\nCounter underflow (cnt_udf)\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 110. Counter timing diagram, internal clock divided by 2\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0002\n0001 0000\n0036\n0035\n0034\n0033\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 111. Counter timing diagram, internal clock divided by 4\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0001\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n358/1096\nDoc ID 13902 Rev 14\n0000\n0036\n0035 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 112. Counter timing diagram, internal clock divided by N\nCK_INT\nTimer clock = CK_CNT\nCounter register\n20\n1F\n00\n36\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 113. Counter timing diagram, Update event when repetition counter\nis not used\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n05\n04 03 02 01 00 36 35 34 33 32 31 30 2F\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\n36\nWrite a new value in TIMx_ARR\nCenter-aligned mode (up/down counting)\nIn center-aligned mode, the counter counts from 0 to the auto-reload value (content of the\nTIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-\nreload value down to 1 and generates a counter underflow event. Then it restarts counting\nfrom 0.\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to\n'00'. The Output compare interrupt flag of channels configured in output is set when: the\ncounter counts down (Center aligned mode 1, CMS = \"01\"), the counter counts up (Center\naligned mode 2, CMS = \"10\") the counter counts up and down (Center aligned mode 3,\nCMS = \"11\").\nIn this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated\nby hardware and gives the current direction of the counter.\nThe update event can be generated at each counter overflow and at each counter underflow\nor by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode\ncontroller) also generates an update event. In this case, the counter restarts counting from\n0, as well as the counter of the prescaler.\nDoc ID 13902 Rev 14\n359/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nThe UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\npreload registers. Then no update event occurs until the UDIS bit has been written to 0.\nHowever, the counter continues counting up and down, based on the current auto-reload\nvalue.\nIn addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the\nUG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or\nDMA request is sent). This is to avoid generating both update and capture interrupt when\nclearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister).\n● The auto-reload active register is updated with the preload value (content of the\nTIMx_ARR register). Note that if the update source is a counter overflow, the auto-\nreload is updated before the counter is reloaded, so that the next period is the expected\none (the counter is loaded with the new value).\nThe following figures show some examples of the counter behavior for different clock\nfrequencies.\nFigure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n04\n03 02 01 00 01 02 03 04 05 06 05 04 03\nCounter underflow\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n1.\n360/1096\nHere, center-aligned mode 1 is used (for more details refer to Section 15.4.1: TIMx control register 1 (TIMx_CR1) on\npage 388).\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 115. Counter timing diagram, internal clock divided by 2\nCK_INT\nCNT_EN\nTImer clock = CK_CNT\nCounter register\n0003\n0002 0001\n0000\n0001\n0002\n0003\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035\n0036\n0035\nCounter overflow (cnt_ovf)\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n1.\nCenter-aligned mode 2 or 3 is used with an UIF on overflow.\nFigure 117. Counter timing diagram, internal clock divided by N\nCK_INT\nTimer clock = CK_CNT\nCounter register\n20\n1F\n01\n00\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n361/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow)\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n06\n05 04 03 02 01 00 01 02 03 04 05 06 07\nCounter underflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register\nFD\n36\nWrite a new value in TIMx_ARR\nAuto-reload active register\nFD\n36\nFigure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow)\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC 36 35 34 33 32 31 30 2F\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register\nFD\n36\nWrite a new value in TIMx_ARR\nAuto-reload active register\n362/1096\nFD\nDoc ID 13902 Rev 14\n36 RM0008\n15.3.3\nGeneral-purpose timers (TIM2 to TIM5)\nClock selection\nThe counter clock can be provided by the following clock sources:\n● Internal clock (CK_INT)\n● External clock mode1: external input pin (TIx)\n● External clock mode2: external trigger input (ETR)\n● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for\nexample, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to : Using\none timer as prescaler for another on page 382 for more details.\nInternal clock source (CK_INT)\nIf the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the\nCEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual\ncontrol bits and can be changed only by software (except UG which remains cleared\nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal\nclock CK_INT.\nFigure 120 shows the behavior of the control circuit and the upcounter in normal mode,\nwithout prescaler.\nFigure 120. Control circuit in normal mode, internal clock divided by 1\nCK_INT\nCEN=CNT_EN\nUG\nCNT_INIT\nCounter clock = CK_CNT = CK_PSC\nCOUNTER REGISTER\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nExternal clock source mode 1\nThis mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count\nat each rising or falling edge on a selected input.\nDoc ID 13902 Rev 14\n363/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 121. TI2 external clock connection example\nTIMx_SMCR\nTS[2:0]\nor\nITRx\nTI2\nFilter\nEdge\nDetector\nTI1FP1 101\nTI2FP2 110\nETRF 111\nCC2P\nICF[3:0]\nTIMx_CCMR1\nTIMx_CCER\nor\nor\nencoder\nmode\n001\nTI1F_ED 100\nTI2F_Rising\n0\nTI2F_Falling\n1\nTI2F\nTI1F\nTRGI external clock\nmode 1\nETRF external clock\nmode 2\nCK_INT internal clock\nmode\n(internal clock)\nCK_PSC\nECE SMS[2:0]\nTIMx_SMCR\nFor example, to configure the upcounter to count in response to a rising edge on the TI2\ninput, use the following procedure:\nFor example, to configure the upcounter to count in response to a rising edge on the TI2\ninput, use the following procedure:\nNote:\n1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the\nTIMx_CCMR1 register.\n2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1\nregister (if no filter is needed, keep IC2F=0000).\nThe capture prescaler is not used for triggering, so you don’t need to configure it.\n3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.\n4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR\nregister.\n5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.\n6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the\nresynchronization circuit on TI2 input.\nFigure 122. Control circuit in external clock mode 1\nTI2\nCNT_EN\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35\nTIF\nWrite TIF=0\n364/1096\nDoc ID 13902 Rev 14\n36 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nExternal clock source mode 2\nThis mode is selected by writing ECE=1 in the TIMx_SMCR register.\nThe counter can count at each rising or falling edge on the external trigger input ETR.\nFigure 123 gives an overview of the external trigger input block.\nFigure 123. External trigger input block\nor\nTI2F\nTI1F\nor\nor\nencoder\nmode\nexternal clock\nmode 1\nTRGI\nETR pin\nETR\n0\n1\ndivider\n/1, /2, /4, /8\nETRP\nCK_INT\nfilter\ndowncounter\nETRF external clock\nmode 2\nCK_INT internal clock\nmode\n(internal clock)\nETP\nTIMx_SMCR\nETPS[1:0]\nCK_PSC\nETF[3:0]\nTIMx_SMCR\nTIMx_SMCR\nECE SMS[2:0]\nTIMx_SMCR\nFor example, to configure the upcounter to count each 2 rising edges on ETR, use the\nfollowing procedure:\n1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.\n2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register\n3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR\nregister\n4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.\n5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter counts once each 2 ETR rising edges.\nThe delay between the rising edge on ETR and the actual clock of the counter is due to the\nresynchronization circuit on the ETRP signal.\nFigure 124. Control circuit in external clock mode 2\nCK_INT\nCNT_EN\nETR\nETRP\nETRF\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\nDoc ID 13902 Rev 14\n35\n36\n365/1096 General-purpose timers (TIM2 to TIM5)\n15.3.4\nRM0008\nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a\nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and\nan output stage (with comparator and output control).\nThe following figure gives an overview of one Capture/Compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF.\nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be\nused as trigger input by the slave mode controller or as the capture command. It is\nprescaled before the capture register (ICxPS).\nFigure 125. Capture/compare channel (example: channel 1 input stage)\nTI1F_ED\nto the slave mode controller\nTI1\nf DTS\nfilter\ndowncounter\nTI1F\nTI1F_Rising\nEdge\nDetector\nTI1F_Falling\n0\nTI1FP1\n1\nCC1P\nICF[3:0]\nTIMx_CCMR1\n(from channel 2)\n10\nIC1\ndivider\n/1, /2, /4, /8\nIC1PS\nTRC\n11\n(from slave mode\ncontroller)\nTIMx_CCER\nTI2F_rising\n(from channel 2)\nTI2F_falling\n01\nTI2FP1\n0\nCC1S[1:0] ICPS[1:0]\n1\nTIMx_CCMR1\nCC1E\nTIMx_CCER\nThe output stage generates an intermediate waveform which is then used for reference:\nOCxRef (active high). The polarity acts at the end of the chain.\nFigure 126. Capture/compare channel 1 main circuit\nAPB Bus\nread CCR1L\nread_in_progress\nCC1S[0]\nIC1PS\nCapture/Compare Preload Register\ninput\nmode\noutput\nmode\nCapture/Compare Shadow Register\ncomparator\ncapture\nCNT>CCR1\nCounter\nCC1G\nTIMx_EGR\nDoc ID 13902 Rev 14\nS write CCR1H\nR\ncompare_transfer\nCC1E\n366/1096\nwrite_in_progress\nR\ncapture_transfer\nCC1S[1]\n8\nread CCR1H S\n8\nMCU-peripheral interface\nCNT=CCR1\nwrite CCR1L\nCC1S[1]\nCC1S[0]\nOC1PE\nOC1PE\nUEV\nTIMx_CCMR1\n(from time\nbase unit) RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 127. Output stage of capture/compare channel (channel 1)\nOCREF_CLR\nETRF\n0\nocref_clr_int\n1\nTo the master mode\ncontroller\n0\nOCCS\n1\nTIMx_SMCR\nOutput\nEnable\nCircuit\nOC1\nCC1P\nCNT > CCR1\nOutput mode oc1ref\nCNT = CCR1 controller\nTIMx_CCER\nCC1E\nTIMx_CCER\nOC1M[2:0]\nTIMx_CCMR1\nai17187\nThe capture/compare block is made of one preload register and one shadow register. Write\nand read always access the preload register.\nIn capture mode, captures are actually done in the shadow register, which is copied into the\npreload register.\nIn compare mode, the content of the preload register is copied into the shadow register\nwhich is compared to the counter.\n15.3.5\nInput capture mode\nIn Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the\nvalue of the counter after a transition detected by the corresponding ICx signal. When a\ncapture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or\na DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was\nalready high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be\ncleared by software by writing it to 0 or by reading the captured data stored in the\nTIMx_CCRx register. CCxOF is cleared when you write it to 0.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1\ninput rises. To do this, use the following procedure:\n●\n●\nSelect the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S\nbits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,\nthe channel is configured in input and the TIMx_CCR1 register becomes read-only.\nProgram the input filter duration you need with respect to the signal you connect to the\ntimer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s\nimagine that, when toggling, the input signal is not stable during at must 5 internal clock\ncycles. We must program a filter duration longer than these 5 clock cycles. We can\nvalidate a transition on TI1 when 8 consecutive samples with the new level have been\nDoc ID 13902 Rev 14\n367/1096 General-purpose timers (TIM2 to TIM5)\n●\n●\n●\n●\nRM0008\ndetected (sampled at f DTS frequency). Then write IC1F bits to 0011 in the\nTIMx_CCMR1 register.\nSelect the edge of the active transition on the TI1 channel by writing the CC1P bit to 0\nin the TIMx_CCER register (rising edge in this case).\nProgram the input prescaler. In our example, we wish the capture to be performed at\neach valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the\nTIMx_CCMR1 register).\nEnable capture from the counter into the capture register by setting the CC1E bit in the\nTIMx_CCER register.\nIf needed, enable the related interrupt request by setting the CC1IE bit in the\nTIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the\nTIMx_DIER register.\nWhen an input capture occurs:\n●\n●\n●\n●\nThe TIMx_CCR1 register gets the value of the counter on the active transition.\nCC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures\noccurred whereas the flag was not cleared.\nAn interrupt is generated depending on the CC1IE bit.\nA DMA request is generated depending on the CC1DE bit.\nIn order to handle the overcapture, it is recommended to read the data before the\novercapture flag. This is to avoid missing an overcapture which could happen after reading\nthe flag and before reading the data.\nNote: IC interrupt and/or DMA requests can be generated by software by setting the\ncorresponding CCxG bit in the TIMx_EGR register.\n15.3.6 PWM input mode\nThis mode is a particular case of input capture mode. The procedure is the same except:\n368/1096\n● Two ICx signals are mapped on the same TIx input.\n● These 2 ICx signals are active on edges with opposite polarity.\n● One of the two TIxFP signals is selected as trigger input and the slave mode controller\nis configured in reset mode.\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFor example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in\nTIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending\non CK_INT frequency and prescaler value):\n● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1\nregister (TI1 selected).\n● Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter\nclear): write the CC1P to ‘0’ (active on rising edge).\n● Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1\nregister (TI1 selected).\n● Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P\nbit to ‘1’ (active on falling edge).\n● Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register\n(TI1FP1 selected).\n● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the\nTIMx_SMCR register.\n● Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.\nFigure 128. PWM input mode timing\nTI1\nTIMx_CNT\n0004\n0000\n0001\n0002\nTIMx_CCR1 0004\nTIMx_CCR2 0002\nIC1 capture\nIC2 capture\nreset counter\n0003\n0004\nIC2 capture\npulse width\nmeasurement\n0000\nIC1 capture\nperiod\nmeasurement\nai15413\n1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only\nTI1FP1 and TI2FP2 are connected to the slave mode controller.\n15.3.7\nForced output mode\nIn output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal\n(OCxREF and then OCx) can be forced to active or inactive level directly by software,\nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (ocxref/OCx) to its active level, you just need to write 101\nin the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high\n(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.\ne.g.: CCxP=0 (OCx active high) => OCx is forced to high level.\nocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx\nregister.\nDoc ID 13902 Rev 14\n369/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still\nperformed and allows the flag to be set. Interrupt and DMA requests can be sent\naccordingly. This is described in the Output Compare Mode section.\n15.3.8\nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has\nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output\ncompare function:\n● Assigns the corresponding output pin to a programmable value defined by the output\ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP\nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set\nactive (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.\n● Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the\nTIMx_DIER register).\n● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the\nTIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request\nselection).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the\nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on ocxref and OCx output.\nThe timing resolution is one count of the counter. Output compare mode can also be used to\noutput a single pulse (in One-pulse mode).\nProcedure:\n1. Select the counter clock (internal, external, prescaler).\n2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be\ngenerated.\n4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0\nand CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not\nused, OCx is enabled and active high.\n5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.\nThe TIMx_CCRx register can be updated at any time by software to control the output\nwaveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx\nshadow register is updated only at the next update event UEV). An example is given in\nFigure 129.\n370/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 129. Output compare mode, toggle on OC1.\nWrite B201h in the CC1R register\nTIMx_CNT\nTIMx_CCR1\n0039\n003A\n003B\n003A\nB200\nB201\nB201\nOC1REF=OC1\nMatch detected on CCR1\nInterrupt generated if enabled\n15.3.9\nPWM mode\nPulse width modulation mode allows you to generate a signal with a frequency determined\nby the value of the TIMx_ARR register and a duty cycle determined by the value of the\nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx\noutput) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the\nTIMx_CCMRx register. You must enable the corresponding preload register by setting the\nOCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in\nupcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event\noccurs, before starting the counter, you have to initialize all the registers by setting the UG\nbit in the TIMx_EGR register.\nOCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It\ncan be programmed as active high or active low. OCx output is enabled by the CCxE bit in\nthe TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine\nwhether TIMx_CCRx≤ TIMx_CNT or TIMx_CNT≤ TIMx_CCRx (depending on the direction\nof the counter). However, to comply with the OCREF_CLR functionality (OCREF can be\ncleared by an external event through the ETR signal until the next PWM period), the OCREF\nsignal is asserted only:\n● When the result of the comparison changes, or\n● When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from\nthe “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes\n(OCxM=‘110 or ‘111).\nThis forces the PWM by software while the timer is running.\nThe timer is able to generate PWM in edge-aligned mode or center-aligned mode\ndepending on the CMS bits in the TIMx_CR1 register.\nDoc ID 13902 Rev 14\n371/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nPWM edge-aligned mode\nUpcounting configuration\nUpcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section :\nUpcounting mode on page 354.\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is\nhigh as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in\nTIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.\nIf the compare value is 0 then OCxREF is held at ‘0. Figure 130 shows some edge-aligned\nPWM waveforms in an example where TIMx_ARR=8.\nFigure 130. Edge-aligned PWM waveforms (ARR=8)\n0\nCounter register\nCCRx=4\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCxREF\nCCxIF\nOCxREF\nCCRx=8\nCCxIF\nOCxREF\n‘1\nCCRx>8\nCCxIF\nOCxREF\n‘0\nCCRx=0\nCCxIF\nDowncounting configuration\nDowncounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :\nDowncounting mode on page 357.\nIn PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else\nit becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in\nTIMx_ARR, then ocxref is held at ‘1. 0% PWM is not possible in this mode.\nPWM center-aligned mode\nCenter-aligned mode is active when the CMS bits in TIMx_CR1 register are different from\n‘00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The\ncompare flag is set when the counter counts up, when it counts down or both when it counts\nup and down depending on the CMS bits configuration. The direction bit (DIR) in the\nTIMx_CR1 register is updated by hardware and must not be changed by software. Refer to\nSection : Center-aligned mode (up/down counting) on page 359.\nFigure 131 shows some center-aligned PWM waveforms in an example where:\n●\n●\n●\n372/1096\nTIMx_ARR=8,\nPWM mode is the PWM mode 1,\nThe flag is set when the counter counts down corresponding to the center-aligned\nmode 1 selected for CMS=01 in TIMx_CR1 register.\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 131. Center-aligned PWM waveforms (ARR=8)\n#OUNTER General-purpose timers (TIM2 to TIM5)\n15.3.10\nRM0008\nOne-pulse mode\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to\nbe started in response to a stimulus and to generate a pulse with a programmable length\nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the\nwaveform can be done in output compare mode or PWM mode. You select One-pulse mode\nby setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically\nat the next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter\ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must\nbe:\n● In upcounting: CNT<CCRx≤ ARR (in particular, 0<CCRx),\n● In downcounting: CNT>CCRx.\nFigure 132. Example of one-pulse mode.\nTI2\nOC1REF\nOC1\nTIM1_ARR\nTIM1_CCR1\n0\nt DELAY\nt PULSE\nt\nFor example you may want to generate a positive pulse on OC1 with a length of t PULSE and\nafter a delay of t DELAY as soon as a positive edge is detected on the TI2 input pin.\nLet’s use TI2FP2 as trigger 1:\n● Map TI2FP2 on TI2 by writing IC2S=01 in the TIMx_CCMR1 register.\n● TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register.\n● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in\nthe TIMx_SMCR register.\n● TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register\n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the\nclock frequency and the counter prescaler).\n374/1096\n● The t DELAY is defined by the value written in the TIMx_CCR1 register.\n● The t PULSE is defined by the difference between the auto-reload value and the compare\nvalue (TIMx_ARR - TIMx_CCR1).\n● Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare\nmatch occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nvalue. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1\nregister. You can optionally enable the preload registers by writing OC1PE=1 in the\nTIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to\nwrite the compare value in the TIMx_CCR1 register, the auto-reload value in the\nTIMx_ARR register, generate an update by setting the UG bit and wait for external\ntrigger event on TI2. CC1P is written to ‘0 in this example.\nIn our example, the DIR and CMS bits in the TIMx_CR1 register should be low.\nYou only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1\nregister to stop the counter at the next update event (when the counter rolls over from the\nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the\nRepetitive Mode is selected.\nParticular case: OCx fast enable:\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the\ncounter. Then the comparison between the counter and the compare value makes the\noutput toggle. But several clock cycles are needed for these operations and it limits the\nminimum delay t DELAY min we can get.\nIf you want to output a waveform with the minimum delay, you can set the OCxFE bit in the\nTIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,\nwithout taking in account the comparison. Its new level is the same as if a compare match\nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n15.3.11\nClearing the OCxREF signal on an external event\nThe OCxREF signal for a given channel can be reset by applying a high level on the ETRF\ninput (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF\nremains low until the next update event (UEV) occurs.\nThis function can be used only in the output compare and PWM modes. It does not work in\nforced mode.\nFor example, the OCxREF signal can be connected to the output of a comparator to be used\nfor current handling. In this case, ETR must be configured as follows:\n1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR\nregister are cleared to 00.\n2. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is\ncleared to 0.\n3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be\nconfigured according to the application’s needs.\nFigure 133 shows the behavior of the OCxREF signal when the ETRF input becomes high,\nfor both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in\nPWM mode.\nDoc ID 13902 Rev 14\n375/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 133. Clearing TIMx OCxREF\n(CCRx)\ncounter (CNT)\nETRF\nOCxREF\n(OCxCE=0)\nOCxREF\n(OCxCE=1)\nOCREF_CLR\nbecomes high\n15.3.12\nOCREF_CLR\nstill high\nEncoder interface mode\nTo select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter\nis counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if\nit is counting on both TI1 and TI2 edges.\nSelect the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER\nregister. When needed, you can program the input filter as well.\nThe two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to\nTable 85. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2\nafter input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,\nTI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in\nTIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated\nand generates count pulses as well as the direction signal. Depending on the sequence the\ncounter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware\naccordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever\nthe counter is counting on TI1 only, TI2 only or both TI1 and TI2.\nEncoder interface mode acts simply as an external clock with direction selection. This\nmeans that the counter just counts continuously between 0 and the auto-reload value in the\nTIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must\nconfigure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,\ntrigger output features continue to work as normal.\nIn this mode, the counter is modified automatically following the speed and the direction of\nthe incremental encoder and its content, therefore, always represents the encoder’s\nposition. The count direction correspond to the rotation direction of the connected sensor.\nThe table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the\nsame time.\n376/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nTable 85.\nCounting direction versus encoder signals\nLevel on opposite\nsignal (TI1FP1 for\nTI2, TI2FP2 for TI1) Rising Falling Rising Falling\nCounting on\nTI1 only High Down Up No Count No Count\nLow Up Down No Count No Count\nCounting on\nTI2 only High No Count No Count Up Down\nLow No Count No Count Down Up\nCounting on\nTI1 and TI2 High Down Up Up Down\nLow Up Down Down Up\nActive edge\nTI1FP1 signal\nTI2FP2 signal\nAn external incremental encoder can be connected directly to the MCU without external\ninterface logic. However, comparators are normally be used to convert the encoder’s\ndifferential outputs to digital signals. This greatly increases noise immunity. The third\nencoder output which indicate the mechanical zero position, may be connected to an\nexternal interrupt input and trigger a counter reset.\nFigure 134 gives an example of counter operation, showing count signal generation and\ndirection control. It also shows how input jitter is compensated where both edges are\nselected. This might occur if the sensor is positioned near to one of the switching points. For\nthis example we assume that the configuration is the following:\n● CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)\n● CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)\n● CC1P=0 (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)\n● CC2P=0 (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)\n● SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling\nedges)\n● CEN= 1 (TIMx_CR1 register, Counter is enabled)\nFigure 134. Example of counter operation in encoder interface mode\nforward\njitter\nbackward\njitter\nforward\nTI1\nTI2\nCounter\nup\ndown\nDoc ID 13902 Rev 14\nup\n377/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 135 gives an example of counter behavior when TI1FP1 polarity is inverted (same\nconfiguration as above except CC1P=1).\nFigure 135. Example of encoder interface mode with TI1FP1 polarity inverted\nforward\njitter\nbackward\njitter\nforward\nTI1\nTI2\nCounter\ndown\nup\ndown\nThe timer, when configured in Encoder Interface mode provides information on the sensor’s\ncurrent position. You can obtain dynamic information (speed, acceleration, deceleration) by\nmeasuring the period between two encoder events using a second timer configured in\ncapture mode. The output of the encoder which indicates the mechanical zero can be used\nfor this purpose. Depending on the time between two events, the counter can also be read\nat regular times. You can do this by latching the counter value into a third input capture\nregister if available (then the capture signal must be periodic and can be generated by\nanother timer). when available, it is also possible to read its value through a DMA request\ngenerated by a Real-Time clock.\n15.3.13\nTimer input XOR function\nThe TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to\nthe output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.\nThe XOR output can be used with all the timer input functions such as trigger or input\ncapture.\nAn example of this feature used to interface Hall sensors is given in Section 14.3.18 on page\n317.\n15.3.14\nTimers and external trigger synchronization\nThe TIMx Timers can be synchronized with an external trigger in several modes: Reset\nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input.\nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is\ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n●\n378/1096\nConfigure the channel 1 to detect rising edges on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write\nCC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).\n● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n● Start the counter by writing CEN=1 in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising\nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the\ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA\nrequest can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.\nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the\nresynchronization circuit on TI1 input.\nFigure 136. Control circuit in reset mode\nTI1\nUG\nCounter clock = CK_CNT = CK_PSC\nCounter register\n30 31 32 33 34 35 36 00 01 02 03 00 01 02 03\nTIF\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=0000). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write\nCC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).\n● Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\n● Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the\ncounter doesn’t start if CEN=0, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as\nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts\nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the\nresynchronization circuit on TI1 input.\nDoc ID 13902 Rev 14\n379/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nFigure 137. Control circuit in gated mode\nTI1\nCNT_EN\nCounter clock = CK_CNT = CK_PSC\nCounter register\n30 31 32 33\n34\n35 36 37 38\nTIF\nWrite TIF=0\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC2F=0000). The capture\nprescaler is not used for triggering, so you don’t need to configure it. CC2S bits are\nselecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write\nCC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).\n● Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select\nTI2 as the input source by writing TS=110 in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the\nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the\nresynchronization circuit on TI2 input.\nFigure 138. Control circuit in trigger mode\nTI2\nCNT_EN\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35 36 37 38\nTIF\nSlave mode: External Clock mode 2 + trigger mode\nThe external clock mode 2 can be used in addition to another slave mode (except external\nclock mode 1 and encoder mode). In this case, the ETR signal is used as external clock\ninput, and another input can be selected as trigger input when operating in reset mode,\ngated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS\nbits of TIMx_SMCR register.\n380/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nIn the following example, the upcounter is incremented at each rising edge of the ETR signal\nas soon as a rising edge of TI1 occurs:\n1.\n2.\n3.\nConfigure the external trigger input circuit by programming the TIMx_SMCR register as\nfollows:\n– ETF = 0000: no filter\n– ETPS=00: prescaler disabled\n– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock\nmode 2.\nConfigure the channel 1 as follows, to detect rising edges on TI:\n– IC1F=0000: no filter.\n– The capture prescaler is not used for triggering and does not need to be\nconfigured.\n– CC1S=01in TIMx_CCMR1 register to select only the input capture source\n– CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge\nonly).\nConfigure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=101 in TIMx_SMCR register.\nA rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on\nETR rising edges.\nThe delay between the rising edge of the ETR signal and the actual reset of the counter is\ndue to the resynchronization circuit on ETRP input.\nFigure 139. Control circuit in external clock mode 2 + trigger mode\nTI1\nCEN/CNT_EN\nETR\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35\n36\nTIF\nDoc ID 13902 Rev 14\n381/1096 General-purpose timers (TIM2 to TIM5)\n15.3.15\nRM0008\nTimer synchronization\nThe TIMx timers are linked together internally for timer synchronization or chaining. When\none Timer is configured in Master Mode, it can reset, start, stop or clock the counter of\nanother Timer configured in Slave Mode.\nFigure 140: Master/Slave timer example presents an overview of the trigger selection and\nthe master mode selection blocks.\nUsing one timer as prescaler for another\nFigure 140. Master/Slave timer example\nTIM1\nTIM2\nMMS\nClock\nUEV\nMaster\nmode\nPrescaler\nCounter\nTS\nTRGO1 ITR1\nSMS\nSlave\nCK_PSC\nmode\ncontrol\ncontrol\nPrescaler\nCounter\nInput\ntrigger\nselection\nFor example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to\nFigure 140. To do this:\nNote:\n● Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each\nupdate event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is\noutput on TRGO1 each time an update event is generated.\n● To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in\nslave mode using ITR1 as internal trigger. You select this through the TS bits in the\nTIM2_SMCR register (writing TS=000).\n● Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the\nTIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the\nperiodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).\n● Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1\nregister).\nIf OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock\nthe counter of timer 2.\nUsing one timer to enable another timer\nIn this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.\nRefer to Figure 140 for connections. Timer 2 counts on the divided internal clock only when\n382/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nOC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the\nprescaler compared to CK_INT (f CK_CNT = f CK_INT /3).\nNote:\n● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)\nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR\nregister).\n● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n● Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nThe counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2\ncounter enable signal.\nFigure 141. Gating timer 2 with OC1REF of timer 1\nCK_INT\nTIMER1-OC1REF\nTIMER1-CNT\nTIMER2-CNT\nFC\nFD\n3045\nFE\n3046\nFF\n3047\n00\n01\n3048\nTIMER 2-TIF\nWrite TIF=0\nIn the example in Figure 141, the Timer 2 counter and prescaler are not initialized before\nbeing started. So they start counting from their current value. It is possible to start from a\ngiven value by resetting both timers before starting Timer 1. You can then write any value\nyou want in the timer counters. The timers can easily be reset by software using the UG bit\nin the TIMx_EGR registers.\nIn the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts\nfrom 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both\nDoc ID 13902 Rev 14\n383/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\ntimers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1\nregister:\n● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)\nsignal as trigger output (MMS=100 in the TIM1_CR2 register).\n● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).\n● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR\nregister).\n● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).\n● Reset Timer 1 by writing ‘1 in UG bit (TIM1_EGR register).\n● Reset Timer 2 by writing ‘1 in UG bit (TIM2_EGR register).\n● Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).\n● Enable Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\n● Stop Timer 1 by writing ‘0 in the CEN bit (TIM1_CR1 register).\nFigure 142. Gating timer 2 with Enable of timer 1\nCK_INT\nTIMER1-CEN=CNT_EN\nTIMER1-CNT_INIT\nTIMER1-CNT\nTIMER2-CNT\n75\n00\nAB\n00\nE7\n01 02\nE8 E9\nTIMER2-CNT_INIT\nTIMER2\nwrite CNT\nTIMER 2-TIF\nWrite TIF=0\nUsing one timer to start another timer\nIn this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to\nFigure 140 for connections. Timer 2 starts counting from its current value (which can be\nnonzero) on the divided internal clock as soon as the update event is generated by Timer 1.\nWhen Timer 2 receives the trigger signal its CEN bit is automatically set and the counter\ncounts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock\nfrequencies are divided by 3 by the prescaler compared to CK_INT (f CK_CNT = f CK_INT /3).\n384/1096\n● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output\n(MMS=010 in the TIM1_CR2 register).\n● Configure the Timer 1 period (TIM1_ARR registers).\n● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR\nregister).\n● Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).\n● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 143. Triggering timer 2 with update of timer 1\nCK_INT\nTIMER1-UEV\nTIMER1-CNT\nFD\nFE\nTIMER2-CNT\n00\nFF\n45\n02\n01\n47\n46\n48\nTIMER2-CEN=CNT_EN\nTIMER 2-TIF\nWrite TIF=0\nAs in the previous example, you can initialize both counters before starting counting.\nFigure 144 shows the behavior with the same configuration as in Figure 143 but in trigger\nmode instead of gated mode (SMS=110 in the TIM2_SMCR register).\nFigure 144. Triggering timer 2 with Enable of timer 1\nCK_INT\nTIMER1-CEN=CNT_EN\nTIMER1-CNT_INIT\nTIMER1-CNT\nTIMER2-CNT\n75\n00\nCD\n00\n01\nE7\nE8\n02\nE9\nEA\nTIMER2-CNT_INIT\nTIMER2\nwrite CNT\nTIMER 2-TIF\nWrite TIF=0\nDoc ID 13902 Rev 14\n385/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nUsing one timer as prescaler for another timer\nFor example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to\nFigure 140 for connections. To do this:\n● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output\n(MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter\noverflow.\n● Configure the Timer 1 period (TIM1_ARR registers).\n● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR\nregister).\n● Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register).\n● Start Timer 2 by writing ‘1 in the CEN bit (TIM2_CR1 register).\n● Start Timer 1 by writing ‘1 in the CEN bit (TIM1_CR1 register).\nStarting 2 timers synchronously in response to an external trigger\nIn this example, we set the enable of timer 1 when its TI1 input rises, and the enable of\nTimer 2 with the enable of Timer 1. Refer to Figure 140 for connections. To ensure the\ncounters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect\nto TI1, master with respect to Timer 2):\n● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the\nTIM1_CR2 register).\n● Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the\nTIM1_SMCR register).\n● Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).\n● Configure the Timer 1 in Master/Slave mode by writing MSM=1 (TIM1_SMCR register).\n● Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR\nregister).\n● Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).\nWhen a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on\nthe internal clock and both TIF flags are set.\nNote:\n386/1096\nIn this example both timers are initialized before starting (by setting their respective UG\nbits). Both counters starts from 0, but you can easily insert an offset between them by\nwriting any of the counter registers (TIMx_CNT). You can see that the master/slave mode\ninsert a delay between CNT_EN and CK_PSC on timer 1.\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nFigure 145. Triggering timer 1 and 2 with timer 1 TI1 input\nCK_INT\nTIMER 1-TI1\nTIMER1-CEN=CNT_EN\nTIMER 1-CK_PSC\nTIMER1-CNT\n00 01 02 03 04 05 06 07 08 09\n00 01 02 03 04 05 06 07 08 09\nTIMER1-TIF\nTIMER2-CEN=CNT_EN\nTIMER 2-CK_PSC\nTIMER2-CNT\nTIMER2-TIF\n15.3.16\nDebug mode\nWhen the microcontroller enters debug mode (Cortex™-M3 core - halted), the TIMx counter\neither continues to work normally or stops, depending on DBG_TIMx_STOP configuration\nbit in DBGMCU module. For more details, refer to Section 31.16.2: Debug support for\ntimers, watchdog, bxCAN and I2C.\nDoc ID 13902 Rev 14\n387/1096 General-purpose timers (TIM2 to TIM5)\n15.4\nRM0008\nTIMx2 to TIM5 registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n15.4.1\nTIMx control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\nCKD[1:0]\n7\n6\nARPE\n5\nCMS\n4 3 2 1 0\nDIR OPM URS UDIS CEN\nrw rw rw rw rw\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and\nsampling clock used by the digital filters (ETR, TIx),\n00: t DTS = t CK_INT\n01: t DTS = 2 × t CK_INT\n10: t DTS = 4 × t CK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:5 CMS: Center-aligned mode selection\n00: Edge-aligned mode. The counter counts up or down depending on the direction bit\n(DIR).\n01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nonly when the counter is counting down.\n10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nonly when the counter is counting up.\n11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare\ninterrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set\nboth when the counter is counting up or down.\nNote: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as\nthe counter is enabled (CEN=1)\nBit 4 DIR: Direction\n0: Counter used as upcounter\n1: Counter used as downcounter\nNote: This bit is read only when the timer is configured in Center-aligned mode or Encoder\nmode.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the bit CEN)\n388/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generate an update interrupt or DMA request if enabled.\nThese events can be:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value\n(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is\nset or if a hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: External clock, gated mode and encoder mode can work only if the CEN bit has been\npreviously set by software. However trigger mode can set the CEN bit automatically by\nhardware.\nCEN is cleared automatically in one-pulse mode, when an update event occurs.\nDoc ID 13902 Rev 14\n389/1096 General-purpose timers (TIM2 to TIM5)\n15.4.2\nRM0008\nTIMx control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\nTI1S\n5\n4\nMMS[2:0]\n3\n2\n1\n0\nCCDS\nReserved\nReserved\nrw\nrw\nrw\nrw\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 TI1S: TI1 selection\n0: The TIMx_CH1 pin is connected to TI1 input\n1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)\nSee also Section 14.3.18: Interfacing with Hall sensors on page 317\nBits 6:4 MMS: Master mode selection\nThese bits allow to select the information to be sent in master mode to slave timers for\nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the\nreset is generated by the trigger input (slave mode controller configured in reset mode) then\nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is\nuseful to start several timers at the same time or to control a window in which a slave timer is\nenabled. The Counter Enable signal is generated by a logic OR between CEN control bit and\nthe trigger input when configured in gated mode.\nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,\nexcept if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR\nregister).\n010: Update - The update event is selected as trigger output (TRGO). For instance a master\ntimer can then be used as a prescaler for a slave timer.\n011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be\nset (even if it was already high), as soon as a capture or a compare match occurred. (TRGO)\n100: Compare - OC1REF signal is used as trigger output (TRGO)\n101: Compare - OC2REF signal is used as trigger output (TRGO)\n110: Compare - OC3REF signal is used as trigger output (TRGO)\n111: Compare - OC4REF signal is used as trigger output (TRGO)\nBit 3 CCDS: Capture/compare DMA selection\n0: CCx DMA request sent when CCx event occurs\n1: CCx DMA requests sent when update event occurs\nBits 2:0 Reserved, must be kept at reset value.\n390/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\n15.4.3\nTIMx slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n15 14\nETP ECE\nrw rw\n13\n12\n11\nETPS[1:0]\n10\n9\n8\nETF[3:0]\n7\n6\nMSM\n5\n4\n3\n2\nTS[2:0]\n1\n0\nSMS[2:0]\nRes.\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBit 15 ETP: External trigger polarity\nThis bit selects whether ETR or ETR is used for trigger operations\n0: ETR is non-inverted, active at high level or rising edge\n1: ETR is inverted, active at low level or falling edge\nBit 14 ECE: External clock enable\nThis bit enables External clock mode 2.\n0: External clock mode 2 disabled\n1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF\nsignal.\n1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI\nconnected to ETRF (SMS=111 and TS=111).\n2: It is possible to simultaneously use external clock mode 2 with the following slave modes:\nreset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to\nETRF in this case (TS bits must not be 111).\n3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the\nexternal clock input is ETRF.\nBits 13:12 ETPS: External trigger prescaler\nExternal trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A\nprescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external\nclocks.\n00: Prescaler OFF\n01: ETRP frequency divided by 2\n10: ETRP frequency divided by 4\n11: ETRP frequency divided by 8\nBits 11:8 ETF[3:0]: External trigger filter\nThis bit-field then defines the frequency used to sample ETRP signal and the length of the\ndigital filter applied to ETRP. The digital filter is made of an event counter in which N events\nare needed to validate a transition on the output:\n1000: f SAMPLING =f DTS /8, N=6\n0000: No filter, sampling is done at f DTS\n0001: f SAMPLING =f CK_INT , N=2\n1001: f SAMPLING =f DTS /8, N=8\n1010: f SAMPLING =f DTS /16, N=5\n0010: f SAMPLING =f CK_INT , N=4\n1011: f SAMPLING =f DTS /16, N=6\n0011: f SAMPLING =f CK_INT , N=8²\n0100: f SAMPLING =f DTS /2, N=6\n1100: f SAMPLING =f DTS /16, N=8\n0101: f SAMPLING =f DTS /2, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n0110: f SAMPLING =f DTS /4, N=6²\n0111: f SAMPLING =f DTS /4, N=8\n1111: f SAMPLING =f DTS /32, N=8\nBit 7 MSM: Master/Slave mode\n0: No action\n1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect\nsynchronization between the current timer and its slaves (through TRGO). It is useful if we\nwant to synchronize several timers on a single external event.\nDoc ID 13902 Rev 14\n391/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nBits 6:4 TS: Trigger selection\nThis bit-field selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0).\n001: Internal Trigger 1 (ITR1).\n010: Internal Trigger 2 (ITR2).\n011: Internal Trigger 3 (ITR3).\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: External Trigger input (ETRF)\nSee Table 86: TIMx Internal trigger connection on page 392for more details on ITRx\nmeaning for each Timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=000) to\navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected the active edge of the trigger signal (TRGI) is linked to\nthe polarity selected on the external input (see Input Control register and Control Register\ndescription.\n000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal\nclock.\n001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1\nlevel.\n010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2\nlevel.\n011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges\ndepending on the level of the other input.\n100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter\nand generates an update of the registers.\n101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The\ncounter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of\nthe counter are controlled.\n110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not\nreset). Only the start of the counter is controlled.\n111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.\nNote: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).\nIndeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode\nchecks the level of the trigger signal.\nTable 86.\nTIMx Internal trigger connection (1)\nSlave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011)\nTIM2 TIM1 TIM8 TIM3 TIM4\nTIM3 TIM1 TIM2 TIM5 TIM4\nTIM4 TIM1 TIM2 TIM3 TIM8\nTIM5 TIM2 TIM3 TIM4 TIM8\n1. When a timer is not present in the product, the corresponding trigger ITRx is not available.\n392/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\n15.4.4\nTIMx DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n15\n14\n13\nTDE\nRes.\n12\n11\n10\n9\nCC4DE CC3DE CC2DE CC1DE\n8\nRes\nrw\n6\nrw\nrw\nrw\n5\nTIE\nRes.\nrw\nBit 15\n7\nUDE\nrw\n4 3 2 1 0\nCC4IE CC3IE CC2IE CC1IE UIE\nrw rw rw rw rw\nRes\nrw\nReserved, must be kept at reset value.\nBit 14 TDE: Trigger DMA request enable\n0: Trigger DMA request disabled.\n1: Trigger DMA request enabled.\nBit 13\nReserved, always read as 0\nBit 12 CC4DE: Capture/Compare 4 DMA request enable\n0: CC4 DMA request disabled.\n1: CC4 DMA request enabled.\nBit 11 CC3DE: Capture/Compare 3 DMA request enable\n0: CC3 DMA request disabled.\n1: CC3 DMA request enabled.\nBit 10 CC2DE: Capture/Compare 2 DMA request enable\n0: CC2 DMA request disabled.\n1: CC2 DMA request enabled.\nBit 9 CC1DE: Capture/Compare 1 DMA request enable\n0: CC1 DMA request disabled.\n1: CC1 DMA request enabled.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBit 7\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IE: Capture/Compare 4 interrupt enable\n0: CC4 interrupt disabled.\n1: CC4 interrupt enabled.\nBit 3 CC3IE: Capture/Compare 3 interrupt enable\n0: CC3 interrupt disabled.\n1: CC3 interrupt enabled.\nDoc ID 13902 Rev 14\n393/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled.\n1: CC2 interrupt enabled.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled.\n1: CC1 interrupt enabled.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n15.4.5\nTIMx status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\nCC4OF CC3OF CC2OF CC1OF\nReserved\nTIF\nReserved\nrc_w0\nBit 15:13\nrc_w0\nrc_w0\n5\nrc_w0\n4 3 2 1\n0\nCC4IF CC3IF CC2IF CC1IF UIF\nrc_w0 rc_w0 rc_w0 rc_w0 rc_w0\nRes\nrc_w0\nReserved, must be kept at reset value.\nBit 12 CC4OF: Capture/Compare 4 overcapture flag\nrefer to CC1OF description\nBit 11 CC3OF: Capture/Compare 3 overcapture flag\nrefer to CC1OF description\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input\ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was\nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the\nslave mode controller is enabled in all modes but gated mode, both edges in case gated\nmode is selected). It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBit 5\nReserved, must be kept at reset value.\nBit 4 CC4IF: Capture/Compare 4 interrupt flag\nrefer to CC1IF description\nBit 3 CC3IF: Capture/Compare 3 interrupt flag\nrefer to CC1IF description\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\n394/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value, with some\nexception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register\ndescription). It is cleared by software.\n0: No match.\n1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1\nregister.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the\nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected\non IC1 which matches the selected polarity).\nBit 0 UIF: Update interrupt flag\n–This bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–At overflow or underflow regarding the repetition counter value (update if repetition\ncounter = 0) and if the UDIS=0 in the TIMx_CR1 register.\n–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0\nand UDIS=0 in the TIMx_CR1 register.\n–When CNT is reinitialized by a trigger event (refer to the synchro control register\ndescription), if URS=0 and UDIS=0 in the TIMx_CR1 register.\nDoc ID 13902 Rev 14\n395/1096 General-purpose timers (TIM2 to TIM5)\n15.4.6\nRM0008\nTIMx event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\nTG\nReserved\n4 3 2 1 0\nCC4G CC3G CC2G CC1G UG\nw w w w w\nRes.\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if\nenabled.\nBit 5 Reserved, must be kept at reset value.\nBit 4 CC4G: Capture/compare 4 generation\nrefer to CC1G description\nBit 3 CC3G: Capture/compare 3 generation\nrefer to CC1G description\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,\nthe corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the\nCC1IF flag was already high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler\ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if\nthe center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload\nvalue (TIMx_ARR) if DIR=1 (downcounting).\n396/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\n15.4.7\nTIMx capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The\ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other\nbits of this register have a different function in input and in output mode. For a given bit,\nOCxx describes its function when the channel is configured in output, ICxx describes its\nfunction when the channel is configured in input. So you must take care that the same bit\ncan have a different meaning for the input stage and for the output stage.\n15\n14\nOC2CE\n13\n12\nOC2M[2:0]\n11\n10\n9\n8\nOC2PE OC2FE\n7\n6\nOC1CE\n5\n4\nOC1M[2:0]\n3\n2\nCC2S[1:0]\nIC2F[3:0]\nrw\nrw\nrw\nrw\nrw\nIC1F[3:0]\nrw\nrw\n0\nCC1S[1:0]\nIC2PSC[1:0]\nrw\n1\nOC1PE OC1FE\nrw\nrw\nrw\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only\nif an internal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output Compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\nDoc ID 13902 Rev 14\n397/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and\nOC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends\non CC1P and CC1NP bits.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the\ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing\nbase).\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter\nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the\ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1\nelse inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as\nTIMx_CNT>TIMx_CCR1 else active (OC1REF=1).\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as\nTIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as\nTIMx_CNT>TIMx_CCR1 else inactive.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed\n(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in\noutput).\n2: In PWM mode 1 or 2, the OCREF level changes only when the result of the\ncomparison changes or when the output compare mode switches from “frozen” mode\nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the\nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload\nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: 1: These bits can not be modified as long as LOCK level 3 has been programmed\n(LOCK bits in TIMx_BDTR register) and CC1S=00 (the channel is configured in\noutput).\n2: The PWM mode can be used without validating the preload register only in one-\npulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is\nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is\n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC\nis set to the compare level independently from the result of the comparison. Delay to sample\nthe trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if\nthe channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: CC1 channel is configured as input, IC1 is mapped on TI2.\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only\nif an internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n398/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output.\n01: CC2 channel is configured as input, IC2 is mapped on TI2.\n10: CC2 channel is configured as input, IC2 is mapped on TI1.\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter\napplied to TI1. The digital filter is made of an event counter in which N events are needed to\nvalidate a transition on the output:\n1000: f SAMPLING =f DTS /8, N=6\n0000: No filter, sampling is done at f DTS\n1001: f SAMPLING =f DTS /8, N=8\n0001: f SAMPLING =f CK_INT , N=2\n0010: f SAMPLING =f CK_INT , N=4\n1010: f SAMPLING =f DTS /16, N=5\n1011: f SAMPLING =f DTS /16, N=6\n0011: f SAMPLING =f CK_INT , N=8\n1100: f SAMPLING =f DTS /16, N=8\n0100: f SAMPLING =f DTS /2, N=6\n0101: f SAMPLING =f DTS /2, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n0110: f SAMPLING =f DTS /4, N=6\n1111: f SAMPLING =f DTS /32, N=8\n0111: f SAMPLING =f DTS /4, N=8\nNote: In current silicon revision, f DTS is replaced in the formula by CK_INT when ICxF[3:0]= 1,\n2 or 3.\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=0 (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\nDoc ID 13902 Rev 14\n399/1096 General-purpose timers (TIM2 to TIM5)\n15.4.8\nRM0008\nTIMx capture/compare mode register 2 (TIMx_CCMR2)\nAddress offset: 0x1C\nReset value: 0x0000\nRefer to the above CCMR1 register description.\n15\n14\nOC4CE\n13\n12\nOC4M[2:0]\n11\n10\n9\n8\nOC4PE OC4FE\n7\n6\nOC3CE\n5\n4\nOC3M[2:0]\n3\n2\nCC4S[1:0]\nIC4F[3:0]\nrw\nrw\nrw\nrw\nrw\nIC3F[3:0]\nrw\nrw\n0\nCC3S[1:0]\nIC4PSC[1:0]\nrw\n1\nOC3PE OC3FE\nrw\nrw\nrw\nIC3PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode\nBit 15 OC4CE: Output compare 4 clear enable\nBits 14:12 OC4M: Output compare 4 mode\nBit 11 OC4PE: Output compare 4 preload enable\nBit 10 OC4FE: Output compare 4 fast enable\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBit 7 OC3CE: Output compare 3 clear enable\nBits 6:4 OC3M: Output compare 3 mode\nBit 3 OC3PE: Output compare 3 preload enable\nBit 2 OC3FE: Output compare 3 fast enable\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n400/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nInput capture mode\nBits 15:12 IC4F: Input capture 4 filter\nBits 11:10 IC4PSC: Input capture 4 prescaler\nBits 9:8 CC4S: Capture/Compare 4 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC4 channel is configured as output\n01: CC4 channel is configured as input, IC4 is mapped on TI4\n10: CC4 channel is configured as input, IC4 is mapped on TI3\n11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).\nBits 7:4 IC3F: Input capture 3 filter\nBits 3:2 IC3PSC: Input capture 3 prescaler\nBits 1:0 CC3S: Capture/Compare 3 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC3 channel is configured as output\n01: CC3 channel is configured as input, IC3 is mapped on TI3\n10: CC3 channel is configured as input, IC3 is mapped on TI4\n11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).\n15.4.9\nTIMx capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n15\n14\n13 12\nCC4P CC4E\nrw rw\nReserved\n11\n10\n9 8\nCC3P CC3E\nrw rw\nReserved\n7\n6\n5 4\nCC2P CC2E\nrw rw\nReserved\n3\n2\n1 0\nCC1P CC1E\nrw rw\nReserved\nBits 15:14 Reserved, must be kept at reset value.\nBit 13 CC4P: Capture/Compare 4 output polarity\nrefer to CC1P description\nBit 12 CC4E: Capture/Compare 4 output enable\nrefer to CC1E description\nBits 11:10 Reserved, must be kept at reset value.\nBit 9 CC3P: Capture/Compare 3 output polarity\nrefer to CC1P description\nBit 8 CC3E: Capture/Compare 3 output enable\nrefer to CC1E description\nBits 7:6 Reserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output polarity\nrefer to CC1P description\nDoc ID 13902 Rev 14\n401/1096 General-purpose timers (TIM2 to TIM5)\nRM0008\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBits 3:2 Reserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output polarity\nCC1 channel configured as output:\n0: OC1 active high.\n1: OC1 active low.\nCC1 channel configured as input:\nThis bit selects whether IC1 or IC1 is used for trigger or capture operations.\n0: non-inverted: capture is done on a rising edge of IC1. When used as external trigger, IC1\nis non-inverted.\n1: inverted: capture is done on a falling edge of IC1. When used as external trigger, IC1 is\ninverted.\nBit 0 CC1E: Capture/Compare 1 output enable\nCC1 channel configured as output:\n0: Off - OC1 is not active.\n1: On - OC1 signal is output on the corresponding output pin.\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input\ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\nTable 87.\nCCxE bit\nOutput control bit for standard OCx channels\nOCx output state\n0 Output Disabled (OCx=0, OCx_EN=0)\n1 OCx=OCxREF + Polarity, OCx_EN=1\nNote: The state of the external IO pins connected to the standard OCx channels depends on the\nOCx channel state and the GPIO and AFIO registers.\n15.4.10 TIMx counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCNT[15:0]\nrw\nBits 15:0 CNT[15:0]: Counter value\n15.4.11\nTIMx prescaler (TIMx_PSC)\nAddress offset: 0x28\n402/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event.\n15.4.12\nTIMx auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nARR[15:0]\nrw\nrw\nrw\nBits 15:0\nrw\nrw\nrw\nrw\nrw\nrw\nARR[15:0]: Prescaler value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to the Section 15.3.1: Time-base unit on page 352 for more details about ARR update\nand behavior.\nThe counter is blocked while the auto-reload value is null.\nDoc ID 13902 Rev 14\n403/1096 General-purpose timers (TIM2 to TIM5)\n15.4.13\nRM0008\nTIMx capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR1[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register\n(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1).\n15.4.14\nTIMx capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR2[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register\n(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2).\n404/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\n15.4.15\nTIMx capture/compare register 3 (TIMx_CCR3)\nAddress offset: 0x3C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR3[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR3[15:0]: Capture/Compare value\nIf channel CC3 is configured as output:\nCCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register\n(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when\nan update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC3 output.\nIf channel CC3is configured as input:\nCCR3 is the counter value transferred by the last input capture 3 event (IC3).\n15.4.16\nTIMx capture/compare register 4 (TIMx_CCR4)\nAddress offset: 0x40\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR4[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR4[15:0]: Capture/Compare value\n1.\nif CC4 channel is configured as output (CC4S bits):\nCCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR4\nregister (bit OC4PE). Else the preload value is copied in the active capture/compare 4\nregister when an update event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signalled on OC4 output.\n2.\nif CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):\nCCR4 is the counter value transferred by the last input capture 4 event (IC4).\nDoc ID 13902 Rev 14\n405/1096 General-purpose timers (TIM2 to TIM5)\n15.4.17\nRM0008\nTIMx DMA control register (TIMx_DCR)\nAddress offset: 0x48\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\nDBL[4:0]\n2\n1 0\nrw rw\nDBA[4:0]\nReserved\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:13 Reserved, must be kept at reset value.\nBits 12:8 DBL[4:0]: DMA burst length\nThis 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer\nwhen a read or a write access is done to the TIMx_DMAR address).\n00000: 1 transfer,\n00001: 2 transfers,\n00010: 3 transfers,\n...\n10001: 18 transfers.\nBits 7:5 Reserved, must be kept at reset value.\nBits 4:0 DBA[4:0]: DMA base address\nThis 5-bit vector defines the base-address for DMA transfers (when read/write access are\ndone through the TIMx_DMAR address). DBA is defined as an offset starting from the\naddress of the TIMx_CR1 register.\nExample:\n00000: TIMx_CR1,\n00001: TIMx_CR2,\n00010: TIMx_SMCR,\n...\nExample: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this\ncase the transfer is done to/from 7 registers starting from the TIMx_CR1 address..\n15.4.18\nTIMx DMA address for full transfer (TIMx_DMAR)\nAddress offset: 0x4C\nReset value: 0x0000\n15 14 13 12 11 10 9\nrw rw rw rw rw rw rw\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nDMAB[15:0]\nrw\nrw\nBits 15:0 DMAB[15:0]: DMA register for burst accesses\nA read or write operation to the DMAR register accesses the register located at the address\n(TIMx_CR1 address) + (DBA + DMA index) x 4\nwhere TIMx_CR1 address is the address of the control register 1, DBA is the DMA base\naddress configured in TIMx_DCR register, DMA index is automatically controlled by the DMA\ntransfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).\nExample of how to use the DMA burst feature\nIn this example the timer DMA burst feature is used to update the contents of the CCRx\nregisters (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.\n406/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nThis is done in the following steps:\n1.\nConfigure the corresponding DMA channel as follows:\n– DMA channel peripheral address is the DMAR register address\n– DMA channel memory address is the address of the buffer in the RAM containing\nthe data to be transferred by DMA into CCRx registers.\n– Number of data to transfer = 3 (See note below).\n– Circular mode disabled.\n2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:\nDBL = 3 transfers, DBA = 0xE.\n3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).\n4. Enable TIMx\n5. Enable the DMA channel\nNote: This example is for the case where every CCRx register to be updated once. If every CCRx\nregister is to be updated twice for example, the number of data to transfer should be 6. Let's\ntake the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and\ndata6. The data is transferred to the CCRx registers as follows: on the first update DMA\nrequest, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to\nCCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is\ntransferred to CCR3 and data6 is transferred to CCR4.\n15.4.19 TIMx register map\nTIMx registers are mapped as described in the table below:\n0\nDoc ID 13902 Rev 14\n0 0 0 0 0\n0\nCCDS\n0\n0\n0 0 0 0 0\n0\n0\n0\n0\n0\nSMS[2:0]\n0\n0\nReserve\nd\n0 0 0\n0\nTS[2:0]\n0 0\n0\n0 0\n0\n0\n0 0 0\n0 0 0 0 0\nReserved\nReset value\n0\n0 0\nTIMx_EGR\n0x14\n0\nReset value\n0\nReserved\n0\nTIMx_SR\n0x10\n0\nReset value\n0\nReserved\n0\nETF[3:0]\nTIMx_DIER\n0x0C\nETP\nS\n[1:0]\nReset value\nReserved\nTIMx_SMCR\n0x08\nReset value\nMMS[2:0\n]\n0\nReserved\n0\nTIMx_CR2\n0x04\n0\n0\nCMS\n[1:0] 0\nReset value\nCKD\n[1:0]\nReserved\nTIMx_CR1\n0x00\nRegister\nOffset\nTIMx register map and reset values\n8\nTable 88.\n0 0 0 0 0\n407/1096 General-purpose timers (TIM2 to TIM5)\n0\nTIMx_CCER\nReserved\nReset value\n0\n0\n0 0\nCC4\nS\n[1:0] 0 0 0 0\n0\nIC4\nPSC\n[1:0] CC4\nS\n[1:0]\n0 0\n0\n0\n0 0\n0\n0\n0\n0\nOC3M\n[2:0]\n0\n0\n0\nIC3F[3:0]\n0\n0\n0\n0\n0\nIC1\nPSC\n[1:0] CC1\nS\n[1:0]\n0 0 0\nCC3\nS\n[1:0]\n0 0 0\n0\n0\nIC3\nPSC\n[1:0] CC3\nS\n[1:0]\n0 0\n0 0 0 0 0\n0 0 0\n0\n0\n0 0\n0 0 0\n0 0 0 0\n0 0 0 0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\nCNT[15:0]\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nPSC[15:0]\nTIMx_PSC\nReserved\n0x28\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nARR[15:0]\nTIMx_ARR\nReserved\n0x2C\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\n0x30\nCCR1[15:0]\nTIMx_CCR1\nReserved\n0x34\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCCR2[15:0]\nTIMx_CCR2\nReserved\n0x38\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCCR3[15:0]\nTIMx_CCR3\nReserved\n0x3C\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCCR4[15:0]\nTIMx_CCR4\nReserved\n0x40\nReset value\n408/1096\n0\n0\n0 0 0\nTIMx_CNT\n0x24\n0x44\n0\nIC1F[3:0]\n0\n0\nCC2\nS\n[1:0]\n0\nIC4F[3:0]\nIC2\nPSC\n[1:0]\n0\n0\nReserved\nReset value\n0x20\n0\n0\n0\n0\nCC1\nS\n[1:0]\nOC4M\n[2:0]\n0\n0\n0\n0\nOC1M\n[2:0]\nReset value\n0\n0 TIMx_CCMR2\nOutput\nCompare\nmode\nReserved\n0\n0\nReserved\n0\nTIMx_CCMR2\nInput Capture\nmode\n0\nIC2F[3:0]\nReset value\n0x1C\n0\n0\nTIMx_CCMR1\nInput Capture\nmode\n0\nReset value\n0x18\nCC2\nS\n[1:0]\nReserved\nOC2M\n[2:0]\nTIMx_CCMR1\nOutput\nCompare\nmode\nRegister\nOffset\nTIMx register map and reset values\nTable 88.\nRM0008\n0\nReserved\nDoc ID 13902 Rev 14\n0\n0\n0\n0\n0\n0\n0\n0\n0 RM0008\nGeneral-purpose timers (TIM2 to TIM5)\nOffset\nTIMx register map and reset values\nRegister\nTable 88.\nTIMx_DCR\n0x48\nDBL[4:0]\nReset value\n0\n0\n0\nTIMx_DMAR\n0x4C\n0\nDBA[4:0]\nReserve\nd\nReserved\n0\n0 0 0 0 0\n0 0 0 0 0\nDMAB[15:0]\nReserved\nReset value\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n409/1096 General-purpose timers (TIM9 to TIM14)\n16\nRM0008\nGeneral-purpose timers (TIM9 to TIM14)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to XL-density devices only.\n16.1\nTIM9 to TIM14 introduction\nThe TIM9 to TIM14 general-purpose timers consist of a 16-bit auto-reload counter driven by\na programmable prescaler.\nThey may be used for a variety of purposes, including measuring the pulse lengths of input\nsignals (input capture) or generating output waveforms (output compare, PWM).\nPulse lengths and waveform periods can be modulated from a few microseconds to several\nmilliseconds using the timer prescaler and the RCC clock controller prescalers.\nThe TIM9 to TIM14 timers are completely independent, and do not share any resources.\nThey can be synchronized together as described in Section 16.4.12.\n410/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.2 TIM9 to TIM14 main features\n16.2.1 TIM9/TIM12 main features\nThe features of the TIM9/TIM12 general-purpose timers include:\n● 16-bit auto-reload upcounter\n● 16-bit programmable prescaler used to divide the counter clock frequency by any factor\nbetween 1 and 65535 (can be changed “on the fly”)\n● Up to 2 independent channels for:\n– Input capture\n– Output compare\n– PWM generation (edge-aligned mode)\n– One-pulse mode output\n● Synchronization circuit to control the timer with external signals and to interconnect\nseveral timers together\n● Interrupt generation on the following events:\n– Update: counter overflow, counter initialization (by software or internal trigger)\n– Trigger event (counter start, stop, initialization or count by internal trigger)\n– Input capture\n– Output compare\nFigure 146. General-purpose timer block diagram (TIM9 and TIM12)\nInternal clock (CK_INT)\nITR0\nITR1\nTGI\nITR\nITR2\nTRC\nTrigger\ncontroller\nTRGI\nITR3\nTI1F_ED\nSlave\nmode\ncontroller\nReset, Enable, Count\nTI1FP1\nTI2FP2\nU\nAuto-reload register\nStop, Clear\nCK_PSC\nPSC\nCK_CNT\nPrescaler\n+/-\nCNT\nCOUNTER\nCC1I\nCC1I\nTI1\nInput filter &\nEdge detector\nTIMx_CH1\nTI1FP1\nTI1FP2\nIC1\nPrescaler\nTIMx_CH2\nInput filter &\nEdge detector\nCapture/Compare 1 register\nOC1REF\noutput\nOC1\ncontrol\nTRC\nTI2\nIC1PS U\nUI\nU\nTI2FP1\nTI2FP2\nCC2I\nIC2\nCC2I\nIC2PS U\nPrescaler\nTIMx_CH1\nCapture/Compare 2 register\nOC2REF\noutput\nOC2\nTIMx_CH2\ncontrol\nTRC\nNotes:\nReg\nPreload registers transferred\nto active registers on U event\naccording to control bit\nevent\ninterrupt\nai17190\nDoc ID 13902 Rev 14\n411/1096 General-purpose timers (TIM9 to TIM14)\n16.3\nRM0008\nTIM10/TIM11 and TIM13/TIM14 main features\nThe features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include:\n● 16-bit auto-reload upcounter\n● 16-bit programmable prescaler used to divide the counter clock frequency by any factor\nbetween 1 and 65535 (can be changed “on the fly”)\n● independent channel for:\n●\n– Input capture\n– Output compare\n– PWM generation (edge-aligned mode)\nInterrupt generation on the following events:\n– Update: counter overflow, counter initialization (by software)\n– Input capture\n– Output compare\nFigure 147. General-purpose timer block diagram (TIM10/11/13/14)\n)NTERNAL RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.4 TIM9 to TIM14 functional description\n16.4.1 Time-base unit\nThe main block of the programmable advanced-control timer is a 16-bit counter with its\nrelated auto-reload register. The counter can count up. The counter clock can be divided by\na prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by\nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n● Counter register (TIMx_CNT)\n● Prescaler register (TIMx_PSC)\n● Auto-reload register (TIMx_ARR)\nThe auto-reload register is preloaded. Writing to or reading from the auto-reload register\naccesses the preload register. The content of the preload register are transferred into the\nshadow register permanently or at each update event (UEV), depending on the auto-reload\npreload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter\nreaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be\ngenerated by software. The generation of the update event is described in detailed for each\nconfiguration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the\ncounter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller\ndescription to get more details on counter enabling).\nNote that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1\nregister.\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It\nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).\nIt can be changed on the fly as this control register is buffered. The new prescaler ratio is\ntaken into account at the next update event.\nFigure 149 and Figure 150 give some examples of the counter behavior when the prescaler\nratio is changed on the fly.\nDoc ID 13902 Rev 14\n413/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 148. Counter timing diagram with prescaler division change from 1 to 2\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\n02\n03\nUpdate event (UEV)\nPrescaler control register\n0\n1\nWrite a new value in TIMx_PSC\nPrescaler buffer 0\nPrescaler counter 0\n1\n0\n1\n0\n1\n0\n1\n0\n1\nFigure 149. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\nUpdate event (UEV)\nPrescaler control register\n0\n3\nWrite a new value in TIMx_PSC\n16.4.2\nPrescaler buffer 0\nPrescaler counter 0\n3\n0\n1\n2\n3\n0\n1\n2\n3\nCounter modes\nUpcounting mode\nIn upcounting mode, the counter counts from 0 to the auto-reload value (content of the\nTIMx_ARR register), then restarts from 0 and generates a counter overflow event.\nSetting the UG bit in the TIMx_EGR register (by software or by using the slave mode\ncontroller on TIM9 and TIM12) also generates an update event.\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1\nregister. This is to avoid updating the shadow registers while writing new values in the\npreload registers. Then no update event occurs until the UDIS bit has been written to 0.\nHowever, the counter restarts from 0, as well as the counter of the prescaler (but the\nprescale rate does not change). In addition, if the URS bit (update request selection) in\nTIMx_CR1 register is set, setting the UG bit generates an update event UEV but without\n414/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nsetting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and\ncapture interrupts when clearing the counter on the capture event.\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nTIMx_SR register) is set (depending on the URS bit):\n● The auto-reload shadow register is updated with the preload value (TIMx_ARR),\n● The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC\nregister).\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR=0x36.\nFigure 150. Counter timing diagram, internal clock divided by 1\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 151. Counter timing diagram, internal clock divided by 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035 0036\n0000\n0001\n0002\n0003\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n415/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 152. Counter timing diagram, internal clock divided by 4\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0035\n0000\n0036\n0001\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 153. Counter timing diagram, internal clock divided by N\nCK_PSC\nTimer clock = CK_CNT\nCounter register\n1F\n00\n20\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not\npreloaded)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\nWrite a new value in TIMx_ARR\n416/1096\nDoc ID 13902 Rev 14\n36 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nFigure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded)\nCK_PSC\nCEN\nTimer clock = CK_CNT\nCounter register\nF0\nF1 F2 F3 F4 F5 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register F5 36\nAuto-reload shadow register F5 36\nWrite a new value in TIMx_ARR\n16.4.3\nClock selection\nThe counter clock can be provided by the following clock sources:\n● Internal clock (CK_INT)\n● External clock mode1 (for TIM9 and TIM12): external input pin (TIx)\n● Internal trigger inputs (ITRx) (for TIM9 and TIM12): connecting the trigger output from\nanother timer. Refer to Section : Using one timer as prescaler for another for more\ndetails.\nInternal clock source (CK_INT)\nThe internal clock source is the default clock source for TIM10/TIM11 and TIM13/TIM14.\nFor TIM9 and TIM12, the internal clock source is selected when the slave mode controller is\ndisabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the\nTIMx_EGR register are then used as control bits and can be changed only by software\n(except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the\nprescaler is clocked by the internal clock CK_INT.\nFigure 156 shows the behavior of the control circuit and the upcounter in normal mode,\nwithout prescaler.\nDoc ID 13902 Rev 14\n417/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 156. Control circuit in normal mode, internal clock divided by 1\nInternal clock\nCEN=CNT_EN\nUG\nCNT_INIT\nCounter clock = CK_CNT = CK_PSC\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nExternal clock source mode 1( TIM9 and TIM12)\nThis mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count\nat each rising or falling edge on a selected input.\nFigure 157. TI2 external clock connection example\nTIMx_SMCR\nTS[2:0]\nor\nITRx\nTI1_ED\nTI2\nFilter\nICF[3:0]\nTIMx_CCMR1\nTI2F_Rising 0\nEdge\nDetector TI2F_Falling\n1\nor\nor\n0xx\n100\nTI1FP1 101\nTI2FP2 110\nCC2P\nTI2F\nTI1F\nTRGI\nexternal clock\nmode 1\nCK_PSC\nCK_INT\ninternal clock\nmode\n(internal clock)\nTIMx_CCER\nSMS[2:0]\nTIMx_SMCR\nFor example, to configure the upcounter to count in response to a rising edge on the TI2\ninput, use the following procedure:\nNote:\n1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in\nthe TIMx_CCMR1 register.\n2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1\nregister (if no filter is needed, keep IC2F=’0000’).\n3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER\nregister.\n4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR\nregister.\n5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.\n6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register.\nThe capture prescaler is not used for triggering, so you don’t need to configure it.\nWhen a rising edge occurs on TI2, the counter counts once and the TIF flag is set.\nThe delay between the rising edge on TI2 and the actual clock of the counter is due to the\nresynchronization circuit on TI2 input.\n418/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nFigure 158. Control circuit in external clock mode 1\nTI2\nCNT_EN\nCounter clock = CK_CNT = CK_PSC\nCounter register\n34\n35\n36\nTIF\nWrite TIF=0\n16.4.4\nCapture/compare channels\nEach Capture/Compare channel is built around a capture/compare register (including a\nshadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and\nan output stage (with comparator and output control).\nFigure 159 to Figure 161 give an overview of one capture/compare channel.\nThe input stage samples the corresponding TIx input to generate a filtered signal TIxF.\nThen, an edge detector with polarity selection generates a signal (TIxFPx) which can be\nused as trigger input by the slave mode controller or as the capture command. It is\nprescaled before the capture register (ICxPS).\nFigure 159. Capture/compare channel (example: channel 1 input stage)\nTI1F_ED\nto the slave mode controller\nTI1\nf DTS\nfilter\ndowncounter\nICF[3:0]\nTIMx_CCMR1\nTI1F\nTI1F_Rising\nEdge\nDetector\nTI1F_Falling\n0\n1\nCC1P/CC1NP\n(from channel 2)\nTI2FP1\n01\n10\nIC1\ndivider\n/1, /2, /4, /8\nIC1PS\nTRC\n11\n(from slave mode\ncontroller)\nTIMx_CCER\nTI2F_rising\n(from channel 2)\nTI2F_falling\nTI1FP1\n0\nCC1S[1:0] ICPS[1:0]\n1\nTIMx_CCMR1\nCC1E\nTIMx_CCER\nThe output stage generates an intermediate waveform which is then used for reference:\nOCxRef (active high). The polarity acts at the end of the chain.\nDoc ID 13902 Rev 14\n419/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 160. Capture/compare channel 1 main circuit\nAPB Bus\nread CCR1L\nread_in_progress\n8\nread CCR1H S\n8\nMCU-peripheral interface\nwrite_in_progress\nCapture/compare preload register\nR\nR\ncompare_transfer\ncapture_transfer\ninput\nmode\nCC1S[1]\nCC1S[0]\noutput\nmode\nCapture/compare shadow register\nIC1PS\ncomparator\ncapture\nCC1E\nS write CCR1H\nwrite CCR1L\nCC1S[1]\nCC1S[0]\nOC1PE\nOC1PE\nUEV\nTIM1_CCMR1\n(from time\nbase unit)\nCNT>CCR1\nCounter\nCC1G\nCNT=CCR1\nTIM1_EGR\nFigure 161. Output stage of capture/compare channel (channel 1)\n4O RM0008\nGeneral-purpose timers (TIM9 to TIM14)\ncleared by software by writing it to ‘0’ or by reading the captured data stored in the\nTIMx_CCRx register. CCxOF is cleared when you write it to ‘0’.\nThe following example shows how to capture the counter value in TIMx_CCR1 when TI1\ninput rises. To do this, use the following procedure:\n1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S\nbits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,\nthe channel is configured in input mode and the TIMx_CCR1 register becomes read-\nonly.\n2. Program the input filter duration you need with respect to the signal you connect to the\ntimer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s\nimagine that, when toggling, the input signal is not stable during at must 5 internal clock\ncycles. We must program a filter duration longer than these 5 clock cycles. We can\nvalidate a transition on TI1 when 8 consecutive samples with the new level have been\ndetected (sampled at f DTS frequency). Then write IC1F bits to ‘0011’ in the\nTIMx_CCMR1 register.\n3. Select the edge of the active transition on the TI1 channel by programming CC1P and\nCC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).\n4. Program the input prescaler. In our example, we wish the capture to be performed at\neach valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the\nTIMx_CCMR1 register).\n5. Enable capture from the counter into the capture register by setting the CC1E bit in the\nTIMx_CCER register.\n6. If needed, enable the related interrupt request by setting the CC1IE bit in the\nTIMx_DIER register.\nWhen an input capture occurs:\n● The TIMx_CCR1 register gets the value of the counter on the active transition.\n● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures\noccurred whereas the flag was not cleared.\n● An interrupt is generated depending on the CC1IE bit.\nIn order to handle the overcapture, it is recommended to read the data before the\novercapture flag. This is to avoid missing an overcapture which could happen after reading\nthe flag and before reading the data.\nNote: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in\nthe TIMx_EGR register.\n16.4.6 PWM input mode (only for TIM9/12)\nThis mode is a particular case of input capture mode. The procedure is the same except:\n● Two ICx signals are mapped on the same TIx input.\n● These 2 ICx signals are active on edges with opposite polarity.\n● One of the two TIxFP signals is selected as trigger input and the slave mode controller\nis configured in reset mode.\nFor example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in\nTIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending\non CK_INT frequency and prescaler value):\nDoc ID 13902 Rev 14\n421/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\n1. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1\nregister (TI1 selected).\n2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter\nclear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).\n3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1\nregister (TI1 selected).\n4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the\nCC2P and CC2NP bits to ‘11’ (active on falling edge).\n5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register\n(TI1FP1 selected).\n6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the\nTIMx_SMCR register.\n7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.\nFigure 162. PWM input mode timing\nTI1\nTIMx_CNT\n0004\n0000\n0001\n0002\nTIMx_CCR1 0004\nTIMx_CCR2 0002\nIC1 capture\nIC2 capture\nreset counter\n0003\n0004\nIC2 capture\npulse width\nmeasurement\n0000\nIC1 capture\nperiod\nmeasurement\nai15413\n1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only\nTI1FP1 and TI2FP2 are connected to the slave mode controller.\n16.4.7\nForced output mode\nIn output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal\n(OCxREF and then OCx) can be forced to active or inactive level directly by software,\nindependently of any comparison between the output compare register and the counter.\nTo force an output compare signal (OCXREF/OCx) to its active level, you just need to write\n‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced\nhigh (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.\nFor example: CCxP=’0’ (OCx active high) => OCx is forced to high level.\nThe OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the TIMx_CCMRx\nregister.\nAnyway, the comparison between the TIMx_CCRx shadow register and the counter is still\nperformed and allows the flag to be set. Interrupt requests can be sent accordingly. This is\ndescribed in the output compare mode section below.\n422/1096\nDoc ID 13902 Rev 14 RM0008\n16.4.8\nGeneral-purpose timers (TIM9 to TIM14)\nOutput compare mode\nThis function is used to control an output waveform or indicating when a period of time has\nelapsed.\nWhen a match is found between the capture/compare register and the counter, the output\ncompare function:\n1. Assigns the corresponding output pin to a programmable value defined by the output\ncompare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP\nbit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set\nactive (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on\nmatch.\n2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).\n3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the\nTIMx_DIER register).\nThe TIMx_CCRx registers can be programmed with or without preload registers using the\nOCxPE bit in the TIMx_CCMRx register.\nIn output compare mode, the update event UEV has no effect on OCxREF and OCx output.\nThe timing resolution is one count of the counter. Output compare mode can also be used to\noutput a single pulse (in One-pulse mode).\nProcedure:\n1. Select the counter clock (internal, external, prescaler).\n2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.\n3. Set the CCxIE bit if an interrupt request is to be generated.\n4. Select the output mode. For example:\n5.\n– Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx\n– Write OCxPE = ‘0’ to disable preload register\n– Write CCxP = ‘0’ to select active high polarity\n– Write CCxE = ‘1’ to enable the output\nEnable the counter by setting the CEN bit in the TIMx_CR1 register.\nThe TIMx_CCRx register can be updated at any time by software to control the output\nwaveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx\nshadow register is updated only at the next update event UEV). An example is given in\nFigure 163.\nDoc ID 13902 Rev 14\n423/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 163. Output compare mode, toggle on OC1.\nWrite B201h in the CC1R register\nTIM1_CNT\n0039\n003A\nTIM1_CCR1\n003B\n003A\nB200\nB201\nB201\noc1ref=OC1\nMatch detected on CCR1\nInterrupt generated if enabled\n16.4.9\nPWM mode\nPulse Width Modulation mode allows you to generate a signal with a frequency determined\nby the value of the TIMx_ARR register and a duty cycle determined by the value of the\nTIMx_CCRx register.\nThe PWM mode can be selected independently on each channel (one PWM per OCx\noutput) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the\nTIMx_CCMRx register. You must enable the corresponding preload register by setting the\nOCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in\nupcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.\nAs the preload registers are transferred to the shadow registers only when an update event\noccurs, before starting the counter, you have to initialize all the registers by setting the UG\nbit in the TIMx_EGR register.\nThe OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.\nIt can be programmed as active high or active low. The OCx output is enabled by the CCxE\nbit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more\ndetails.\nIn PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine\nwhether TIMx_CNT ≤ TIMx_CCRx.\nThe timer is able to generate PWM in edge-aligned mode only since the counter is\nupcounting.\nPWM edge-aligned mode\nIn the following example, we consider PWM mode 1. The reference PWM signal OCxREF is\nhigh as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in\nTIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at\n‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 164 shows some edge-\naligned PWM waveforms in an example where TIMx_ARR=8.\n424/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nFigure 164. Edge-aligned PWM waveforms (ARR=8)\nCounter register\nCCRx=4\n0\n1\n2\n3\n4\n5\n6\n7\n8\n0\n1\nOCXREF\nCCxIF\nOCXREF\nCCRx=8\nCCxIF\nOCXREF ‚Äò\nCCRx>8\nCCxIF\nOCXREF ‚Äò\nCCRx=0\nCCxIF\nOne-pulse mode (only for TIM9/12)\nOne-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to\nbe started in response to a stimulus and to generate a pulse with a programmable length\nafter a programmable delay.\nStarting the counter can be controlled through the slave mode controller. Generating the\nwaveform can be done in output compare mode or PWM mode. You select One-pulse mode\nby setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically\nat the next update event UEV.\nA pulse can be correctly generated only if the compare value is different from the counter\ninitial value. Before starting (when the timer is waiting for the trigger), the configuration must\nbe as follows:\nCNT < CCRx≤ ARR (in particular, 0 < CCRx)\nFigure 165. Example of one pulse mode.\nTI2\nOC1REF\nOC1\n16.4.10\nTIM1_ARR\nTIM1_CCR1\n0\nt DELAY\nt PULSE\nDoc ID 13902 Rev 14\nt\n425/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFor example you may want to generate a positive pulse on OC1 with a length of t PULSE and\nafter a delay of t DELAY as soon as a positive edge is detected on the TI2 input pin.\nUse TI2FP2 as trigger 1:\n1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.\n2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER\nregister.\n3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in\nthe TIMx_SMCR register.\n4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register\n(trigger mode).\nThe OPM waveform is defined by writing the compare registers (taking into account the\nclock frequency and the counter prescaler).\n● The t DELAY is defined by the value written in the TIMx_CCR1 register.\n● The t PULSE is defined by the difference between the auto-reload value and the compare\nvalue (TIMx_ARR - TIMx_CCR1).\n● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare\nmatch occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload\nvalue. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1\nregister. You can optionally enable the preload registers by writing OC1PE=’1’ in the\nTIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to\nwrite the compare value in the TIMx_CCR1 register, the auto-reload value in the\nTIMx_ARR register, generate an update by setting the UG bit and wait for external\ntrigger event on TI2. CC1P is written to ‘0’ in this example.\nYou only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1\nregister to stop the counter at the next update event (when the counter rolls over from the\nauto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the\nRepetitive Mode is selected.\nParticular case: OCx fast enable\nIn One-pulse mode, the edge detection on TIx input set the CEN bit which enables the\ncounter. Then the comparison between the counter and the compare value makes the\noutput toggle. But several clock cycles are needed for these operations and it limits the\nminimum delay t DELAY min we can get.\nIf you want to output a waveform with the minimum delay, you can set the OCxFE bit in the\nTIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,\nwithout taking in account the comparison. Its new level is the same as if a compare match\nhad occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.\n16.4.11\nTIM9/12 external trigger synchronization\nThe TIM9/12 timers can be synchronized with an external trigger in several modes: Reset\nmode, Gated mode and Trigger mode.\nSlave mode: Reset mode\nThe counter and its prescaler can be reinitialized in response to an event on a trigger input.\nMoreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is\ngenerated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.\nIn the following example, the upcounter is cleared in response to a rising edge on TI1 input:\n426/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register.\nProgram CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and\ndetect rising edges only).\n2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select\nTI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register.\nThe counter starts counting on the internal clock, then behaves normally until TI1 rising\nedge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the\ntrigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if\nenabled (depending on the TIE bit in TIMx_DIER register).\nThe following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.\nThe delay between the rising edge on TI1 and the actual reset of the counter is due to the\nresynchronization circuit on TI1 input.\nFigure 166. Control circuit in reset mode\nTI1\nUG\nCounter clock = ck_cnt = ck_psc\nCounter register\n30 31 32 33 34 35 36 00 01 02 03 00 01 02 03\nTIF\nSlave mode: Gated mode\nThe counter can be enabled depending on the level of a selected input.\nIn the following example, the upcounter counts only when TI1 input is low:\n1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC1S bits\nselect the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program\nCC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect\nlow level only).\n2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.\nSelect TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.\n3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the\ncounter doesn’t start if CEN=’0’, whatever is the trigger input level).\nThe counter starts counting on the internal clock as long as TI1 is low and stops as soon as\nTI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts\nor stops.\nThe delay between the rising edge on TI1 and the actual stop of the counter is due to the\nresynchronization circuit on TI1 input.\nDoc ID 13902 Rev 14\n427/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nFigure 167. Control circuit in gated mode\nTI1\ncnt_en\nCounter clock = ck_cnt = ck_psc\nCounter register\n30 31 32 33\n34\n35 36 37 38\nTIF\nWrite TIF=0\nSlave mode: Trigger mode\nThe counter can start in response to an event on a selected input.\nIn the following example, the upcounter starts in response to a rising edge on TI2 input:\n1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration\n(in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture\nprescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are\nconfigured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register.\nProgram CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and\ndetect low level only).\n2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register.\nSelect TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.\nWhen a rising edge occurs on TI2, the counter starts counting on the internal clock and the\nTIF flag is set.\nThe delay between the rising edge on TI2 and the actual start of the counter is due to the\nresynchronization circuit on TI2 input.\nFigure 168. Control circuit in trigger mode\nTI2\ncnt_en\nCounter clock = ck_cnt = ck_psc\nCounter register\n34\nTIF\n428/1096\nDoc ID 13902 Rev 14\n35 36 37 38 RM0008\n16.4.12\nGeneral-purpose timers (TIM9 to TIM14)\nTimer synchronization (TIM9/12)\nThe TIM timers are linked together internally for timer synchronization or chaining. Refer to\nSection 15.3.15: Timer synchronization on page 382 for details.\n16.4.13\nDebug mode\nWhen the microcontroller enters debug mode (Cortex™-M3 core halted), the TIMx counter\neither continues to work normally or stops, depending on DBG_TIMx_STOP configuration\nbit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,\nwatchdog, bxCAN and I2C.\nDoc ID 13902 Rev 14\n429/1096 General-purpose timers (TIM9 to TIM14)\n16.5\nRM0008\nTIM9 and TIM12 registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\n16.5.1\nTIM9/12 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\nCKD[1:0]\n7\n6\n5\nARPE\nReserved\n4\n3 2 1 0\nOPM URS UDIS CEN\nrw rw rw rw\nreserved\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and\nsampling clock used by the digital filters (TIx),\n00: t DTS = t CK_INT\n01: t DTS = 2 × t CK_INT\n10: t DTS = 4 × t CK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped on the update event\n1: Counter stops counting on the next update event (clearing the CEN bit).\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt if enabled:\n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an update interrupt if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update event (UEV) generation.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,\nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n430/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.5.2\nTIM9/12 slave mode control register (TIMx_SMCR)\nAddress offset: 0x08\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\nTS[2:0]\n1\n0\nSMS[2:0]\nReserved\nRes.\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 TS: Trigger selection\nThis bitfield selects the trigger input to be used to synchronize the counter.\n000: Internal Trigger 0 (ITR0)\n001: Internal Trigger 1 (ITR1)\n010: Internal Trigger 2 (ITR2)\n011: Internal Trigger 3 (ITR3)\n100: TI1 Edge Detector (TI1F_ED)\n101: Filtered Timer Input 1 (TI1FP1)\n110: Filtered Timer Input 2 (TI2FP2)\n111: Reserved.\nSee Table 89: TIMx internal trigger connection on page 432 for more details on the meaning\nof ITRx for each timer.\nNote: These bits must be changed only when they are not used (e.g. when SMS=’000’) to\navoid wrong edge detections at the transition.\nBit 3 Reserved, must be kept at reset value.\nBits 2:0 SMS: Slave mode selection\nWhen external signals are selected, the active edge of the trigger signal (TRGI) is linked to\nthe polarity selected on the external input (see Input control register and Control register\ndescriptions.\n000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal\nclock\n001: Reserved\n010: Reserved\n011: Reserved\n100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter\nand generates an update of the registers\n101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The\ncounter stops (but is not reset) as soon as the trigger becomes low. Counter starts and\nstops are both controlled\n110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not\nreset). Only the start of the counter is controlled\n111: External clock mode 1 - Rising edges of the selected trigger (TRGI) clock the counter\nNote: The Gated mode must not be used if TI1F_ED is selected as the trigger input\n(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the\nGated mode checks the level of the trigger signal.\nDoc ID 13902 Rev 14\n431/1096 General-purpose timers (TIM9 to TIM14)\nTable 89.\n16.5.3\nRM0008\nTIMx internal trigger connection\nSlave TIM ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’)\nTIM2 TIM1 TIM8 TIM3 TIM4\nTIM3 TIM1 TIM2 TIM5 TIM4\nTIM4 TIM1 TIM2 TIM3 TIM8\nTIM5 TIM2 TIM3 TIM4 TIM8\nTIM9 TIM2 TIM3 TIM10 TIM11\nTIM12 TIM4 TIM5 TIM13 TIM14\nTIM9/12 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\nTIE\nReserved\nReserved, must be kept at reset value.\nBit 6 TIE: Trigger interrupt enable\n0: Trigger interrupt disabled.\n1: Trigger interrupt enabled.\nBit 5:3\nReserved, must be kept at reset value.\nBit 2 CC2IE: Capture/Compare 2 interrupt enable\n0: CC2 interrupt disabled.\n1: CC2 interrupt enabled.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled.\n1: CC1 interrupt enabled.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\n432/1096\n2 1 0\nCC2IE CC1IE UIE\nrw rw rw\nRes\nrw\nBit 15:7\n3\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.5.4\nTIM9/12 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\nCC2OF CC1OF\nReserved\nReserved\nrc_w0\nBit 15:11\n6\n5\n4\nTIF\nrc_w0\n3\n2 1 0\nCC2IF CC1IF UIF\nrc_w0 rc_w0 rc_w0\nReserved\nrc_w0\nReserved, must be kept at reset value.\nBit 10 CC2OF: Capture/compare 2 overcapture flag\nrefer to CC1OF description\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input\ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was\nalready set\nBits 8:7\nReserved, must be kept at reset value.\nBit 6 TIF: Trigger interrupt flag\nThis flag is set by hardware on trigger event (active edge detected on TRGI input when the\nslave mode controller is enabled in all modes but gated mode. It is set when the counter\nstarts or stops when gated mode is selected. It is cleared by software.\n0: No trigger event occurred.\n1: Trigger interrupt pending.\nBit 5:3\nReserved, must be kept at reset value.\nBit 2 CC2IF: Capture/Compare 2 interrupt flag\nrefer to CC1IF description\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by\nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.\nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF\nbit goes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the\nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected\non IC1 which matches the selected polarity).\nDoc ID 13902 Rev 14\n433/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–At overflow and if UDIS=’0’ in the TIMx_CR1 register.\n–When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’\nand UDIS=’0’ in the TIMx_CR1 register.\n–When CNT is reinitialized by a trigger event (refer to the synchro control register\ndescription), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n16.5.5\nTIM9/12 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\nTG\nReserved\n3\n2 1 0\nCC2G CC1G UG\nw w w\nReserved\nw\nBits 15:7 Reserved, must be kept at reset value.\nBit 6 TG: Trigger generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled\nBits 5:3 Reserved, must be kept at reset value.\nBit 2 CC2G: Capture/compare 2 generation\nrefer to CC1G description\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software to generate an event, it is automatically cleared by hardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nthe CC1IF flag is set, the corresponding interrupt is sent if enabled.\nIf channel CC1 is configured as input:\nThe current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the\ncorresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was\nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initializes the counter and generates an update of the registers. The prescaler counter\nis also cleared and the prescaler ratio is not affected. The counter is cleared.\n434/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.5.6\nTIM9/12 capture/compare mode register 1 (TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The\ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other\nbits in this register have different functions in input and output modes. For a given bit, OCxx\ndescribes its function when the channel is configured in output mode, ICxx describes its\nfunction when the channel is configured in input mode. So you must take care that the same\nbit can have different meanings for the input stage and the output stage.\n15\n14\nOC2CE\n13\n12\nOC2M[2:0]\n11\n10\n9\n8\nOC2PE OC2FE\n7\n6\nOC1CE\n5\n4\nOC1M[2:0]\n3\n2\nCC2S[1:0]\nIC2F[3:0]\nrw\nrw\nrw\nrw\nrw\nIC1F[3:0]\nrw\nrw\n0\nCC1S[1:0]\nIC2PSC[1:0]\nrw\n1\nOC1PE OC1FE\nrw\nrw\nrw\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode\nBit 15 OC2CE: Output compare 2 clear enable\nBits 14:12 OC2M[2:0]: Output compare 2 mode\nBit 11 OC2PE: Output compare 2 preload enable\nBit 10 OC2FE: Output compare 2 fast enable\nBits 9:8 CC2S[1:0]: Capture/Compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an\ninternal trigger input is selected through the TS bit (TIMx_SMCR register\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBit 7 OC1CE: Output compare 1 clear enable\nOC1CE: Output Compare 1 Clear Enable\n0: OC1Ref is not affected by the ETRF input\n1: OC1Ref is cleared as soon as a High level is detected on ETRF input\nDoc ID 13902 Rev 14\n435/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 and\nOC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N\ndepend on the CC1P and CC1NP bits, respectively.\n000: Frozen - The comparison between the output compare register TIMx_CCR1 and the\ncounter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing\nbase).\n001: Set channel 1 to active level on match. The OC1REF signal is forced high when the\nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the\nTIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1\n100: Force inactive level - OC1REF is forced low\n101: Force active level - OC1REF is forced high\n110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1\nelse it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as\nTIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’)\n111: PWM mode 2 - In upcounting, channel 1 is inactive as long as\nTIMx_CNT<TIMx_CCR1 else it is active. In downcounting, channel 1 is active as long as\nTIMx_CNT>TIMx_CCR1 else it is inactive.\nNote: In PWM mode 1 or 2, the OCREF level changes only when the result of the\ncomparison changes or when the output compare mode switches from “frozen” mode\nto “PWM” mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the\nnew value is taken into account immediately\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload\nregister. TIMx_CCR1 preload value is loaded into the active register at each update event\nNote: The PWM mode can be used without validating the preload register only in one-pulse\nmode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed.\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on the counter and CCR1 values even when the\ntrigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the\ntrigger input is 5 clock cycles\n1: An active edge on the trigger input acts like a compare match on the CC1 output. Then,\nOC is set to the compare level independently of the result of the comparison. Delay to\nsample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE\nacts only if the channel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an\ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n436/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nInput capture mode\nBits 15:12 IC2F: Input capture 2 filter\nBits 11:10 IC2PSC[1:0]: Input capture 2 prescaler\nBits 9:8 CC2S: Capture/compare 2 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input.\n00: CC2 channel is configured as output\n01: CC2 channel is configured as input, IC2 is mapped on TI2\n10: CC2 channel is configured as input, IC2 is mapped on TI1\n11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an\ninternal trigger input is selected through the TS bit (TIMx_SMCR register)\nNote: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).\nBits 7:4 IC1F: Input capture 1 filter\nThis bitfield defines the frequency used to sample the TI1 input and the length of the digital\nfilter applied to TI1. The digital filter is made of an event counter in which N events are\nneeded to validate a transition on the output:\n1000: f SAMPLING =f DTS /8, N=6\n0000: No filter, sampling is done at f DTS\n1001: f SAMPLING =f DTS /8, N=8\n0001: f SAMPLING =f CK_INT , N=2\n0010: f SAMPLING =f CK_INT , N=4\n1010: f SAMPLING =f DTS /16, N=5\n1011: f SAMPLING =f DTS /16, N=6\n0011: f SAMPLING =f CK_INT , N=8\n1100: f SAMPLING =f DTS /16, N=8\n0100: f SAMPLING =f DTS /2, N=6\n0101: f SAMPLING =f DTS /2, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n0110: f SAMPLING =f DTS /4, N=6\n1111: f SAMPLING =f DTS /32, N=8\n0111: f SAMPLING =f DTS /4, N=8\nNote: In the current silicon revision, f DTS is replaced in the formula by CK_INT when\nICxF[3:0]= 1, 2 or 3.\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bitfield defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\nDoc ID 13902 Rev 14\n437/1096 General-purpose timers (TIM9 to TIM14)\n16.5.7\nRM0008\nTIM9/12 capture/compare enable register (TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\nCC2NP\nReserved\n5 4 3\nCC2P CC2E CC1NP\nrw rw rw\nRes.\nrw\n2\n1 0\nCC1P CC1E\nrw rw\nRes.\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 CC2NP: Capture/Compare 2 output Polarity\nrefer to CC1NP description\nBits 6 Reserved, must be kept at reset value.\nBit 5 CC2P: Capture/Compare 2 output Polarity\nrefer to CC1P description\nBit 4 CC2E: Capture/Compare 2 output enable\nrefer to CC1E description\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity\nCC1 channel configured as output: CC1NP must be kept cleared\nCC1 channel configured as input: CC1NP is used in conjunction with CC1P to define\nTI1FP1/TI2FP1 polarity (refer to CC1P description).\nBits 2 Reserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high.\n1: OC1 active low.\nCC1 channel configured as input:\nCC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger\nmode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).\n01: inverted/falling edge\nCircuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger\nmode), TIxFP1 is inverted (trigger in gated mode, encoder mode).\n10: reserved, do not use this configuration.\nNote: 11: noninverted/both edges\nCircuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,\nexternal clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This\nconfiguration must not be used for encoder mode.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active.\n1: On - OC1 signal is output on the corresponding output pin.\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input\ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled.\n1: Capture enabled.\n438/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\nTable 90.\nOutput control bit for standard OCx channels\nCCxE bit\nOCx output state\n0 Output disabled (OCx=’0’, OCx_EN=’0’)\n1 OCx=OCxREF + Polarity, OCx_EN=’1’\nNote: The states of the external I/O pins connected to the standard OCx channels depend on the\nstate of the OCx channel and on the GPIO registers.\n16.5.8 TIM9/12 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000 0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw rw\n7 6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n16.5.9\nTIM9/12 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\nPSC[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded into the active prescaler register at each update event.\n16.5.10\nTIM9/12 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0x0000 0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to the Section 16.4.1: Time-base unit on page 413 for more details about ARR update\nand behavior.\nThe counter is blocked while the auto-reload value is null.\nDoc ID 13902 Rev 14\n439/1096 General-purpose timers (TIM9 to TIM14)\n16.5.11\nRM0008\nTIM9/12 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR1[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register\n(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register\nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT\ncounter and signaled on the OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1).\n16.5.12\nTIM9/12 capture/compare register 2 (TIMx_CCR2)\nAddress offset: 0x38\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR2[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR2[15:0]: Capture/Compare 2 value\nIf channel CC2 is configured as output:\nCCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register\n(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register\nwhen an update event occurs.\nThe active capture/compare register contains the value to be compared to the TIMx_CNT\ncounter and signalled on the OC2 output.\nIf channel CC2 is configured as input:\nCCR2 is the counter value transferred by the last input capture 2 event (IC2).\n16.5.13\nTIM9/12 register map\nTIM9/12 registers are mapped as 16-bit addressable registers as described below:\n0x08\nTIMx_SMCR\nReserved\nReset value\n440/1096\nTS[2:0]\n0\nDoc ID 13902 Rev 14\n0\n0\n0\n0\n0\n0\nReset value\nCKD\n[1:0]\nReserved\nTIMx_CR1\n0x00\nTIM9/12 register map and reset values\nRegister\nOffset\nTable 91.\n0 0 0\nSMS[2:0]\n0\n0\n0 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n0\n0\n0\nIC2F[3:0]\nReserved\n0\n0\n0\n0\n0\n0 0\n0\nCC1S\n[1:0]\n0\n0 0 0\n0 0 0\nTIMx_ARR\n0\nTIMx_PSC\n0 0 0\n0 0 0\n0 0 0 0\n0 0 0 0 0\n0 0 0 0 0 0\n0 0 0 0 0 0\nCNT[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nPSC[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nARR[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\nTIMx_CCR1\nCCR1[15:0]\nReserved\nReset value\nTIMx_CCR2\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nCCR2[15:0]\nReserved\nReset value\n0x3C to\n0x4C\n0\nTIMx_CNT\n0\nReserved\n0x30\n0x38\n0\n0 0 0 0\nIC1\nCC1S\nPSC\n[1:0]\n[1:0]\n0 0 0 0\nTIMx_CCER\nReset value\n0x34\n0 0 0 0\n0 0 0\nIC2\nCC2S\nPSC\nIC1F[3:0]\n[1:0]\n[1:0]\n0 0 0 0 0 0 0 0\n0\nReserved\nReset value\n0x2C\nOC1M\n[2:0]\n0\nCC2S\n[1:0]\n0\nOC2M\n[2:0]\nReserved\nReset value\n0x28\n0\nReset value\n0x24\n0\nReserved\n0x1C\n0x20\n0\nReset value\nTIMx_CCMR1\nOutput Compare\nmode\nReset value\nTIMx_CCMR1\nInput Capture\nmode\nReset value\n0\n0x18\nTIMx_EGR\n0x14\nReset value\nReserved\nTIMx_SR\n0x10\n0\nReserved\nReset value\nTIMx_DIER\n0x0C\nRegister\nOffset\nTIM9/12 register map and reset values (continued)\nTable 91.\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nReserved\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n441/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\n16.6 TIM10/11/13/14 registers\n16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\nCKD[1:0]\n7\n6\n5\n4\nARPE\nReserved\n3\n2 1 0\nURS UDIS CEN\nrw rw rw\nReserved\nrw\nrw\nrw\nBits 15:10 Reserved, must be kept at reset value.\nBits 9:8 CKD: Clock division\nThis bit-field indicates the division ratio between the timer clock (CK_INT) frequency and\nsampling clock used by the digital filters (ETR, TIx),\n00: t DTS = t CK_INT\n01: t DTS = 2 × t CK_INT\n10: t DTS = 4 × t CK_INT\n11: Reserved\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered\n1: TIMx_ARR register is buffered\nBits 6:3 Reserved, must be kept at reset value.\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the update interrupt (UEV) sources.\n0: Any of the following events generate an UEV if enabled:\n–\nCounter overflow\n–\nSetting the UG bit\n1: Only counter overflow generates an UEV if enabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable update interrupt (UEV) event\ngeneration.\n0: UEV enabled. An UEV is generated by one of the following events:\n–\nCounter overflow\n–\nSetting the UG bit.\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,\nCCRx). The counter and the prescaler are reinitialized if the UG bit is set.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\n442/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.6.2\nTIM10/11/13/14 Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1 0\nCC1IE UIE\nrw rw\nReserved\nBits 15:2\nReserved, must be kept at reset value.\nBit 1 CC1IE: Capture/Compare 1 interrupt enable\n0: CC1 interrupt disabled\n1: CC1 interrupt enabled\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled\n1: Update interrupt enabled\n16.6.3\nTIM10/11/13/14 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\nCC1OF\nReserved\n3\n2\n1 0\nCC1IF UIF\nrc_w0 rc_w0\nReserved\nrc_w0\nBit 15:10\n4\nReserved, must be kept at reset value.\nBit 9 CC1OF: Capture/Compare 1 overcapture flag\nThis flag is set by hardware only when the corresponding channel is configured in input\ncapture mode. It is cleared by software by writing it to ‘0’.\n0: No overcapture has been detected.\n1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was\nalready set\nBits 8:2\nReserved, must be kept at reset value.\nBit 1 CC1IF: Capture/compare 1 interrupt flag\nIf channel CC1 is configured as output:\nThis flag is set by hardware when the counter matches the compare value. It is cleared by\nsoftware.\n0: No match.\n1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.\nWhen the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit\ngoes high on the counter overflow.\nIf channel CC1 is configured as input:\nThis bit is set by hardware on a capture. It is cleared by software or by reading the\nTIMx_CCR1 register.\n0: No input capture occurred.\n1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected\non IC1 which matches the selected polarity).\nDoc ID 13902 Rev 14\n443/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–\nAt overflow and if UDIS=’0’ in the TIMx_CR1 register.\n–\nWhen CNT is reinitialized by software using the UG bit in TIMx_EGR register, if\nURS=’0’ and UDIS=’0’ in the TIMx_CR1 register.\n16.6.4\nTIM10/11/13/14 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1 0\nCC1G UG\nw w\nReserved\nBits 15:2 Reserved, must be kept at reset value.\nBit 1 CC1G: Capture/compare 1 generation\nThis bit is set by software in order to generate an event, it is automatically cleared by\nhardware.\n0: No action\n1: A capture/compare event is generated on channel 1:\nIf channel CC1 is configured as output:\nCC1IF flag is set, Corresponding interrupt or is sent if enabled.\nIf channel CC1 is configured as input:\nThe current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,\nthe corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was\nalready high.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action\n1: Re-initialize the counter and generates an update of the registers. Note that the prescaler\ncounter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared.\n444/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.6.5\nTIM10/11/13/14 capture/compare mode register 1\n(TIMx_CCMR1)\nAddress offset: 0x18\nReset value: 0x0000\nThe channels can be used in input (capture mode) or in output (compare mode). The\ndirection of a channel is defined by configuring the corresponding CCxS bits. All the other\nbits of this register have a different function in input and in output mode. For a given bit,\nOCxx describes its function when the channel is configured in output, ICxx describes its\nfunction when the channel is configured in input. So you must take care that the same bit\ncan have a different meaning for the input stage and for the output stage.\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\nReserved\n5\n4\nOC1M[2:0]\n3\n2\n1\n0\nOC1PE OC1FE\nCC1S[1:0]\nReserved\nrw\nrw\nrw\nrw\nrw\nIC1F[3:0]\nrw\nrw\nrw\nrw\nrw\nrw\nIC1PSC[1:0]\nrw\nrw\nrw\nrw\nrw\nOutput compare mode\nBits 15:7\nReserved, must be kept at reset value.\nBits 6:4 OC1M: Output compare 1 mode\nThese bits define the behavior of the output reference signal OC1REF from which OC1 is\nderived. OC1REF is active high whereas OC1 active level depends on CC1P bit.\n000: Frozen. The comparison between the output compare register TIMx_CCR1 and the\ncounter TIMx_CNT has no effect on the outputs.\n001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter\nTIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the\ncounter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).\n011: Toggle - OC1REF toggles when TIMx_CNT = TIMx_CCR1.\n100: Force inactive level - OC1REF is forced low.\n101: Force active level - OC1REF is forced high.\n110: PWM mode 1 - Channel 1 is active as long as TIMx_CNT < TIMx_CCR1 else inactive.\n111: PWM mode 2 - Channel 1 is inactive as long as TIMx_CNT < TIMx_CCR1 else active.\nNote: In PWM mode 1 or 2, the OCREF level changes when the result of the comparison\nchanges or when the output compare mode switches from frozen to PWM mode.\nBit 3 OC1PE: Output compare 1 preload enable\n0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the\nnew value is taken in account immediately.\n1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload\nregister. TIMx_CCR1 preload value is loaded in the active register at each update event.\nNote: The PWM mode can be used without validating the preload register only in one pulse\nmode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.\nDoc ID 13902 Rev 14\n445/1096 General-purpose timers (TIM9 to TIM14)\nRM0008\nBit 2 OC1FE: Output compare 1 fast enable\nThis bit is used to accelerate the effect of an event on the trigger in input on the CC output.\n0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is\nON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is\n5 clock cycles.\n1: An active edge on the trigger input acts like a compare match on CC1 output. OC is then\nset to the compare level independently of the result of the comparison. Delay to sample the\ntrigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the\nchannel is configured in PWM1 or PWM2 mode.\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output.\n01: CC1 channel is configured as input, IC1 is mapped on TI1.\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only\nif an internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\nInput capture mode\nBits 15:8\nReserved, must be kept at reset value.\nBits 7:4 IC1F: Input capture 1 filter\nThis bit-field defines the frequency used to sample TI1 input and the length of the digital filter\napplied to TI1. The digital filter is made of an event counter in which N events are needed to\nvalidate a transition on the output:\n1000: f SAMPLING =f DTS /8, N=6\n0000: No filter, sampling is done at f DTS\n1001: f SAMPLING =f DTS /8, N=8\n0001: f SAMPLING =f CK_INT , N=2\n0010: f SAMPLING =f CK_INT , N=4\n1010: f SAMPLING =f DTS /16, N=5\n1011: f SAMPLING =f DTS /16, N=6\n0011: f SAMPLING =f CK_INT , N=8\n1100: f SAMPLING =f DTS /16, N=8\n0100: f SAMPLING =f DTS /2, N=6\n0101: f SAMPLING =f DTS /2, N=8\n1101: f SAMPLING =f DTS /32, N=5\n1110: f SAMPLING =f DTS /32, N=6\n0110: f SAMPLING =f DTS /4, N=6\n1111: f SAMPLING =f DTS /32, N=8\n0111: f SAMPLING =f DTS /4, N=8\nNote: In current silicon revision, f DTS is replaced in the formula by CK_INT when ICxF[3:0]= 1,\n2 or 3.\nBits 3:2 IC1PSC: Input capture 1 prescaler\nThis bit-field defines the ratio of the prescaler acting on CC1 input (IC1).\nThe prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).\n00: no prescaler, capture is done each time an edge is detected on the capture input\n01: capture is done once every 2 events\n10: capture is done once every 4 events\n11: capture is done once every 8 events\nBits 1:0 CC1S: Capture/Compare 1 selection\nThis bit-field defines the direction of the channel (input/output) as well as the used input.\n00: CC1 channel is configured as output\n01: CC1 channel is configured as input, IC1 is mapped on TI1\n10: CC1 channel is configured as input, IC1 is mapped on TI2\n11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if\nan internal trigger input is selected through TS bit (TIMx_SMCR register)\nNote: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).\n446/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.6.6\nTIM10/11/13/14 capture/compare enable register\n(TIMx_CCER)\nAddress offset: 0x20\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\nCC1NP\nReserved\n1 0\nCC1P CC1E\nrw rw\nRes.\nrw\nBits 15:4 Reserved, must be kept at reset value.\nBit 3 CC1NP: Capture/Compare 1 complementary output Polarity.\nCC1 channel configured as output: CC1NP must be kept cleared.\nCC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define\nTI1FP1 polarity (refer to CC1P description).\nBit 2 Reserved, must be kept at reset value.\nBit 1 CC1P: Capture/Compare 1 output Polarity.\nCC1 channel configured as output:\n0: OC1 active high\n1: OC1 active low\nCC1 channel configured as input:\nThe CC1P bit selects TI1FP1 and TI2FP1 polarity for trigger or capture operations.\n00: noninverted/rising edge\nCircuit is sensitive to TI1FP1 rising edge (capture mode), TI1FP1 is not inverted.\n01: inverted/falling edge\nCircuit is sensitive to TI1FP1 falling edge (capture mode), TI1FP1 is inverted.\n10: reserved, do not use this configuration.\n11: noninverted/both edges\nCircuit is sensitive to both TI1FP1 rising and falling edges (capture mode), TI1FP1 is not\ninverted.\nBit 0 CC1E: Capture/Compare 1 output enable.\nCC1 channel configured as output:\n0: Off - OC1 is not active\n1: On - OC1 signal is output on the corresponding output pin\nCC1 channel configured as input:\nThis bit determines if a capture of the counter value can actually be done into the input\ncapture/compare register 1 (TIMx_CCR1) or not.\n0: Capture disabled\n1: Capture enabled\nTable 92.\nCCxE bit\nNote:\nOutput control bit for standard OCx channels\nOCx output state\n0 Output Disabled (OCx=’0’, OCx_EN=’0’)\n1 OCx=OCxREF + Polarity, OCx_EN=’1’\nThe state of the external I/O pins connected to the standard OCx channels depends on the\nOCx channel state and the GPIO registers.\nDoc ID 13902 Rev 14\n447/1096 General-purpose timers (TIM9 to TIM14)\n16.6.7\nRM0008\nTIM10/11/13/14 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCNT[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CNT[15:0]: Counter value\n16.6.8\nTIM10/11/13/14 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7\nPSC[15:0]\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded in the active prescaler register at each update event.\n16.6.9\nTIM10/11/13/14 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nARR[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 ARR[15:0]: Auto-reload value\nARR is the value to be loaded in the actual auto-reload register.\nRefer to Section 16.4.1: Time-base unit on page 413 for more details about ARR update and\nbehavior.\nThe counter is blocked while the auto-reload value is null.\n448/1096\nDoc ID 13902 Rev 14 RM0008\nGeneral-purpose timers (TIM9 to TIM14)\n16.6.10\nTIM10/11/13/14 capture/compare register 1 (TIMx_CCR1)\nAddress offset: 0x34\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCCR1[15:0]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 CCR1[15:0]: Capture/Compare 1 value\nIf channel CC1 is configured as output:\nCCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).\nIt is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit\nOC1PE). Else the preload value is copied in the active capture/compare 1 register when an\nupdate event occurs.\nThe active capture/compare register contains the value to be compared to the counter\nTIMx_CNT and signaled on OC1 output.\nIf channel CC1is configured as input:\nCCR1 is the counter value transferred by the last input capture 1 event (IC1).\n16.6.11\nTIM10/11/13/14 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the tables below:\n0x08\nTIMx_SMCR\n0\n0\n0\nReset value\nCKD\n[1:0]\nReserved\nTIMx_CR1\nARPE\n0x00\nRegister\nOffset\nTIM10/11/13/14 register map and reset values\n10\nTable 93.\n0 0 0\nNot Available\n0\n0\n0\nIC1F[3:0]\n0 0 0 0\nReserved\nReserved\n0 0\n0 0\nCC1S\n[1:0]\n0 0 0 0\nIC1\nCC1S\nPSC\n[1:0]\n[1:0]\n0 0 0 0\nDoc ID 13902 Rev 14\n0\nReserved\nReset value\nTIMx_CCER\nReserved\n0x1C\n0x20\nOC1M\n[2:0]\nReset value\nTIMx_CCMR1\nOutput compare\nmode\nReset value\nTIMx_CCMR1\nInput capture\nmode\nReset value\nReserved\n0x18\nTIMx_EGR\n0x14\nReserved\n0\nReserved\nReset value\n0\nTIMx_SR\n0x10\n0\nReserved\nReset value\nTIMx_DIER\n0x0C\nReset value\n0 0\n449/1096 General-purpose timers (TIM9 to TIM14)\nOffset\n0x24\nTIM10/11/13/14 register map and reset values (continued)\nRegister\nTIMx_CNT\nTable 93.\nRM0008\nCNT[15:0]\nReserved\nReset value\n0x28\nTIMx_PSC\n0\nTIMx_ARR\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0 0\nReserved\nTIMx_CCR1\nCCR1[15:0]\nReserved\nReset value\n0\n0\n0\n0\n0\n0\nReserved\nRefer to Table 3 on page 50 for the register boundary addresses.\n450/1096\n0\nARR[15:0]\nReserved\n0x30\n0x38 to\n0x4C\n0\nPSC[15:0]\nReset value\n0x34\n0\nReserved\nReset value\n0x2C\n0\nDoc ID 13902 Rev 14\n0\n0\n0\n0 RM0008\n17\nBasic timers (TIM6&TIM7)\nBasic timers (TIM6&TIM7)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to high-density and XL-density STM32F101xx and STM32F103xx\ndevices, and to connectivity line devices only.\n17.1\nTIM6&TIM7 introduction\nThe basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a\nprogrammable prescaler.\nThey may be used as generic timers for time-base generation but they are also specifically\nused to drive the digital-to-analog converter (DAC). In fact, the timers are internally\nconnected to the DAC and are able to drive it through their trigger outputs.\nThe timers are completely independent, and do not share any resources.\n17.2\nTIM6&TIM7 main features\nBasic timer (TIM6&TIM7) features include:\n● 16-bit auto-reload upcounter\n● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock\nfrequency by any factor between 1 and 65535\n● Synchronization circuit to trigger the DAC\n● Interrupt/DMA generation on the update event: counter overflow\nDoc ID 13902 Rev 14\n451/1096 Basic timers (TIM6&TIM7)\nRM0008\nFigure 169. Basic timer block diagram\nTIMxCLK from RCC\nTrigger TRGO\ncontroller\nInternal clock (CK_INT)\nReset, Enable, Count,\nController\nU\nAuto-reload Register\nStop, Clear or up\nCK_PSC\nFlag\nCK_CNT\nPSC\n±\nPrescaler\nto DAC\nUI\nU\nCNT\nCOUNTER\nPreload registers transferred\nto active registers on U event according to control bit\nevent\ninterrupt & DMA output\nai14749b\n17.3 TIM6&TIM7 functional description\n17.3.1 Time-base unit\nThe main block of the programmable timer is a 16-bit upcounter with its related auto-reload\nregister. The counter clock can be divided by a prescaler.\nThe counter, the auto-reload register and the prescaler register can be written or read by\nsoftware. This is true even when the counter is running.\nThe time-base unit includes:\n● Counter Register (TIMx_CNT)\n● Prescaler Register (TIMx_PSC)\n● Auto-Reload Register (TIMx_ARR)\nThe auto-reload register is preloaded. The preload register is accessed each time an\nattempt is made to write or read the auto-reload register. The contents of the preload\nregister are transferred into the shadow register permanently or at each update event UEV,\ndepending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The\nupdate event is sent when the counter reaches the overflow value and if the UDIS bit equals\n0 in the TIMx_CR1 register. It can also be generated by software. The generation of the\nupdate event is described in detail for each configuration.\nThe counter is clocked by the prescaler output CK_CNT, which is enabled only when the\ncounter enable bit (CEN) in the TIMx_CR1 register is set.\nNote that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.\n452/1096\nDoc ID 13902 Rev 14 RM0008\nBasic timers (TIM6&TIM7)\nPrescaler description\nThe prescaler can divide the counter clock frequency by any factor between 1 and 65536. It\nis based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).\nIt can be changed on the fly as the TIMx_PSC control register is buffered. The new\nprescaler ratio is taken into account at the next update event.\nFigure 170 and Figure 171 give some examples of the counter behavior when the prescaler\nratio is changed on the fly.\nFigure 170. Counter timing diagram with prescaler division change from 1 to 2\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF7\nF8 F9 FA FB FC\n00\n01\n02\n03\nUpdate event (UEV)\nPrescaler control register\n0\n1\nWrite a new value in TIMx_PSC\nPrescaler buffer 0\nPrescaler counter 0\n1\n0\n1\n0\n1\n0\n1\n0\n1\nFigure 171. Counter timing diagram with prescaler division change from 1 to 4\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF7\n00\nF8 F9 FA FB FC\n01\nUpdate event (UEV)\nPrescaler control register\n0\n3\nWrite a new value in TIMx_PSC\nPrescaler buffer 0\nPrescaler counter 0\nDoc ID 13902 Rev 14\n3\n0\n1\n2\n3\n0\n1\n2\n3\n453/1096 Basic timers (TIM6&TIM7)\n17.3.2\nRM0008\nCounting mode\nThe counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),\nthen restarts from 0 and generates a counter overflow event.\nAn update event can be generate at each counter overflow or by setting the UG bit in the\nTIMx_EGR register (by software or by using the slave mode controller).\nThe UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1\nregister. This avoids updating the shadow registers while writing new values into the preload\nregisters. In this way, no update event occurs until the UDIS bit has been written to 0,\nhowever, the counter and the prescaler counter both restart from 0 (but the prescale rate\ndoes not change). In addition, if the URS (update request selection) bit in the TIMx_CR1\nregister is set, setting the UG bit generates an update event UEV, but the UIF flag is not set\n(so no interrupt or DMA request is sent).\nWhen an update event occurs, all the registers are updated and the update flag (UIF bit in\nthe TIMx_SR register) is set (depending on the URS bit):\n● The buffer of the prescaler is reloaded with the preload value (contents of the\nTIMx_PSC register)\n● The auto-reload shadow register is updated with the preload value (TIMx_ARR)\nThe following figures show some examples of the counter behavior for different clock\nfrequencies when TIMx_ARR = 0x36.\nFigure 172. Counter timing diagram, internal clock divided by 1\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\n454/1096\nDoc ID 13902 Rev 14 RM0008\nBasic timers (TIM6&TIM7)\nFigure 173. Counter timing diagram, internal clock divided by 2\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n0034\n0035 0036\n0000\n0001\n0002\n0003\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 174. Counter timing diagram, internal clock divided by 4\nCK_INT\nCNT_EN\nTImer clock = CK_CNT\nCounter register\n0035\n0036\n0000\n0001\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nFigure 175. Counter timing diagram, internal clock divided by N\nCK_INT\nTimer clock = CK_CNT\nCounter register\n1F\n20\n00\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nDoc ID 13902 Rev 14\n455/1096 Basic timers (TIM6&TIM7)\nRM0008\nFigure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not\npreloaded)\nCK_INT\nCNT_EN\nTimer clock = CK_CNT\nCounter register\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload register\nFF\n36\nWrite a new value in TIMx_ARR\nFigure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR\npreloaded)\nCK_PSC\nCNT_EN\nTimer clock = CK_CNT\nCounter register\nF0\nF1 F2 F3 F4 F5 00 01 02 03 04 05 06 07\nCounter overflow\nUpdate event (UEV)\nUpdate interrupt flag (UIF)\nAuto-reload preload register F5 36\nAuto-reload shadow register F5 36\nWrite a new value in TIMx_ARR\n17.3.3\nClock source\nThe counter clock is provided by the Internal clock (CK_INT) source.\nThe CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual\ncontrol bits and can be changed only by software (except for UG that remains cleared\nautomatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal\nclock CK_INT.\nFigure 178 shows the behavior of the control circuit and the upcounter in normal mode,\nwithout prescaler.\n456/1096\nDoc ID 13902 Rev 14 RM0008\nBasic timers (TIM6&TIM7)\nFigure 178. Control circuit in normal mode, internal clock divided by 1\nCK_INT\nCEN=CNT_EN\nUG\nCNT_INIT\nCounter clock = CK_CNT = CK_PSC\nCounter register\n17.3.4\n31\n32 33 34 35 36 00 01 02 03 04 05 06 07\nDebug mode\nWhen the microcontroller enters the debug mode (Cortex™-M3 core - halted), the TIMx\ncounter either continues to work normally or stops, depending on the DBG_TIMx_STOP\nconfiguration bit in the DBG module. For more details, refer to Section 31.16.2: Debug\nsupport for timers, watchdog, bxCAN and I2C.\n17.4\nTIM6&TIM7 registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n17.4.1\nTIM6&TIM7 control register 1 (TIMx_CR1)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\nARPE\nReserved\n4\n3 2 1 0\nOPM URS UDIS CEN\nrw rw rw rw\nReserved\nrw\nBits 15:8 Reserved, must be kept at reset value.\nBit 7 ARPE: Auto-reload preload enable\n0: TIMx_ARR register is not buffered.\n1: TIMx_ARR register is buffered.\nBits 6:4 Reserved, must be kept at reset value.\nBit 3 OPM: One-pulse mode\n0: Counter is not stopped at update event\n1: Counter stops counting at the next update event (clearing the CEN bit).\nDoc ID 13902 Rev 14\n457/1096 Basic timers (TIM6&TIM7)\nRM0008\nBit 2 URS: Update request source\nThis bit is set and cleared by software to select the UEV event sources.\n0: Any of the following events generates an update interrupt or DMA request if enabled.\nThese events can be:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\n1: Only counter overflow/underflow generates an update interrupt or DMA request if\nenabled.\nBit 1 UDIS: Update disable\nThis bit is set and cleared by software to enable/disable UEV event generation.\n0: UEV enabled. The Update (UEV) event is generated by one of the following events:\n–\nCounter overflow/underflow\n–\nSetting the UG bit\n–\nUpdate generation through the slave mode controller\nBuffered registers are then loaded with their preload values.\n1: UEV disabled. The Update event is not generated, shadow registers keep their value\n(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if\na hardware reset is received from the slave mode controller.\nBit 0 CEN: Counter enable\n0: Counter disabled\n1: Counter enabled\nNote: Gated mode can work only if the CEN bit has been previously set by software. However\ntrigger mode can set the CEN bit automatically by hardware.\nCEN is cleared automatically in one-pulse mode, when an update event occurs.\n458/1096\nDoc ID 13902 Rev 14 RM0008\nBasic timers (TIM6&TIM7)\n17.4.2\nTIM6&TIM7 control register 2 (TIMx_CR2)\nAddress offset: 0x04\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nMMS[2:0]\nReserved\nReserved\nrw\nrw\nrw\nBits 15:7 Reserved, must be kept at reset value.\nBits 6:4 MMS: Master mode selection\nThese bits are used to select the information to be sent in master mode to slave timers for\nsynchronization (TRGO). The combination is as follows:\n000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If\nreset is generated by the trigger input (slave mode controller configured in reset mode) then\nthe signal on TRGO is delayed compared to the actual reset.\n001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is\nuseful to start several timers at the same time or to control a window in which a slave timer\nis enabled. The Counter Enable signal is generated by a logic OR between CEN control bit\nand the trigger input when configured in gated mode.\nWhen the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,\nexcept if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR\nregister).\n010: Update - The update event is selected as a trigger output (TRGO). For instance a\nmaster timer can then be used as a prescaler for a slave timer.\nBits 3:0 Reserved, must be kept at reset value.\n17.4.3\nTIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER)\nAddress offset: 0x0C\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\nUDE\nReserved\n3\n2\n1\n0\nUIE\nReserved\nrw\nrw\nBit 15:9 Reserved, must be kept at reset value.\nBit 8 UDE: Update DMA request enable\n0: Update DMA request disabled.\n1: Update DMA request enabled.\nBit 7:1 Reserved, must be kept at reset value.\nBit 0 UIE: Update interrupt enable\n0: Update interrupt disabled.\n1: Update interrupt enabled.\nDoc ID 13902 Rev 14\n459/1096 Basic timers (TIM6&TIM7)\n17.4.4\nRM0008\nTIM6&TIM7 status register (TIMx_SR)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUIF\nReserved\nrc_w0\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UIF: Update interrupt flag\nThis bit is set by hardware on an update event. It is cleared by software.\n0: No update occurred.\n1: Update interrupt pending. This bit is set by hardware when the registers are updated:\n–At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the\nTIMx_CR1 register.\n–When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if\nURS = 0 and UDIS = 0 in the TIMx_CR1 register.\n17.4.5\nTIM6&TIM7 event generation register (TIMx_EGR)\nAddress offset: 0x14\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nUG\nReserved\nw\nBits 15:1 Reserved, must be kept at reset value.\nBit 0 UG: Update generation\nThis bit can be set by software, it is automatically cleared by hardware.\n0: No action.\n1: Re-initializes the timer counter and generates an update of the registers. Note that the\nprescaler counter is cleared too (but the prescaler ratio is not affected).\n17.4.6\nTIM6&TIM7 counter (TIMx_CNT)\nAddress offset: 0x24\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nCNT[15:0]\nrw\nrw\nBits 15:0\n460/1096\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nCNT[15:0]: Counter value\nDoc ID 13902 Rev 14 RM0008\nBasic timers (TIM6&TIM7)\n17.4.7\nTIM6&TIM7 prescaler (TIMx_PSC)\nAddress offset: 0x28\nReset value: 0x0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nPSC[15:0]\nrw\nBits 15:0 PSC[15:0]: Prescaler value\nThe counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).\nPSC contains the value to be loaded into the active prescaler register at each update event.\n17.4.8\nTIM6&TIM7 auto-reload register (TIMx_ARR)\nAddress offset: 0x2C\nReset value: 0x0000\n15 14 13 12 11 10 9 8\nrw rw rw rw rw rw rw rw\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nARR[15:0]\nrw\nBits 15:0 ARR[15:0]: Prescaler value\nARR is the value to be loaded into the actual auto-reload register.\nRefer to Section 17.3.1: Time-base unit on page 452 for more details about ARR update and\nbehavior.\nThe counter is blocked while the auto-reload value is null.\nDoc ID 13902 Rev 14\n461/1096 Basic timers (TIM6&TIM7)\n17.4.9\nRM0008\nTIM6&TIM7 register map\nTIMx registers are mapped as 16-bit addressable registers as described in the table below:\nTIMx_CR2\n0\n0 0\n0\n0\nTIMx_DIER\nReserved\n0x08\nReserved\n0\nTIMx_SR\n0\nReset value\n0x10\n0\nMMS[2:0]\nReserved\nReset value\n0x0C\n0\n0x04\n0\nReserved\nReset value\nTIMx_CR1\n0x00\nTIM6&TIM7 register map and reset values\nRegister\nOffset\nTable 94.\nReserved\n0x14\n0\nTIMx_EGR\nReset value\nReserved\nReset value\n0\n0x18 Reserved\n0x1C Reserved\n0x20 Reserved\n0x24\nTIMx_CNT\nReset value\n0x28\nTIMx_PSC\n0\nTIMx_ARR\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nDoc ID 13902 Rev 14\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0 0\nARR[15:0]\nReserved\nRefer to for the register boundary addresses.\n0\nPSC[15:0]\n0\nReset value\n462/1096\n0\nReserved\nReset value\n0x2C\nCNT[15:0]\nReserved\n0\n0\n0\n0\n0\n0\n0\n0\n0 RM0008\n18\nReal-time clock (RTC)\nReal-time clock (RTC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F10xxx family, unless otherwise specified.\n18.1\nRTC introduction\nThe real-time clock is an independent timer. The RTC provides a set of continuously running\ncounters which can be used, with suitable software, to provide a clock-calendar function.\nThe counter values can be written to set the current time/date of the system.\nThe RTC core and clock configuration (RCC_BDCR register) are in the Backup domain,\nwhich means that RTC setting and time are kept after reset or wakeup from Standby mode.\nAfter reset, access to the Backup registers and RTC is disabled and the Backup domain\n(BKP) is protected against possible parasitic write access. To enable access to the Backup\nregisters and the RTC, proceed as follows:\n● enable the power and backup interface clocks by setting the PWREN and BKPEN bits\nin the RCC_APB1ENR register\n● set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup\nregisters and RTC.\nDoc ID 13902 Rev 14\n463/1096 Real-time clock (RTC)\n18.2\nRTC main features\n● Programmable prescaler: division factor up to 2 20\n● 32-bit programmable counter for long-term measurement\n● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least\nfour times slower than the PCLK1 clock)\n● The RTC clock source could be any of the following ones:\n●\n●\n464/1096\nRM0008\n– HSE clock divided by 128\n– LSE oscillator clock\n– LSI oscillator clock (refer to Section 7.2.8: RTC clock for details)\nTwo separate reset types:\n– The APB1 interface is reset by system reset\n– The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup\ndomain reset (see Section 7.1.3: Backup domain reset on page 88).\nThree dedicated maskable interrupt lines:\n– Alarm interrupt, for generating a software programmable alarm interrupt.\n– Seconds interrupt, for generating a periodic interrupt signal with a programmable\nperiod length (up to 1 second).\n– Overflow interrupt, to detect when the internal programmable counter rolls over to\nzero.\nDoc ID 13902 Rev 14 RM0008\nReal-time clock (RTC)\n18.3 RTC functional description\n18.3.1 Overview\nThe RTC consists of two main units (see Figure 179 on page 465). The first one (APB1\nInterface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit\nregisters accessible from the APB1 bus in read or write mode (for more information refer to\nSection 18.4: RTC registers on page 468). The APB1 interface is clocked by the APB1 bus\nclock in order to interface with the APB1 bus.\nThe other unit (RTC Core) consists of a chain of programmable counters made of two main\nblocks. The first block is the RTC prescaler block, which generates the RTC time base\nTR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit\nprogrammable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an\ninterrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a\n32-bit programmable counter that can be initialized to the current system time. The system\ntime is incremented at the TR_CLK rate and compared with a programmable date (stored in\nthe RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR\ncontrol register.\nFigure 179. RTC simplified block diagram\nAPB1 bus\nPCLK1\nAPB1 interface\nRTCCLK\nnot powered in Standby\nBackup domain\nRTC_CR\nRTC_PRL\nRTC_Second\nReload\nRTC_DIV\nTR_CLK\n32-bit programmable\ncounter\nRTC_CNT\nrising\nedge\nRTC prescaler\nSECF\nSECIE\nRTC_Overflow\nOWF\nOWIE\n=\nRTC_Alarm\nALRF\nALRIE\nRTC_ALR\nnot powered in Standby\npowered in Standby\nNVIC interrupt\ncontroller\npowered in Standby\nnot powered in Standby\nWKUP pin\nRTC_Alarm\nWKP_STDBY\nexit\nStandby mode\npowered in Standby\nai14969b\nDoc ID 13902 Rev 14\n465/1096 Real-time clock (RTC)\n18.3.2\nRM0008\nResetting RTC registers\nAll system registers are asynchronously reset by a System Reset or Power Reset, except for\nRTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV.\nThe RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup\nDomain reset. Refer to Section 7.1.3 on page 88.\n18.3.3\nReading RTC registers\nThe RTC core is completely independent from the RTC APB1 interface.\nSoftware accesses the RTC prescaler, counter and alarm values through the APB1 interface\nbut the associated readable registers are internally updated at each rising edge of the RTC\nclock resynchronized by the RTC APB1 clock. This is also true for the RTC flags.\nThis means that the first read to the RTC APB1 registers may be corrupted (generally read\nas 0) if the APB1 interface has previously been disabled and the read occurs immediately\nafter the APB1 interface is enabled but before the first internal update of the registers. This\ncan occur if:\n● A system reset or power reset has occurred\n● The MCU has just woken up from Standby mode (see Section 5.3: Low-power modes)\n● The MCU has just woken up from Stop mode (see Section 5.3: Low-power modes)\nIn all the above cases, the RTC core has been kept running while the APB1 interface was\ndisabled (reset, not clocked or unpowered).\nConsequently when reading the RTC registers, after having disabled the RTC APB1\ninterface, the software must first wait for the RSF bit (Register Synchronized Flag) in the\nRTC_CRL register to be set by hardware.\nNote that the RTC APB1 interface is not affected by WFI and WFE low-power modes.\n18.3.4\nConfiguring RTC registers\nTo write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter\nConfiguration Mode. This is done by setting the CNF bit in the RTC_CRL register.\nIn addition, writing to any RTC register is only enabled if the previous write operation is\nfinished. To enable the software to detect this situation, the RTOFF status bit is provided in\nthe RTC_CR register to indicate that an update of the registers is in progress. A new value\ncan be written to the RTC registers only when the RTOFF status bit value is ’1’.\nConfiguration procedure:\n1. Poll RTOFF, wait until its value goes to ‘1’\n2. Set the CNF bit to enter configuration mode\n3. Write to one or more RTC registers\n4. Clear the CNF bit to exit configuration mode\n5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation.\nThe write operation only executes when the CNF bit is cleared; it takes at least three\nRTCCLK cycles to complete.\n466/1096\nDoc ID 13902 Rev 14 RM0008\nReal-time clock (RTC)\n18.3.5\nRTC flag assertion\nThe RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update\nof the RTC Counter.\nThe RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the\ncounter reaches 0x0000.\nThe RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 180) are asserted on the last RTC\nCore clock cycle before the counter reaches the RTC Alarm value stored in the Alarm\nregister increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC\nSecond flag must be synchronized by using one of the following sequences:\n● Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm\nand/or RTC Counter registers are updated.\n● Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or\nthe RTC Counter register.\nFigure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004\nRTCCLK\nRTC_PR\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\nRTC_Second\nRTC_CNT\n0001\n0000\n0002\n0003\n0004\n0005\nRTC_ALARM\n1 RTCCLK\nALRF\n(not powered\nin Standby)\ncan be cleared by software\nFigure 181. RTC Overflow waveform example with PR=0003\nRTCCLK\nRTC_PR\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\n0002\n0001\n0000\n0003\nRTC_Second\nRTC_CNT\nFFFFFFFB\nFFFFFFFC\nFFFFFFFD\nFFFFFFFE\n0000\nFFFFFFFF\nRTC_Overflow\n1 RTCCLK\nOWF\n(not powered\nin Standby)\ncan be cleared by software\nDoc ID 13902 Rev 14\n467/1096 Real-time clock (RTC)\n18.4\nRM0008\nRTC registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n18.4.1\nRTC control register high (RTC_CRH)\nAddress offset: 0x00\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2 1 0\nOWIE ALRIE SECIE\nrw rw rw\nReserved\nBits 15:3 Reserved, forced by hardware to 0.\nBit 2 OWIE: Overflow interrupt enable\n0: Overflow interrupt is masked.\n1: Overflow interrupt is enabled.\nBit 1 ALRIE: Alarm interrupt enable\n0: Alarm interrupt is masked.\n1: Alarm interrupt is enabled.\nBit 0 SECIE: Second interrupt enable\n0: Second interrupt is masked.\n1: Second interrupt is enabled.\nThese bits are used to mask interrupt requests. Note that at reset all interrupts are disabled,\nso it is possible to write to the RTC registers to ensure that no interrupt requests are pending\nafter initialization. It is not possible to write to the RTC_CRH register when the peripheral is\ncompleting a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page\n466).\nThe RTC functions are controlled by this control register. Some bits must be written using a\nspecific configuration procedure (see Configuration procedure:).\n468/1096\nDoc ID 13902 Rev 14 RM0008\nReal-time clock (RTC)\n18.4.2\nRTC control register low (RTC_CRL)\nAddress offset: 0x04\nReset value: 0x0020\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5 4 3 2 1 0\nRTOFF CNF RSF OWF ALRF SECF\nr rw rc_w0 rc_w0 rc_w0 rc_w0\nReserved\nBits 15:6 Reserved, forced by hardware to 0.\nBit 5 RTOFF: RTC operation OFF\nWith this bit the RTC reports the status of the last write operation performed on its registers,\nindicating if it has been completed or not. If its value is ‘0’ then it is not possible to write to any\nof the RTC registers. This bit is read only.\n0: Last write operation on RTC registers is still ongoing.\n1: Last write operation on RTC registers terminated.\nBit 4 CNF: Configuration flag\nThis bit must be set by software to enter in configuration mode so as to allow new values to\nbe written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write operation is only\nexecuted when the CNF bit is reset by software after has been set.\n0: Exit configuration mode (start update of RTC registers).\n1: Enter configuration mode.\nBit 3 RSF: Registers synchronized flag\nThis bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated\nand cleared by software. Before any read operation after an APB1 reset or an APB1 clock\nstop, this bit must be cleared by software, and the user application must wait until it is set to\nbe sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized.\n0: Registers not yet synchronized.\n1: Registers synchronized.\nBit 2 OWF: Overflow flag\nThis bit is set by hardware when the 32-bit programmable counter overflows. An interrupt is\ngenerated if OWIE=1 in the RTC_CRH register. It can be cleared only by software. Writing ‘1’\nhas no effect.\n0: Overflow not detected\n1: 32-bit programmable counter overflow occurred.\nBit 1 ALRF: Alarm flag\nThis bit is set by hardware when the 32-bit programmable counter reaches the threshold set\nin the RTC_ALR register. An interrupt is generated if ALRIE=1 in the RTC_CRH register. It\ncan be cleared only by software. Writing ‘1’ has no effect.\n0: Alarm not detected\n1: Alarm detected\nBit 0 SECF: Second flag\nThis bit is set by hardware when the 32-bit programmable prescaler overflows, thus\nincrementing the RTC counter. Hence this flag provides a periodic signal with a period\ncorresponding to the resolution programmed for the RTC counter (usually one second). An\ninterrupt is generated if SECIE=1 in the RTC_CRH register. It can be cleared only by\nsoftware. Writing ‘1’ has no effect.\n0: Second flag condition not met.\n1: Second flag condition met.\nDoc ID 13902 Rev 14\n469/1096 Real-time clock (RTC)\nRM0008\nThe functions of the RTC are controlled by this control register. It is not possible to write to\nthe RTC_CR register while the peripheral is completing a previous write operation (flagged\nby RTOFF=0, see Section 18.3.4 on page 466).\nNote:\n1 Any flag remains pending until the appropriate RTC_CR request bit is reset by software,\nindicating that the interrupt request has been granted.\n2 At reset the interrupts are disabled, no interrupt requests are pending and it is possible to\nwrite to the RTC registers.\n3 The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running.\n4 The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by\nsoftware.\n5 If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also\nenabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm\ninterrupt are enabled.\n6 If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI\nController in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is\ngenerated on this line (no RTC Alarm interrupt generation).\n18.4.3\nRTC prescaler load register (RTC_PRLH / RTC_PRLL)\nThe Prescaler Load registers keep the period counting value of the RTC prescaler. They are\nwrite-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if\nthe RTOFF value is ‘1’.\nRTC prescaler load register high (RTC_PRLH)\nAddress offset: 0x08\nWrite only (see Section 18.3.4 on page 466)\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPRL[19:16]\nReserved\nw\nw\nw\nw\nBits 15:4 Reserved, forced by hardware to 0.\nBits 3:0 PRL[19:16]: RTC prescaler reload value high\nThese bits are used to define the counter clock frequency according to the following formula:\nf TR_CLK = f RTCCLK /(PRL[19:0]+1)\n470/1096\nDoc ID 13902 Rev 14 RM0008\nReal-time clock (RTC)\nRTC prescaler load register low (RTC_PRLL)\nAddress offset: 0x0C\nWrite only (see Section 18.3.4 on page 466)\nReset value: 0x8000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nw w w w w w w\nPRL[15:0]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 15:0 PRL[15:0]: RTC prescaler reload value low\nThese bits are used to define the counter clock frequency according to the following formula:\nf TR_CLK = f RTCCLK /(PRL[19:0]+1)\nCaution:\nThe zero value is not recommended. RTC interrupts and flags cannot be\nasserted correctly.\nNote: If the input clock frequency (f RTCCLK ) is 32.768 kHz, write 7FFFh in this register to get a\nsignal period of 1 second.\n18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL)\nDuring each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the\nvalue stored in the RTC_PRL register. To get an accurate time measurement it is possible to\nread the current value of the prescaler counter, stored in the RTC_DIV register, without\nstopping it. This register is read-only and it is reloaded by hardware after any change in the\nRTC_PRL or RTC_CNT registers.\nRTC prescaler divider register high (RTC_DIVH)\nAddress offset: 0x10\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRTC_DIV[19:16]\nReserved\nr r r r\nBits 15:4 Reserved\nBits 3:0 RTC_DIV[19:16]: RTC clock divider high\nRTC prescaler divider register low (RTC_DIVL)\nAddress offset: 0x14\nReset value: 0x8000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nr r r r r r r\nRTC_DIV[15:0]\nr\nr\nr\nr\nr\nr\nr\nr\nr\nBits 15:0 RTC_DIV[15:0]: RTC clock divider low\nDoc ID 13902 Rev 14\n471/1096 Real-time clock (RTC)\n18.4.5\nRM0008\nRTC counter register (RTC_CNTH / RTC_CNTL)\nThe RTC core has one 32-bit programmable counter, accessed through two 16-bit registers;\nthe count rate is based on the TR_CLK time reference, generated by the prescaler.\nRTC_CNT registers keep the counting value of this counter. They are write-protected by bit\nRTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A\nwrite operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the\ncorresponding programmable counter and reloads the RTC Prescaler. When reading, the\ncurrent value in the counter (system date) is returned.\nRTC counter register high (RTC_CNTH)\nAddress offset: 0x18\nReset value: 0x0000\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nRTC_CNT[31:16]\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 15:0 RTC_CNT[31:16]: RTC counter high\nReading the RTC_CNTH register, the current value of the high part of the RTC Counter\nregister is returned. To write to this register it is necessary to enter configuration mode (see\nSection 18.3.4: Configuring RTC registers on page 466).\nRTC counter register low (RTC_CNTL)\nAddress offset: 0x1C\nReset value: 0x0000\n15 14 13 12 11 10 9\n8\nrw rw rw rw rw rw rw\n7\n6 5 4 3 2 1 0\nrw rw rw rw rw rw rw\nRTC_CNT[15:0]\nrw\nrw\nBits 15:0 RTC_CNT[15:0]: RTC counter low\nReading the RTC_CNTL register, the current value of the lower part of the RTC Counter\nregister is returned. To write to this register it is necessary to enter configuration mode (see\nSection 18.3.4: Configuring RTC registers on page 466).\n472/1096\nDoc ID 13902 Rev 14 RM0008\nReal-time clock (RTC)\n18.4.6\nRTC alarm register high (RTC_ALRH / RTC_ALRL)\nWhen the programmable counter reaches the 32-bit value stored in the RTC_ALR register,\nan alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is\nwrite-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if\nthe RTOFF value is ‘1’.\nRTC alarm register high (RTC_ALRH)\nAddress offset: 0x20\nWrite only (see Section 18.3.4 on page 466)\nReset value: 0xFFFF\n15\n14\n13\n12\n11\n10\n9\n8\n7\n6 5 4 3 2 1 0\nw w w w w w w\nRTC_ALR[31:16]\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 15:0 RTC_ALR[31:16]: RTC alarm high\nThe high part of the alarm time is written by software in this register. To write to this register\nit is necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers\non page 466).\nRTC alarm register low (RTC_ALRL)\nAddress offset: 0x24\nWrite only (see Section 18.3.4 on page 466)\nReset value: 0xFFFF\n15 14 13 12 11 10 9\n8\nw w w w w w w\n7\n6 5 4 3 2 1 0\nw w w w w w w\nRTC_ALR[15:0]\nw\nw\nBits 15:0 RTC_ALR[15:0]: RTC alarm low\nThe low part of the alarm time is written by software in this register. To write to this register it\nis necessary to enter configuration mode (see Section 18.3.4: Configuring RTC registers on\npage 466).\nDoc ID 13902 Rev 14\n473/1096 Real-time clock (RTC)\n18.4.7\nRM0008\nRTC register map\nRTC registers are mapped as 16-bit addressable registers as described in the table below:\n0x08\nRTC_PRLH\nRTC_PRLL\n0x10\nRTC_DIVH\n0 0\nPRL[19:16]\n0x14\nRTC_DIVL\n1\n0x18\nRTC_CNTH\nRTC_CNTL\n0x20\nRTC_ALRH\nRTC_ALRL\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0 0\n0\n0\n0\n0 0 0 0 0 0\n0 0 0 0 0 0\n1 1 1 1 1 1 1\n1 1 1 1 1 1 1\n0\n0\n0\n0\n0\nALR[31:16]\nReserved\n1\n1\n1\n1\n1\n1\n1\n1\n1\nALR[15:0]\nReserved\n1\nDoc ID 13902 Rev 14\n0\nCNT[15:0]\nReserved\n1\n1\n1\n1\n1\nRefer to Table 3 on page 50for the register boundary addresses.\n474/1096\n0\nCNT[13:16]\nReserved\nReset value\n0\nDIV[15:0]\n1\nReset value\n0x24\n0\nReserved\nReset value\n0\nDIV[31:16]\n0\nReset value\n0x1C\n0\nReserved\nReset value\n0\nPRL[15:0]\nReserved\nReset value\n0\nReserved\nReset value\n0\n1\nReset value\n0x0C\n0\nReserved\nReset value\n0\nRTC_CRL\n0\n0x04\n0\nReserved\nReset value\nRTC_CRH\n0x00\nRTC register map and reset values\nRegister\nOffset\nTable 95.\n1\n1\n1 RM0008\n19\nIndependent watchdog (IWDG)\nIndependent watchdog (IWDG)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F10xxx family, unless otherwise specified.\n19.1\nIWDG introduction\nThe STM32F10xxx have two embedded watchdog peripherals which offer a combination of\nhigh safety level, timing accuracy and flexibility of use. Both watchdog peripherals\n(Independent and Window) serve to detect and resolve malfunctions due to software failure,\nand to trigger system reset or an interrupt (window watchdog only) when the counter\nreaches a given timeout value.\nThe independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)\nand thus stays active even if the main clock fails. The window watchdog (WWDG) clock is\nprescaled from the APB1 clock and has a configurable time-window that can be\nprogrammed to detect abnormally late or early application behavior.\nThe IWDG is best suited to applications which require the watchdog to run as a totally\nindependent process outside the main application, but have lower timing accuracy\nconstraints. The WWDG is best suited to applications which require the watchdog to react\nwithin an accurate timing window. For further information on the window watchdog, refer to\nSection 20 on page 480.\n19.2\n19.3\nIWDG main features\n● Free-running downcounter\n● clocked from an independent RC oscillator (can operate in Standby and Stop modes)\n● Reset (if watchdog activated) when the downcounter value of 0x000 is reached\nIWDG functional description\nFigure 182 shows the functional blocks of the independent watchdog module.\nWhen the independent watchdog is started by writing the value 0xCCCC in the Key register\n(IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it\nreaches the end of count value (0x000) a reset signal is generated (IWDG reset).\nDoc ID 13902 Rev 14\n475/1096 Independent watchdog (IWDG)\nRM0008\nWhenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value\nis reloaded in the counter and the watchdog reset is prevented.\n19.3.1\nHardware watchdog\nIf the “Hardware watchdog” feature is enabled through the device option bits, the watchdog\nis automatically enabled at power-on, and will generate a reset unless the Key register is\nwritten by the software before the counter reaches end of count.\n19.3.2\nRegister access protection\nWrite access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you\nmust first write the code 0x5555 in the IWDG_KR register. A write access to this register\nwith a different value will break the sequence and register access will be protected again.\nThis implies that it is the case of the reload operation (writing 0xAAAA).\nA status register is available to indicate that an update of the prescaler or the down-counter\nreload value is on going.\n19.3.3\nDebug mode\nWhen the microcontroller enters debug mode (Cortex™-M3 core halted), the IWDG counter\neither continues to work normally or stops, depending on DBG_IWDG_STOP configuration\nbit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,\nwatchdog, bxCAN and I2C.\nFigure 182. Independent watchdog block diagram\n#/2%\n0RESCALER RM0008\nIndependent watchdog (IWDG)\nMin/max IWDG timeout period at 40 kHz (LSI) (continued) (1)\nTable 96.\nPrescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]=\n0x000 Max timeout (ms) RL[11:0]=\n0xFFF\n/128 5 3.2 13107.2\n/256 6 (or 7) 6.4 26214.4\n1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30\nto 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing\nof the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.\nThe LSI can be calibrated so as to compute the IWDG timeout with an acceptable accuracy.\nFor more details refer to LSI clock on page 93.\n19.4\nIWDG registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n19.4.1\nKey register (IWDG_KR)\nAddress offset: 0x00\nReset value: 0x0000 0000 (reset by Standby mode)\n31 30 29 28 27 26 25\n24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9\n8\n7\n6 5 4 3 2 1 0\nw w w w w w w\nKEY[15:0]\nReserved\nw\nw\nw\nw\nw\nw\nw\nw\nw\nBits 31:16 Reserved, must be kept at reset value.\nBits 15:0 KEY[15:0]: Key value (write only, read 0000h)\nThese bits must be written by software at regular intervals with the key value AAAAh,\notherwise the watchdog generates a reset when the counter reaches 0.\nWriting the key value 5555h to enable access to the IWDG_PR and IWDG_RLR registers\n(see Section 19.3.2)\nWriting the key value CCCCh starts the watchdog (except if the hardware watchdog option is\nselected)\nDoc ID 13902 Rev 14\n477/1096 Independent watchdog (IWDG)\n19.4.2\nRM0008\nPrescaler register (IWDG_PR)\nAddress offset: 0x04\nReset value: 0x0000 0000\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nPR[2:0]\nReserved\nrw\nrw\nrw\nBits 31:3 Reserved, must be kept at reset value.\nBits 2:0 PR[2:0]: Prescaler divider\nThese bits are write access protected seeSection 19.3.2. They are written by software to\nselect the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in\norder to be able to change the prescaler divider.\n000: divider /4\n001: divider /8\n010: divider /16\n011: divider /32\n100: divider /64\n101: divider /128\n110: divider /256\n111: divider /256\nNote: Reading this register returns the prescaler value from the VDD voltage domain. This\nvalue may not be up to date/valid if a write operation to this register is ongoing. For this\nreason the value read from this register is valid only when the PVU bit in the IWDG_SR\nregister is reset.\n19.4.3\nReload register (IWDG_RLR)\nAddress offset: 0x08\nReset value: 0x0000 0FFF (reset by Standby mode)\n31 30 29 28 27 26 25\n24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9\n8\n7\n6\n5\n4 3 2 1 0\nrw rw rw rw rw\nRL[11:0]\nReserved\nrw rw\nrw\nrw\nrw\nrw\nrw\nBits 31:12 Reserved, must be kept at reset value.\nBits11:0 RL[11:0]: Watchdog counter reload value\nThese bits are write access protected see Section 19.3.2. They are written by software to\ndefine the value to be loaded in the watchdog counter each time the value AAAAh is written\nin the IWDG_KR register. The watchdog counter counts down from this value. The timeout\nperiod is a function of this value and the clock prescaler. Refer to Table 96.\nThe RVU bit in the IWDG_SR register must be reset in order to be able to change the reload\nvalue.\nNote: Reading this register returns the reload value from the VDD voltage domain. This value\nmay not be up to date/valid if a write operation to this register is ongoing on this register.\nFor this reason the value read from this register is valid only when the RVU bit in the\nIWDG_SR register is reset.\n478/1096\nDoc ID 13902 Rev 14 RM0008\n19.4.4\nIndependent watchdog (IWDG)\nStatus register (IWDG_SR)\nAddress offset: 0x0C\nReset value: 0x0000 0000 (not reset by Standby mode)\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9\n8\n7\n6\n5\n4\n3\n2\n1\n0\nRVU PVU\nReserved\nr\nr\nBits 31:2 Reserved, must be kept at reset value.\nBit 1 RVU: Watchdog counter reload value update\nThis bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset\nby hardware when the reload value update operation is completed in the V DD voltage domain\n(takes up to 5 RC 40 kHz cycles).\nReload value can be updated only when RVU bit is reset.\nBit 0 PVU: Watchdog prescaler value update\nThis bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is\nreset by hardware when the prescaler update operation is completed in the V DD voltage\ndomain (takes up to 5 RC 40 kHz cycles).\nPrescaler value can be updated only when PVU bit is reset.\nNote: If several reload values or prescaler values are used by application, it is mandatory to wait\nuntil RVU bit is reset before changing the reload value and to wait until PVU bit is reset\nbefore changing the prescaler value. However, after updating the prescaler and/or the\nreload value it is not necessary to wait until RVU or PVU is reset before continuing code\nexecution (even in case of low-power mode entry, the write operation is taken into account\nand will complete)\n19.4.5 IWDG register map\nThe following table gives the IWDG register map and reset values.\n0x04\n0x08\n0x0C\nIWDG_KR\nReset value\nIWDG_PR\nReset value\nIWDG_SR\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\n0\nPR[2:0]\nReserved\nReset value\nIWDG_RLR\nKEY[15:0]\nReserved\n0 0 0\n1 1 1\n0x00\nIWDG register map and reset values\nRegister\nOffset\n0\nTable 97.\n0 0\nRL[11:0]\nReserved\n1\n1\nReserved\nReset value\n1\n1\n1\n1\n1\n1\n1\nRefer to Table 3 on page 50 for the register boundary addresses.\nDoc ID 13902 Rev 14\n479/1096 Window watchdog (WWDG)\n20\nRM0008\nWindow watchdog (WWDG)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to the whole STM32F10xxx family, unless otherwise specified.\n20.1\nWWDG introduction\nThe window watchdog is used to detect the occurrence of a software fault, usually\ngenerated by external interference or by unforeseen logical conditions, which causes the\napplication program to abandon its normal sequence. The watchdog circuit generates an\nMCU reset on expiry of a programmed time period, unless the program refreshes the\ncontents of the downcounter before the T6 bit becomes cleared. An MCU reset is also\ngenerated if the 7-bit downcounter value (in the control register) is refreshed before the\ndowncounter has reached the window register value. This implies that the counter must be\nrefreshed in a limited window.\n20.2\nWWDG main features\n● Programmable free-running downcounter\n● Conditional reset\n●\n20.3\n– Reset (if watchdog activated) when the downcounter value becomes less than\n0x40\n– Reset (if watchdog activated) if the downcounter is reloaded outside the window\n(see Figure 184)\nEarly wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when\nthe downcounter is equal to 0x40.\nWWDG functional description\nIf the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the\n7-bit downcounter (T[6:0] bits) rolls over from 0x40 to 0x3F (T6 becomes cleared), it initiates\na reset. If the software reloads the counter while the counter is greater than the value stored\nin the window register, then a reset is generated.\n480/1096\nDoc ID 13902 Rev 14 RM0008\nWindow watchdog (WWDG)\nFigure 183. Watchdog block diagram\nWatchdog configuration register (WWDG_CFR)\nRESET\n-\ncomparator\n= 1 when\nT6:0 > W6:0\nW6\nW5\nW4\nW3\nW2\nW1\nW0\nCMP\nWrite WWDG_CR\nWatchdog control register (WWDG_CR)\nWDGA T6\nT5\nT4\nT3\nT2\nT1\nT0\n6-bit downcounter (CNT)\nPCLK1\n(from RCC clock controller)\nWDG prescaler\n(WDGTB)\nThe application program must write in the WWDG_CR register at regular intervals during\nnormal operation to prevent an MCU reset. This operation must occur only when the counter\nvalue is lower than the window register value. The value to be stored in the WWDG_CR\nregister must be between 0xFF and 0xC0:\nEnabling the watchdog\nThe watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the\nWWDG_CR register, then it cannot be disabled again except by a reset.\nControlling the downcounter\nThis downcounter is free-running: It counts down even if the watchdog is disabled. When the\nwatchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.\nThe T[5:0] bits contain the number of increments which represents the time delay before the\nwatchdog produces a reset. The timing varies between a minimum and a maximum value\ndue to the unknown status of the prescaler when writing to the WWDG_CR register (see\nFigure 184).The Configuration register (WWDG_CFR) contains the high limit of the window:\nTo prevent a reset, the downcounter must be reloaded when its value is lower than the\nwindow register value and greater than 0x3F. Figure 184 describes the window watchdog\nprocess.\nNote:\nThe T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is\ncleared).\nAdvanced watchdog interrupt feature\nThe Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging\nmust be performed before the actual reset is generated. The EWI interrupt is enabled by\nsetting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value\n0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)\ncan be used to trigger specific actions (such as communications or data logging), before\nresetting the device.\nIn some applications, the EWI interrupt can be used to manage a software system check\nand/or system recovery/graceful degradation, without generating a WWDG reset. In this\nDoc ID 13902 Rev 14\n481/1096 Window watchdog (WWDG)\nRM0008\ncase, the corresponding interrupt service routine (ISR) should reload the WWDG counter to\navoid the WWDG reset, then trigger the required actions.\nThe EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.\nNote: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,\nthe WWDG reset will eventually be generated.\n20.4 How to program the watchdog timeout\nYou can use the formula in Figure 184 to calculate the WWDG timeout.\nWarning:\nWhen writing to the WWDG_CR register, always write 1 in the\nT6 bit to avoid generating an immediate reset.\nFigure 184. Window watchdog timing diagram\n4;\u0016\u001a\u0010= RM0008\nWindow watchdog (WWDG)\nTable 98.\n20.5\nMin-max timeout value @36 MHz (f PCLK1 )\nPrescaler WDGTB Min timeout value Max timeout value\n1 0 113 µs 7.28 ms\n2 1 227 µs 14.56 ms\n4 2 455 µs 29.12 ms\n8 3 910 µs 58.25 ms\nDebug mode\nWhen the microcontroller enters debug mode (Cortex™-M3 core halted), the WWDG\ncounter either continues to work normally or stops, depending on DBG_WWDG_STOP\nconfiguration bit in DBG module. For more details, refer to Section 31.16.2: Debug support\nfor timers, watchdog, bxCAN and I2C.\nDoc ID 13902 Rev 14\n483/1096 Window watchdog (WWDG)\n20.6\nRM0008\nWWDG registers\nRefer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions.\nThe peripheral registers can be accessed by half-words (16-bit) or words (32-bit).\n20.6.1\nControl register (WWDG_CR)\nAddress offset: 0x00\nReset value: 0x0000 007F\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nWDGA T[6:0]\nrs rw\nReserved\nBits 31:8 Reserved, must be kept at reset value.\nBit 7 WDGA: Activation bit\nThis bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the\nwatchdog can generate a reset.\n0: Watchdog disabled\n1: Watchdog enabled\nBits 6:0 T[6:0]: 7-bit counter (MSB to LSB)\nThese bits contain the value of the watchdog counter. It is decremented every (4096 x\n2 WDGTB ) PCLK1 cycles. A reset is produced when it rolls over from 0x40 to 0x3F (T6\nbecomes cleared).\n484/1096\nDoc ID 13902 Rev 14 RM0008\nWindow watchdog (WWDG)\n20.6.2\nConfiguration register (WWDG_CFR)\nAddress offset: 0x04\nReset value: 0x0000 007F\n31 30 29 28 27 26 25 24\n15 14 13 12 11 10 9 8\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nReserved\nEWI\n7\nWDGTB[1:0]\nW[6:0]\nReserved\nrs\nrw\nrw\nBit 31:10 Reserved, must be kept at reset value.\nBit 9 EWI: Early wakeup interrupt\nWhen set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is\nonly cleared by hardware after a reset.\nBits 8:7 WDGTB[1:0]: Timer base\nThe time base of the prescaler can be modified as follows:\n00: CK Counter Clock (PCLK1 div 4096) div 1\n01: CK Counter Clock (PCLK1 div 4096) div 2\n10: CK Counter Clock (PCLK1 div 4096) div 4\n11: CK Counter Clock (PCLK1 div 4096) div 8\nBits 6:0 W[6:0]: 7-bit window value\nThese bits contain the window value to be compared to the downcounter.\n20.6.3\nStatus register (WWDG_SR)\nAddress offset: 0x08\nReset value: 0x0000 0000\n31\n30\n29\n28\n27\n26\n25\n24\n23\n22 21 20 19 18 17 16\n6 5 4 3 2 1 0\nReserved\n15\n14\n13\n12\n11\n10\n9\n8\n7\nEWIF\nReserved\nrc_w0\nBit 31:1Reserved, must be kept at reset value.\nBit 0 EWIF: Early wakeup interrupt flag\nThis bit is set by hardware when the counter has reached the value 0x40. It must be cleared\nby software by writing ‘0. A write of ‘1 has no effect. This bit is also set if the interrupt is not\nenabled.\nDoc ID 13902 Rev 14\n485/1096 Window watchdog (WWDG)\n20.6.4\nRM0008\nWWDG register map\nThe following table gives the WWDG register map and reset values.\nWWDG_CR\nReserved\nReserved\nReset value\n0x08\nWWDG_SR\nReserved\nReset value\n0 0 0\n1\n1\n1\n1\n1\n1 1\n1 1\nW[6:0]\n1\n1\n1\n1\n1\n0\nRefer to Table 3 on page 50 for the register boundary addresses.\n486/1096\nWWDG_CFR\n0x04\n0\nReset value\nT[6:0]\n0x00\nWWDG register map and reset values\nRegister\nOffset\n31\nTable 99.\nDoc ID 13902 Rev 14 RM0008\n21\nFlexible static memory controller (FSMC)\nFlexible static memory controller (FSMC)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx and STM32F103xx microcontrollers where\nthe Flash memory density ranges between 32 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to high-density and XL-density devices only.\n21.1\nFSMC main features\nThe FSMC block is able to interface with synchronous and asynchronous memories and 16-\nbit PC memory cards. Its main purpose is to:\n● Translate the AHB transactions into the appropriate external device protocol\n● Meet the access timing requirements of the external devices\nAll external memories share the addresses, data and control signals with the controller.\nEach external device is accessed by means of a unique chip select. The FSMC performs\nonly one access at a time to an external device.\nThe FSMC has the following main features:\n●\nInterfaces with static memory-mapped devices including:\n– Static random access memory (SRAM)\n– Read-only memory (ROM)\n– NOR Flash memory\n– PSRAM (4 memory banks)\n● Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data\n● 16-bit PC Card compatible devices\n● Supports burst mode access to synchronous devices (NOR Flash and PSRAM)\n● 8- or 16-bit wide databus\n● Independent chip select control for each memory bank\n● Independent configuration for each memory bank\n● Programmable timings to support a wide range of devices, in particular:\n– Programmable wait states (up to 15)\n– Programmable bus turnaround cycles (up to 15)\n– Programmable output enable and write enable delays (up to 15)\n– Independent read and write timings and protocol, so as to support the widest\nvariety of memories and timings\nDoc ID 13902 Rev 14\n487/1096 Flexible static memory controller (FSMC)\nRM0008\n● Write enable and byte lane select outputs for use with PSRAM and SRAM devices\n● Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to\nexternal 16-bit or 8-bit devices\n● A Write FIFO, 2 words long, each word is 32 bits wide, only stores data and not the\naddress. Therefore, this FIFO only buffers AHB write burst transactions. This makes it\npossible to write to slow memories and free the AHB quickly for other operations. Only\none burst at a time is buffered: if a new AHB burst or single transaction occurs while an\noperation is in progress, the FIFO is drained. The FSMC will insert wait states until the\ncurrent memory access is complete).\n● External asynchronous wait control\nThe FSMC registers that define the external device type and associated characteristics are\nusually set at boot time and do not change until the next reset or power-up. However, it is\npossible to change the settings at any time.\n21.2\nBlock diagram\nThe FSMC consists of four main blocks:\n● The AHB interface (including the FSMC configuration registers)\n● The NOR Flash/PSRAM controller\n● The NAND Flash/PC Card controller\n● The external device interface\nThe block diagram is shown in Figure 185.\n488/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nFigure 185. FSMC block diagram\nFSMC interrupt to NVIC\nFrom clock\ncontroller\nHCLK\nNOR\nmemory\ncontroller\nConfiguration\nRegisters\nNAND/PC Card\nmemory\ncontroller\nFSMC_NE[4:1]\nFSMC_NL (or NADV)\nFSMC_NBL[1:0]\nFSMC_CLK\nNOR/PSRAM\nsignals\nFSMC_A[25:0]\nFSMC_D[15:0]\nFSMC_NOE\nFSMC_NWE\nFSMC_NWAIT Shared\nsignals\nFSMC_NCE[3:2]\nFSMC_INT[3:2] NAND\nsignals\nFSMC_INTR\nFSMC_NCE4_1\nFSMC_NCE4_2\nFSMC_NIORD\nFSMC_NIOWR\nFSMC_NIOS16\nFSMC_NREG\nFSMC_CD\nPC Card\nsignals\nai14718c\n21.3\nAHB interface\nThe AHB slave interface enables internal CPUs and other bus master peripherals to access\nthe external static memories.\nAHB transactions are translated into the external device protocol. In particular, if the\nselected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split\ninto consecutive 16- or 8-bit accesses. The Chip Select is kept low or toggles between the\nconsecutive accesses when perfoming 32-bit aligned or 32-bit unaligned accesses\nrespectively.\nThe FSMC generates an AHB error in the following conditions:\n● When reading or writing to an FSMC bank which is not enabled\n● When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the\nFSMC_BCRx register.\n● When reading or writing to the PC Card banks while the input pin FSMC_CD (Card\nPresence Detection) is low.\nDoc ID 13902 Rev 14\n489/1096 Flexible static memory controller (FSMC)\nRM0008\nThe effect of this AHB error depends on the AHB master which has attempted the R/W\naccess:\n● If it is the Cortex™-M3 CPU, a hard fault interrupt is generated\n● If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is\nautomatically disabled.\nThe AHB clock (HCLK) is the reference clock for the FSMC.\n21.3.1\nSupported memories and transactions\nGeneral transaction rules\nThe requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the\naccessed external device has a fixed data width. This may lead to inconsistent transfers.\nTherefore, some simple transaction rules must be followed:\n● AHB transaction size and memory data size are equal\nThere is no issue in this case.\n● AHB transaction size is greater than the memory size\nIn this case, the FSMC splits the AHB transaction into smaller consecutive memory\naccesses in order to meet the external data width.\n● AHB transaction size is smaller than the memory size\nAsynchronous transfers may or not be consistent depending on the type of external\ndevice.\n–\nAsynchronous accesses to devices that have the byte select feature (SRAM,\nROM, PSRAM).\na) FSMC allows write transactions accessing the right data through its byte lanes\nNBL[1:0]\nb) Read transactions are allowed. All memory bytes are read and the useless\nones are discarded. The NBL[1:0] are driven low during read transactions.\n– Asynchronous accesses to devices that do not have the byte select feature (NOR\nand NAND Flash 16-bit).\nThis situation occurs when a byte access is requested to a 16-bit wide Flash\nmemory. Clearly, the device cannot be accessed in byte mode (only 16-bit words\ncan be read from/written to the Flash memory) therefore:\na) Write transactions are not allowed\nb) Read transactions are allowed (the controller reads the entire 16-bit memory word\nand uses the needed byte only).\nConfiguration registers\nThe FSMC can be configured using a register set. See Section 21.5.6, for a detailed\ndescription of the NOR Flash/PSRAM controller registers. See Section 21.6.8, for a detailed\ndescription of the NAND Flash/PC Card registers.\n490/1096\nDoc ID 13902 Rev 14 RM0008\n21.4\nFlexible static memory controller (FSMC)\nExternal device address mapping\nFrom the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256\nMbytes each (Refer to Figure 186):\n● Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is\nsplit into 4 NOR/PSRAM regions with 4 dedicated Chip Select.\n● Banks 2 and 3 used to address NAND Flash devices (1 device per bank)\n● Bank 4 used to address a PC Card device\nFor each bank the type of memory to be used is user-defined in the Configuration register.\nFigure 186. FSMC memory banks\nAddress\nBanks\nSupported memory type\n6000 0000h\nBank 1\nNOR / PSRAM\n4 × 64 MB\n6FF F FFF Fh\n7000 0000h\nBank 2\n4 × 64 MB\n7FF F FFF Fh\nNAND Flash\n8000 0000h\nBank 3\n4 × 64 MB\n8FF F FFF Fh\n9000 0000h\nBank 4\nPC Card\n4 × 64 MB\n9FF F FFF Fh\nai14719\n21.4.1\nNOR/PSRAM address mapping\nHADDR[27:26] bits are used to select one of the four memory banks as shown in Table 100.\nTable 100. NOR/PSRAM bank selection\nHADDR[27:26] (1)\nSelected bank\n00 Bank 1 NOR/PSRAM 1\n01 Bank 1 NOR/PSRAM 2\n10 Bank 1 NOR/PSRAM 3\n11 Bank 1 NOR/PSRAM 4\n1. HADDR are internal AHB address lines that are translated to external memory.\nDoc ID 13902 Rev 14\n491/1096 Flexible static memory controller (FSMC)\nRM0008\nHADDR[25:0] contain the external memory address. Since HADDR is a byte address\nwhereas the memory is addressed in words, the address actually issued to the memory\nvaries according to the memory data width, as shown in the following table.\nTable 101. External memory address\nMemory width (1)\nData address issued to the memory\nMaximum memory capacity (bits)\n8-bit HADDR[25:0] 64 Mbytes x 8 = 512 Mbit\n16-bit HADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit\n1. In case of a 16-bit external memory width, the FSMC will internally use HADDR[25:1] to generate the\naddress for external memory FSMC_A[24:0].\nWhatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory\naddress A[0].\nWrap support for NOR Flash/PSRAM\nWrap burst mode for synchronous memories is not supported. The memories must be\nconfigured in linear burst mode of undefined length.\n21.4.2\nNAND/PC Card address mapping\nIn this case, three banks are available, each of them divided into memory spaces as\nindicated in Table 102.\nTable 102. Memory mapping and timing registers\nStart address End address\n0x9C00 0000 0x9FFF FFFF\nFSMC Bank\nMemory space Timing register\nI/O FSMC_PIO4 (0xB0)\n0x9800 0000 0x9BFF FFFF Bank 4 - PC card Attribute FSMC_PATT4 (0xAC)\n0x9000 0000 0x93FF FFFF Common FSMC_PMEM4 (0xA8)\n0x8800 0000 0x8BFF FFFF Attribute FSMC_PATT3 (0x8C)\nCommon FSMC_PMEM3 (0x88)\nAttribute FSMC_PATT2 (0x6C)\nCommon FSMC_PMEM2 (0x68)\nBank 3 - NAND Flash\n0x8000 0000 0x83FF FFFF\n0x7800 0000 0x7BFF FFFF\nBank 2- NAND Flash\n0x7000 0000\n0x73FF FFFF\nFor NAND Flash memory, the common and attribute memory spaces are subdivided into\nthree sections (see in Table 103 below) located in the lower 256 Kbytes:\n● Data section (first 64 Kbytes in the common/attribute memory space)\n● Command section (second 64 Kbytes in the common / attribute memory space)\n● Address section (next 128 Kbytes in the common / attribute memory space)\nTable 103. NAND bank selections\nSection name\n492/1096\nHADDR[17:16]\nAddress range\nAddress section 1X 0x020000-0x03FFFF\nCommand section 01 0x010000-0x01FFFF\nData section 00 0x000000-0x0FFFF\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nThe application software uses the 3 sections to access the NAND Flash memory:\n● To send a command to NAND Flash memory: the software must write the command\nvalue to any memory location in the command section.\n● To specify the NAND Flash address that must be read or written: the software must\nwrite the address value to any memory location in the address section. Since an\naddress can be 4 or 5 bytes long (depending on the actual memory size), several\nconsecutive writes to the address section are needed to specify the full address.\n● To read or write data: the software reads or writes the data value from or to any\nmemory location in the data section.\nSince the NAND Flash memory automatically increments addresses, there is no need to\nincrement the address of the data section to access consecutive memory locations.\n21.5\nNOR Flash/PSRAM controller\nThe FSMC generates the appropriate signal timings to drive the following types of\nmemories:\n●\n●\n●\nAsynchronous SRAM and ROM\n– 8-bit\n– 16-bit\n– 32-bit\nPSRAM (Cellular RAM)\n– Asynchronous mode\n– Burst mode\nNOR Flash\n– Asynchronous mode or burst mode\n– Multiplexed or nonmultiplexed\nThe FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals\n(addresses, data and control) are shared.\nFor synchronous accesses, the FSMC issues the clock (CLK) to the selected external\ndevice only during the read/write transactions. This clock is a submultiple of the HCLK clock.\nThe size of each bank is fixed and equal to 64 Mbytes.\nEach bank is configured by means of dedicated registers (see Section 21.5.6).\nThe programmable memory parameters include access timings (see Table 104) and support\nfor wait management (for PSRAM and NOR Flash accessed in burst mode).\nTable 104. Programmable NOR/PSRAM access parameters\nParameter\nFunction\nAccess mode\nUnit Min. Max.\nAddress\nsetup Duration of the address\nsetup phase Asynchronous AHB clock cycle\n(HCLK) 1 16\nAddress hold Duration of the address hold Asynchronous,\nphase\nmuxed I/Os AHB clock cycle\n(HCLK) 2 16\nData setup Duration of the data setup\nphase AHB clock cycle\n(HCLK) 2 256\nAsynchronous\nDoc ID 13902 Rev 14\n493/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 104. Programmable NOR/PSRAM access parameters (continued)\nParameter\n21.5.1\nFunction\nAccess mode\nUnit\nAsynchronous and AHB clock cycle\nsynchronous read (HCLK)\nMin. Max.\n1 16\nBust turn Duration of the bus\nturnaround phase Clock divide\nratio Number of AHB clock cycles\n(HCLK) to build one memory Synchronous\nclock cycle (CLK) AHB clock cycle\n(HCLK) 2 16\nData latency Number of clock cycles to\nissue to the memory before\nthe first data of the burst Memory clock\ncycle (CLK) 2 17\nSynchronous\nExternal memory interface signals\nTable 105, Table 106 and Table 107 list the signals that are typically used to interface NOR\nFlash, SRAM and PSRAM.\nNote:\nPrefix “N”. specifies the associated signal as active low.\nNOR Flash, nonmultiplexed I/Os\nTable 105. Nonmultipled I/O NOR Flash\nFSMC signal name\nI/O\nFunction\nCLK O Clock (for synchronous burst)\nA[25:0] O Address bus\nD[15:0] I/O Bidirectional data bus\nNE[x] O Chip select, x = 1..4\nNOE O Output enable\nNWE O Write enable\nNL(=NADV) O Latch enable (this signal is called address\nvalid, NADV, by some NOR Flash devices)\nNWAIT I NOR Flash wait input signal to the FSMC\nNOR Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26\naddress lines).\nNOR Flash, multiplexed I/Os\nTable 106. Multiplexed I/O NOR Flash\n494/1096\nFSMC signal name I/O\nFunction\nCLK O Clock (for synchronous burst)\nA[25:16] O Address bus\nAD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus\nNE[x] O Chip select, x = 1..4\nNOE O Output enable\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nTable 106. Multiplexed I/O NOR Flash (continued)\nFSMC signal name I/O\nFunction\nNWE O Write enable\nNL(=NADV) O Latch enable (this signal is called address valid, NADV, by some NOR\nFlash devices)\nNWAIT I NOR Flash wait input signal to the FSMC\nNOR-Flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit\n(26 address lines).\nPSRAM/SRAM\nTable 107. Nonmultiplexed I/Os PSRAM/SRAM\nFSMC signal name I/O\nFunction\nCLK O Clock (only for PSRAM synchronous burst)\nA[25:0] O Address bus\nD[15:0] I/O Data bidirectional bus\nNE[x] O Chip select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))\nNOE O Output enable\nNWE O Write enable\nNL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)\nNWAIT I PSRAM wait input signal to the FSMC\nNBL[1] O Upper byte enable (memory signal name: NUB)\nNBL[0] O Lowed byte enable (memory signal name: NLB)\nPSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26\naddress lines).\nDoc ID 13902 Rev 14\n495/1096 Flexible static memory controller (FSMC)\n21.5.2\nRM0008\nSupported memories and transactions\nTable 108 below displays an example of the supported devices, access modes and\ntransactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM.\nTransactions not allowed (or not supported) by the FSMC in this example appear in gray.\nTable 108. NOR Flash/PSRAM supported memories and transactions\nMode R/W AHB\ndata\nsize Memory\ndata size Asynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous\nNOR Flash\n(muxed I/Os\nand nonmuxed Asynchronous\nI/Os) R 32 16 Y Split into 2 FSMC\naccesses\nW 32 16 Y Split into 2 FSMC\naccesses\nAsynchronous\npage R - 16 N Mode is not supported\nSynchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y Asynchronous R 8 16 Y Asynchronous W 8 16 Y Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FSMC\naccesses\nAsynchronous W 32 16 Y Split into 2 FSMC\naccesses\nAsynchronous\npage R - 16 N Mode is not supported\nSynchronous R 8 16 N Synchronous R 16 16 Y Synchronous R 32 16 Y Synchronous W 8 16 Y Synchronous W 16/32 16 Y\nDevice\nPSRAM\n(multiplexed\nI/Os and\nnonmultiplexed\nI/Os)\n496/1096\nDoc ID 13902 Rev 14\nAllowed/\nnot\nallowed\nComments\nUse of byte lanes NBL[1:0]\nUse of byte lanes NBL[1:0] RM0008\nFlexible static memory controller (FSMC)\nTable 108. NOR Flash/PSRAM supported memories and transactions (continued)\nDevice\nSRAM and\nROM\n21.5.3\nMode R/W AHB\ndata\nsize Memory\ndata size Asynchronous R 8 / 16 16 Y Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0]\nAsynchronous R 32 16 Y Split into 2 FSMC\naccesses\nAsynchronous W 32 16 Y Split into 2 FSMC\naccesses\nAllowed/\nnot\nallowed\nComments\nGeneral timing rules\nSignals synchronization\n21.5.4\n● All controller output signals change on the rising edge of the internal clock (HCLK)\n● In synchronous read and write mode, the output data changes on the falling edge of the\nmemory clock (FSMC_CLK).\nNOR Flash/PSRAM controller asynchronous transactions\nAsynchronous static memories (NOR Flash, SRAM)\n● Signals are synchronized by the internal clock HCLK. This clock is not issued to the\nmemory\n● The FSMC always samples the data before de-asserting the chip select signal NE. This\nguarantees that the memory data-hold timing constraint is met (chip enable high to\ndata transition, usually 0 ns min.)\n● When extended mode is set, it is possible to mix modes A, B, C and D in read and write\n(it is for instance possible to read in mode A and write in mode B).\nDoc ID 13902 Rev 14\n497/1096 Flexible static memory controller (FSMC)\nRM0008\nMode 1 - SRAM/CRAM\nFigure 187. Mode1 read accesses\nMemory transaction\nA[25:0]\nNBL[1:0]\nNEx\nNOE\nNWE\nHigh\ndata driven\nby memory\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\n2 HCLK\ncycles\nData sampled Data strobe\nai14720c\nFigure 188. Mode1 write accesses\nMemory transaction\nA[25:0]\nNBL[1:0]\nNEx\nNOE\n1HCLK\nNWE\nD[15:0]\ndata driven by FSMC\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai14721c\n1. NBL[1:0] are driven low during read access.\n498/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nThe one HCLK cycle at the end of the write transaction helps guarantee the address and\ndata hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the\nDATAST value must be greater than zero (DATAST > 0).\nTable 109. FSMC_BCRx bit fields\nBit\nnumber\nBit name\n31-16\n15\nValue to set\n0x0000\nASYNCWAIT\n14-10\nSet to 1 if the memory supports this feature. Otherwise keep at 0.\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6\nFACCEN\n-\n5-4 MWID As needed\n3-2 MTYP As needed, exclude 10 (NOR Flash)\n1 MUXEN 0x0\n0 MBKEN 0x1\nTable 110. FSMC_BTRx bit fields\nBit\nnumber\nBit name\n31-16\n15-8\n0x0000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the second access phase (DATAST+1 HCLK cycles for\nwrite accesses, DATAST+3 HCLK cycles for read accesses).\nThis value cannot be 0 (minimum is 1).\n0x0\nADDSET\nDuration of the first access phase (ADDSET+1 HCLK cycles).\nDoc ID 13902 Rev 14\n499/1096 Flexible static memory controller (FSMC)\nRM0008\nMode A - SRAM/PSRAM (CRAM) OE toggling\nFigure 189. ModeA read accesses\nMemory transaction\nA[25:0]\nNBL[1:0]\nNEx\nNOE\nNWE\nHigh\ndata driven\nby memory\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1) 2 HCLK\nHCLK cycles cycles\nData sampled\nData strobe\nai14722c\nFigure 190. ModeA write accesses\nMemory transaction\nA[25:0]\nNBL[1:0]\nNEx\nNOE\n1HCLK\nNWE\nD[15:0]\ndata driven by FSMC\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai14721c\n1. NBL[1:0] are driven low during read access.\n500/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nThe differences compared with mode1 are the toggling of NOE and the independent read\nand write timings.\nTable 111. FSMC_BCRx bit fields\nBit\nnumber\nBit name\n31-16\nValue to set\n0x0000\n15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.\n14 EXTMOD 0x1\n13-10\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6 FACCEN -\n5-4 MWID As needed\n3-2 MTYP As needed, exclude 10 (NOR Flash)\n1 MUXEN 0x0\n0 MBKEN 0x1\nTable 112. FSMC_BTRx bit fields\nBit\nnumber\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\n0x0\n0x000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the second access phase (DATAST+3 HCLK cycles) in\nread. This value cannot be 0 (minimum is 1)\n0x0\nADDSET\nDuration of the first access phase (ADDSET+1 HCLK cycles) in read.\nTable 113. FSMC_BWTRx bit fields\nBit\nnumber\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\nValue to set\n0x0\n0x000\nDATAST\nDuration of the second access phase (DATAST+1 HCLK cycles) in\nwrite. This value cannot be 0 (minimum is 1).\nDoc ID 13902 Rev 14\n501/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 113. FSMC_BWTRx bit fields (continued)\nBit\nnumber\nBit name\n7-4\n3-0\nValue to set\n0x0\nDuration of the first access phase (ADDSET+1 HCLK cycles) in write\nADDSET\nMode 2/B - NOR Flash\nFigure 191. Mode2/B read accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\nNWE\nHigh\ndata driven\nby memory\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1) 2 HCLK\nHCLK cycles cycles\nData sampled Data strobe\nai14724c\n502/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nFigure 192. Mode2 write accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\n1HCLK\nNWE\ndata driven by FSMC\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai14723b\nFigure 193. ModeB write accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\n1HCLK\nNWE\nD[15:0]\ndata driven by FSMC\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai15110b\nThe differences with mode1 are the toggling of NADV and the independent read and write\ntimings when extended mode is set (Mode B).\nDoc ID 13902 Rev 14\n503/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 114. FSMC_BCRx bit fields\nBit\nnumber\nBit name\n31-16\nValue to set\n0x0000\n15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.\n14 EXTMOD 0x1 for mode B, 0x0 for mode 2\n13-10\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6 FACCEN 0x1\n5-4 MWID As needed\n3-2 MTYP 10 (NOR Flash)\n1 MUXEN 0x0\n0 MBKEN 0x1\nTable 115. FSMC_BTRx bit fields\nBit number\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\n0x1 if extended mode is set\n0x000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the access second phase (DATAST+3 HCLK cycles) in\nread. This value can not be 0 (minimum is 1)\n0x0\nADDSET\nDuration of the access first phase (ADDSET+1 HCLK cycles) in\nread.\nTable 116. FSMC_BWTRx bit fields\nBit\nnumber\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\n504/1096\n0x1 if extended mode is set\n0x000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the access second phase (DATAST+1 HCLK cycles) in\nwrite. This value can not be 0 (minimum is 1).\n0x0\nADDSET\nDuration of the access first phase (ADDSET+1 HCLK cycles) in\nwrite.\nDoc ID 13902 Rev 14 RM0008\nNote:\nFlexible static memory controller (FSMC)\nThe FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its\ncontent is don’t care.\nMode C - NOR Flash - OE toggling\nFigure 194. ModeC read accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\nNWE\nHigh\ndata driven\nby memory\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1) 2 HCLK\nHCLK cycles cycles\nData sampled Data strobe\nai14725c\nFigure 195. ModeC write accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\n1HCLK\nNWE\nD[15:0]\ndata driven by FSMC\n(ADDSET +1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai14723b\nDoc ID 13902 Rev 14\n505/1096 Flexible static memory controller (FSMC)\nRM0008\nThe differences compared with mode1 are the toggling of NOE and NADV and the\nindependent read and write timings.\nTable 117. FSMC_BCRx bit fields\nBit No.\nBit name\n31-16\nValue to set\n0x0000\n15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.\n14 EXTMOD 0x1\n13-10\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6 FACCEN 1\n5-4 MWID As needed\n3-2 MTYP 0x02 (NOR Flash)\n1 MUXEN 0x0\n0 MBKEN 0x1\nTable 118. FSMC_BTRx bit fields\nBit No.\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\n0x2\n0x000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the second access phase (DATAST+3 HCLK cycles) in\nread. This value cannot be 0 (minimum is 1)\n0x0\nADDSET\nDuration of the first access phase (ADDSET+1 HCLK cycles) in\nread.\nTable 119. FSMC_BWTRx bit fields\nBit No.\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n15-8\n506/1096\n0x2\n0x000\nDATAST\n7-4\n3-0\nValue to set\nDuration of the second access phase (DATAST+1 HCLK cycles) in\nwrite. This value cannot be 0 (minimum is 1)\n0x0\nADDSET\nDuration of the first access phase (ADDSET+1 HCLK cycles) in\nwrite.\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nMode D - asynchronous access with extended address\nFigure 196. ModeD read accesses\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\nNWE\nHigh\ndata driven\nby memory\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(ADDHLD + 1)\nHCLK cycles\n(DATAST + 1) 2 HCLK\nHCLK cycles cycles\nData sampled Data strobe\nai14726c\nModeD write accessesThe differences with mode1 are the toggling of NADV, NOE that\nMemory transaction\nA[25:0]\nNADV\nNEx\nNOE\n1HCLK\nNWE\ndata driven by FSMC\nD[15:0]\n(ADDSET +1)\nHCLK cycles\n(ADDHLD + 1)\nHCLK cycles\n(DATAST + 1)\nHCLK cycles\nai14727c\ngoes on toggling after NADV changes and the independent read and write timings.\nDoc ID 13902 Rev 14\n507/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 120. FSMC_BCRx bit fields\nBit No.\nBit name\n31-16\nValue to set\n0x0000\n15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.\n14 EXTMOD 0x1\n13-10\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6 FACCEN Set according to memory support\n5-4 MWID As needed\n3-2 MTYP As needed\n1 MUXEN 0x0\n0 MBKEN 0x1\nTable 121. FSMC_BTRx bit fields\nBit No.\nBit name\n31-30\n29-28\nValue to set\n0x0\nACCMOD\n27-16\n0x2\n0x000\n15-8 DATAST Duration of the second access phase (DATAST+3 HCLK cycles) in\nread. This value cannot be 0 (minimum is 1)\n7-4 ADDHLD Duration of the middle phase of the read access (ADDHLD+1 HCLK\ncycles)\n3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in\nread.\nTable 122. FSMC_BWTRx bit fields\nBit No.\nBit name\n31-30\n29-28\n0x0\nACCMOD\n27-16\n508/1096\nValue to set\n0x2\n0x000\n15-8 DATAST Duration of the second access phase (DATAST+1 HCLK cycles) in\nwrite. This value cannot be 0 (minimum is 1)\n7-4 ADDHLD Duration of the middle phase of the write access (ADDHLD+1 HCLK\ncycles)\n3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in write.\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nMode muxed - asynchronous access muxed NOR Flash\nFigure 197. Multiplexed read accesses\nMemory transaction\nA[25:16]\nNADV\nNEx\nNOE\nNWE\nHigh\nAD[15:0]\ndata driven\nby memory\nLower address\n1HCLK cycle\n(ADDSET +1) (DATAST + 1)\nHCLK cycles HCLK cycles\n(ADDHLD + 1)\nHCLK cycles\n2 HCLK\ncycles\n(BUSTURN + 1) (1)\nHCLK cycles\nData sampled Data strobe\nai14728c\n1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so\nBUSTURN ≤ 5 has not impact.\nFigure 198. Multiplexed write accesses\nMemory transaction\nA[25:16]\nNADV\nNEx\nNOE\n1HCLK\nNWE\nAD[15:0]\nLower address\n(ADDSET +1)\nHCLK cycles\nADDHLD\nHCLK cycles\ndata driven by FSMC\n(DATAST + 2)\nHCLK cycles\nai14729c\nThe difference with mode D is the drive of the lower address byte(s) on the databus.\nDoc ID 13902 Rev 14\n509/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 123. FSMC_BCRx bit fields\nBit No.\nBit name\n31-16\nValue to set\n0x0000\n15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.\n14 EXTMOD 0x0\n13-10\n0x0\n9 WAITPOL Meaningful only if bit 15 is 1\n8 BURSTEN 0x0\n7\n-\n6 FACCEN 0x1\n5-4 MWID As needed\n3-2 MTYP 0x2 (NOR)\n1 MUXEN 0x1\n0 MBKEN 0x1\nTable 124. FSMC_BTRx bit fields\nBit No.\nBit name\n31-20\nValue to set\n0x0000\nDuration of the last phase of the access (BUSTURN+1 HCLK)\n19-16 BUSTURN 15-8 DATAST Duration of the second access phase (DATAST+3 HCLK cycles for\nread accesses and DATAST+1 HCLK cycles for write accesses).\nThis value cannot be 0 (minimum is 1)\n7-4 ADDHLD Duration of the middle phase of the access (ADDHLD+1 HCLK\ncycles).This value cannot be 0 (minimum is 1).\n3-0 ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles).\nWAIT management in asynchronous accesses\nIf the asynchronous memory asserts a WAIT signal to advise that it's not yet ready to accept\nor to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.\nIf the WAIT signal is active (high or low depending on the WAITPOL bit), the second access\nphase (Data setup phase) programmed by the DATAST bits, is extended until WAIT\nbecomes inactive. Unlike the data setup phase, the first access phases (Address setup and\nAddress hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT\nsensitive and so they are not prolonged.\nThe data phase must be programmed so that WAIT can be detected 4 HCLK cycles before\nthe data sampling. The following cases must be considered:\n510/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\n1.\nMemory asserts the WAIT signal aligned to NOE/NWE which toggles:\ndata_setup phase >= 4 * HCLK + max_wait_assertion_time\n2.\nMemory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):\nif max_wait_assertion_time > (address_phase + hold_phase)\ndata_setup phase >= 4 * HCLK + (max_wait_assertion_time - address_phase -\nhold_phase)\notherwise\ndata_setup phase >= 4 * HCLK\nWhere max_wait_assertion_time is the maximum time taken by the memory to assert the\nWAIT signal once NEx/NOE/NWE is low.\nThe Figure 199 and Figure 200 show the number of HCLK clock cycles that memory\naccess is extended after WAIT is removed by the asynchronous memory (independently of\nthe above cases).\nFigure 199. Asynchronous wait during a read access\nMemory transaction\nA[25:0]\nADDRESS Flexible static memory controller (FSMC)\nRM0008\nFigure 200. Asynchronous wait during a write access\nMemory transaction\nA[25:0]\naddress phase\ndata phase\nNEx\nNWAIT\ndon’t care\n1HCLK\nNWE\nD[15:0]\ndata driven by FSMC\n3HCLK\nai15797\n512/1096\nDoc ID 13902 Rev 14 RM0008\n21.5.5\nFlexible static memory controller (FSMC)\nSynchronous burst transactions\nThe memory clock, CLK, is a submultiple of HCLK according to the value of parameter\nCLKDIV.\nNOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet\nthis constraint, the FSMC does not issue the clock to the memory during the first internal\nclock cycle of the synchronous access (before NADV assertion). This guarantees that the\nrising edge of the memory clock occurs in the middle of the NADV low pulse.\nData latency versus NOR Flash latency\nThe data latency is the number of cycles to wait before sampling the data. The DATLAT\nvalue must be consistent with the latency value specified in the NOR Flash configuration\nregister. The FSMC does not include the clock cycle when NADV is low in the data latency\ncount.\nCaution:\nSome NOR Flash memories include the NADV Low cycle in the data latency count, so the\nexact relation between the NOR Flash latency and the FMSC DATLAT parameter can be\neither of:\n● NOR Flash latency = DATLAT + 2\n● NOR Flash latency = DATLAT + 3\nSome recent memories assert NWAIT during the latency phase. In such cases DATLAT can\nbe set to its minimum value. As a result, the FSMC samples the data and waits long enough\nto evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and\nreal data are taken.\nOther memories do not assert NWAIT during latency. In this case the latency must be set\ncorrectly for both the FSMC and the memory, otherwise invalid data are mistaken for good\ndata, or valid data are lost in the initial phase of the memory access.\nSingle-burst transfer\nWhen the selected bank is configured in synchronous burst mode, if an AHB single-burst\ntransaction is requested, the FSMC performs a burst transaction of length 1 (if the AHB\ntransfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select\nsignal when the last data is strobed.\nClearly, such a transfer is not the most efficient in terms of cycles (compared to an\nasynchronous read). Nevertheless, a random asynchronous access would first require to re-\nprogram the memory access mode, which would altogether last longer.\nWait management\nFor synchronous burst NOR Flash, NWAIT is evaluated after the programmed latency\nperiod, (DATALAT+2) CLK clock cycles.\nIf NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1),\nwait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low\nlevel when WAITPOL = 1).\nWhen NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)\nor on the next clock edge (bit WAITCFG = 0).\nDoc ID 13902 Rev 14\n513/1096 Flexible static memory controller (FSMC)\nRM0008\nDuring wait-state insertion via the NWAIT signal, the controller continues to send clock\npulses to the memory, keeping the chip select and output enable signals valid, and does not\nconsider the data valid.\nThere are two timing configurations for the NOR Flash NWAIT signal in burst mode:\n● Flash memory asserts the NWAIT signal one data cycle before the wait state (default\nafter reset)\n● Flash memory asserts the NWAIT signal during the wait state\nThese two NOR Flash wait state configurations are supported by the FSMC, individually for\neach chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).\nFigure 201. Wait configurations\nMemory transaction = burst of 4 half words\nHCLK\nCLK\nA[25:16]\naddr[25:16]\nNADV\nNWAIT\n(WAITCFG = 0)\nNWAIT\n(WAITCFG = 1)\ninserted wait state\nA/D[15:0]\nAddr[15:0]\ndata\ndata\ndata\nai15798\n514/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nFigure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)\n-EMORY Flexible static memory controller (FSMC)\nRM0008\nTable 125. FSMC_BCRx bit fields (continued)\nBit No.\nBit name\nValue to set\n8 BURSTEN 0x1\n7 FWPRLVL Set to protect memory from accidental write access\n6 FACCEN Set according to memory support\n5-4 MWID As needed\n3-2 MTYP 0x1 or 0x2\n1 MUXEN As needed\n0 MBKEN 0x1\nTable 126. FSMC_BTRx bit fields\nBit No.\n516/1096\nBit name\nValue to set\n27-24 DATLAT Data latency\n23-20 CLKDIV 0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16 BUSTURN no effect\n15-8 DATAST no effect\n7-4 ADDHLD no effect\n3-0 ADDSET no effect\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nFigure 203. Synchronous multiplexed write mode - PSRAM (CRAM)\nMemory transaction = burst of 2 half words\nHCLK\nCLK\nA[25:16]\naddr[25:16]\nNEx\nHi-Z\nNOE\nNWE\nNADV\nNWAIT\n(WAITCFG = 0)\n(DATALAT + 2)\nCLK cycles\nA/D[15:0]\nAddr[15:0]\ninserted wait state\ndata\ndata\n1 clock 1 clock\ncycle\ncycle\nai14731d\n1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.\n2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.\nDoc ID 13902 Rev 14\n517/1096 Flexible static memory controller (FSMC)\nRM0008\nTable 127. FSMC_BCRx bit fields\nBit No.\nBit name\n31-20\n19\nValue to set\n0x0000\nCBURSTRW\n18-15\n0x1\n0x0\n14 EXTMOD 0x0\n13 WAITEN When high, the first data after latency period is taken as always\nvalid, regardless of the wait from memory value\n12 WREN no effect on synchronous read\n11 WAITCFG 0x0\n10 WRAPMOD no effect\n9 WAITPOL to be set according to memory\n8 BURSTEN no effect on synchronous write\n7 FWPRLVL Set to protect memory from accidental writes\n6 FACCEN Set according to memory support\n5-4 MWID As needed\n3-2 MTYP 0x1\n1 MUXEN As needed\n0 MBKEN 0x1\nTable 128. FSMC_BTRx bit fields\nBit No.\n518/1096\nBit name\nValue to set\n31-30 - 0x0\n27-24 DATLAT Data latency\n23-20 CLKDIV 0x0 to get CLK = HCLK (not supported)\n0x1 to get CLK = 2 × HCLK\n19-16 BUSTURN No effect\n15-8 DATAST No effect\n7-4 ADDHLD No effect\n3-0 ADDSET No effect\nDoc ID 13902 Rev 14 RM0008\n21.5.6\nFlexible static memory controller (FSMC)\nNOR/PSRAM controller registers\nThe peripheral registers have to be accessed by words (32-bit).\nSRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4)\nAddress offset: 0xA000 0000 + 8 * (x – 1), x = 1...4\nReset value: 0x0000 30DX\nrw\nrw\n3\nrw\nrw rw\n2 1 rw 4 rw rw rw\nrw\n5\nrw\n6\nrw\n7\nrw\nrw\n8\nrw\n9\n14 13 12 11 10\nrw\nReserved\n15\nReserved\nCBURSTRW\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16\nThis register contains the control information of each memory bank, used for SRAMs, ROMs\nand asynchronous or burst NOR Flash memories.\n0\nBit 19 CBURSTRW: Write burst enable.\nFor Cellular RAM, the bit enables synchronous burst protocol during write operations. For Flash\nmemory access in burst mode, this bit enables/disables the wait state insertion via the NWAIT\nsignal. The enable bit for the synchronous burst protocol during read access is the BURSTEN bit in\nthe FSMC_BCRx register.\n0: Write operations are always performed in asynchronous mode\n1: Write operations are performed in synchronous mode.\nBit 15 ASYNCWAIT: Wait signal during asynchronous transfers\nThis bit enables the FSMC to use the wait signal even during an asynchronous protocol.\n0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after\nreset)\n1: NWAIT signal is taken in to account when running an asynchronous protocol\nBit 14 EXTMOD: Extended mode enable.\nThis bit enables the FSMC to program inside the FSMC_BWTR register, so it allows different\ntimings for read and write.\n0: values inside FSMC_BWTR register are not taken into account (default after reset)\n1: values inside FSMC_BWTR register are taken into account\nBit 13 WAITEN: Wait enable bit.\nFor Flash memory access in burst mode, this bit enables/disables wait-state insertion via the\nNWAIT signal:\n0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the\nprogrammed Flash latency period)\n1: NWAIT signal is enabled (its level is taken into account after the programmed Flash latency\nperiod to insert wait states if asserted) (default after reset)\nBit 12 WREN: Write enable bit.\nThis bit indicates whether write operations are enabled/disabled in the bank by the FSMC:\n0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,\n1: Write operations are enabled for the bank by the FSMC (default after reset).\nDoc ID 13902 Rev 14\n519/1096 Flexible static memory controller (FSMC)\nRM0008\nBit 11 WAITCFG: Wait timing configuration.\nFor memory access in burst mode, the NWAIT signal indicates whether the data from the memory\nare valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted\nby the memory one clock cycle before the wait state or during the wait state:\n0: NWAIT signal is active one data cycle before wait state (default after reset),\n1: NWAIT signal is active during wait state (not for Cellular RAM).\nBit 10 WRAPMOD: Wrapped burst mode support.\nDefines whether the controller will or not split an AHB burst wrap access into two linear accesses.\nValid only when accessing memories in burst mode\n0: Direct wrapped burst is not enabled (default after reset),\n1: Direct wrapped burst is enabled.\nNote: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers.\nBit 9 WAITPOL: Wait signal polarity bit.\nDefines the polarity of the wait signal from memory. Valid only when accessing the memory in burst\nmode:\n0: NWAIT active low (default after reset),\n1: NWAIT active high.\nBit 8 BURSTEN: Burst enable bit.\nEnables the burst access mode for the memory. Valid only with synchronous burst memories:\n0: Burst access mode disabled (default after reset)\n1: Burst access mode enable\nBit 7\nReserved, must be kept at reset value..\nBit 6 FACCEN: Flash access enable\nEnables NOR Flash memory access operations.\n0: Corresponding NOR Flash memory access is disabled\n1: Corresponding NOR Flash memory access is enabled (default after reset)\nBits 5:4 MWID: Memory databus width.\nDefines the external memory device width, valid for all type of memories.\n00: 8 bits,\n01: 16 bits (default after reset),\n10: reserved, do not use,\n11: reserved, do not use.\nBits 3:2 MTYP: Memory type.\nDefines the type of external memory attached to the corresponding memory bank:\n00: SRAM, ROM (default after reset for Bank 2...4)\n01: PSRAM (Cellular RAM: CRAM)\n10: NOR Flash(default after reset for Bank 1)\n11: reserved\nBit 1 MUXEN: Address/data multiplexing enable bit.\nWhen this bit is set, the address and data values are multiplexed on the databus, valid only with\nNOR and PSRAM memories:\n0: Address/Data nonmultiplexed\n1: Address/Data multiplexed on databus (default after reset)\nBit 0 MBKEN: Memory bank enable bit.\nEnables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a\ndisabled bank causes an ERROR on AHB bus.\n0: Corresponding memory bank is disabled\n1: Corresponding memory bank is enabled\n520/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nSRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)\nAddress offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank, used for SRAMs, ROMs\nand NOR Flash memories. If the EXTMOD bit is set in the FSMC_BCRx register, then this\nregister is partitioned for write and read access, that is, 2 registers are available: one to\nconfigure read accesses (this register) and one to configure write accesses (FSMC_BWTRx\nregisters).\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n8 7 6\nrw\nrw\nrw\nrw\nrw\nrw\nrw rw rw rw\n5 4 3 2\nrw rw rw rw\nrw\n1 0\nrw rw\n9\nBUSTURN\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nBits 29:28 ACCMOD: Access mode\nSpecifies the asynchronous access modes as shown in the timing diagrams. These bits are\ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT: Data latency for synchronous burst NOR Flash memory\nFor NOR Flash with synchronous burst mode enabled, defines the number of memory clock\ncycles (+2) to issue to the memory before getting the first data:\n0000: Data latency of 2 CLK clock cycles for first burst access\n1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nNote: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)\nperiods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.\nIn the case of CRAM, this field must be set to ‘0’.\nBits 23:20 CLKDIV: Clock divide ratio (for CLK signal)\nDefines the period of CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001: CLK period = 2 × HCLK periods\n0010: CLK period = 3 × HCLK periods\n1111: CLK period = 16 × HCLK periods (default value after reset)\nIn asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.\nBits 19:16 BUSTURN: Bus turnaround phase duration\nThese bits are written by software to insert the bus turnaround delay after a read access only\nfrom multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive\naddresses on the databus for the next side-by-side transaction. BUSTURN can be set to the\nminimum if the slowest memory does not take more than 6 HCLK clock cycles to put the\ndatabus in Hi-Z state.\n0000: BUSTURN phase duration = 1 × HCLK clock cycle\n...\n1111: BUSTURN phase duration = 16 × HCLK clock cycles (default value after reset)\nDoc ID 13902 Rev 14\n521/1096 Flexible static memory controller (FSMC)\nRM0008\nBits 15:8 DATAST: Data-phase duration\nThese bits are written by software to define the duration of the data phase (refer to\nFigure 187 to Figure 198), used in SRAMs, ROMs and asynchronous NOR Flash accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 2 × HCLK clock cycles\n0000 0010: DATAST phase duration = 3 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 256 × HCLK clock cycles (default value after reset)\nFor each memory type and access mode data-phase duration, please refer to the respective\nfigure (Figure 187 to Figure 198).\nExample: Mode1, read access, DATAST=1: Data-phase duration= DATAST+3 = 4 HCLK\nclock cycles.\nNote: In synchronous accesses, this value is don't care.\nBits 7:4 ADDHLD: Address-hold phase duration\nThese bits are written by software to define the duration of the address hold phase (refer to\nFigure 196 to Figure 198), used in mode D and multiplexed accesses:\n0000: Reserved\n0001: ADDHLD phase duration = 2 × HCLK clock cycle\n0010: ADDHLD phase duration = 3 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)\nFor each access mode address-hold phase duration, please refer to the respective figure\n(Figure 196 to Figure 198).\nExample: ModeD, read access, ADDHLD=1: Address-hold phase duration = ADDHLD + 1 =2\nHCLK clock cycles.\nNote: In synchronous accesses, this value is not used, the address hold phase is always 1\nmemory clock period duration.\nBits 3:0 ADDSET: Address setup phase duration\nThese bits are written by software to define the duration of the address setup phase (refer to\nFigure 187 to Figure 198), used in SRAMs, ROMs and asynchronous NOR Flash accesses:\n0000: ADDSET phase duration = 1 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)\nFor each access mode address setup phase duration, please refer to the respective figure\n(refer to Figure 187 to Figure 198).\nExample: Mode2, read access, ADDSET=1: Address setup phase duration = ADDSET + 1 =\n2 HCLK clock cycles.\nNote: In synchronous accesses, this value is don’t care.\nNote:\nPSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these\nmemories issue the NWAIT signal during the whole latency phase to prolong the latency as\nneeded.\nWith PSRAMs (CRAMs) the filed DATLAT must be set to 0, so that the FSMC exits its\nlatency phase soon and starts sampling NWAIT from memory, then starts to read or write\nwhen the memory is ready.\nThis method can be used also with the latest generation of synchronous Flash memories\nthat issue the NWAIT signal, unlike older Flash memories (check the datasheet of the\nspecific Flash memory being used).\nSRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)\nAddress offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4\n522/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nReset value: 0x0FFF FFFF\nThis register contains the control information of each memory bank, used for SRAMs, ROMs\nand NOR Flash memories. When the EXTMOD bit is set in the FSMC_BCRx register, then\nthis register is active for write access.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nRes.\nACCM\nOD\nrw\nrw\nDATLAT\nCLKDIV\n9\n8\n7\nDATAST\n6\n5\n4\n3\nADDHLD\n2\n1\n0\nADDSET\nReserved\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 29:28 ACCMOD: Access mode.\nSpecifies the asynchronous access modes as shown in the next timing diagrams.These bits are\ntaken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.\n00: access mode A\n01: access mode B\n10: access mode C\n11: access mode D\nBits 27:24 DATLAT: Data latency (for synchronous burst NOR Flash).\nFor NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles\n(+2) to issue to the memory before getting the first data:\n0000: (0x0) Data latency of 2 CLK clock cycles for first burst access\n...\n1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)\nNote: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In\nasynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of\nCRAM, this field must be set to 0\nBits 23:20 CLKDIV: Clock divide ratio (for CLK signal).\nDefines the period of CLK clock output signal, expressed in number of HCLK cycles:\n0000: Reserved\n0001 CLK period = 2 × HCLK periods\n0010 CLK period = 3 × HCLK periods\n1111: CLK period = 16 × HCLK periods (default value after reset)\nIn asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.\nBits 19:16\nReserved\nBits 15:8 DATAST: Data-phase duration.\nThese bits are written by software to define the duration of the data phase (refer to Figure 187 to\nFigure 198), used in SRAMs, ROMs and asynchronous NOR Flash accesses:\n0000 0000: Reserved\n0000 0001: DATAST phase duration = 2 × HCLK clock cycles\n0000 0010: DATAST phase duration = 3 × HCLK clock cycles\n...\n1111 1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset)\nNote: In synchronous accesses, this value is don't care.\nDoc ID 13902 Rev 14\n523/1096 Flexible static memory controller (FSMC)\nRM0008\nBits 7:4 ADDHLD: Address-hold phase duration.\nThese bits are written by software to define the duration of the address hold phase (refer to\nFigure 196 to Figure 198), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash\naccesses:\n0000: Reserved\n0001: ADDHLD phase duration = 2 × HCLK clock cycle\n0010: ADDHLD phase duration = 3 × HCLK clock cycle\n...\n1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always\n1 Flash clock period duration.\nBits 3:0 ADDSET: Address setup phase duration.\nThese bits are written by software to define the duration of the address setup phase in HCLK\ncycles (refer to Figure 196 to Figure 198), used in SRAMs, ROMs and asynchronous NOR Flash\naccessed:\n0000: ADDSET phase duration = 1 × HCLK clock cycle\n...\n1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)\nNote: In synchronous NOR Flash accesses, this value is don’t care.\n21.6\nNAND Flash/PC Card controller\nThe FSMC generates the appropriate signal timings to drive the following types of device:\n●\n●\nNAND Flash\n– 8-bit\n– 16-bit\n16-bit PC Card compatible devices\nThe NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support\nNAND Flash devices. Bank 4 supports PC Card devices.\nEach bank is configured by means of dedicated registers (Section 21.6.8). The\nprogrammable memory parameters include access timings (shown in Table 129) and ECC\nconfiguration.\n524/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nTable 129. Programmable NAND/PC Card access parameters\nParameter\n21.6.1\nFunction\nAccess mode\nUnit\nMin. Max.\nMemory setup\ntime Number of clock cycles (HCLK)\nto set up the address before the\ncommand assertion Read/Write AHB clock cycle\n(HCLK) 1 256\nMemory wait Minimum duration (HCLK clock\nRead/Write\ncycles) of the command assertion AHB clock cycle\n(HCLK) 2 256\nMemory hold Number of clock cycles (HCLK)\nto hold the address (and the data\nRead/Write\nin case of a write access) after\nthe command de-assertion AHB clock cycle\n(HCLK) 1 255\nMemory\ndatabus high-Z Number of clock cycles (HCLK)\nduring which the databus is kept\nin high-Z state after the start of a\nwrite access AHB clock cycle\n(HCLK) 0 255\nWrite\nExternal memory interface signals\nThe following tables list the signals that are typically used to interface NAND Flash and PC\nCard.\nCaution: When using a PC Card or a CompactFlash in I/O mode, the NIOS16 input pin must remain\nat ground level during the whole operation, otherwise the FSMC may not operate properly.\nThis means that the NIOS16 input pin must not be connected to the card, but directly to\nground (only 16-bit accesses are allowed).\nNote: Prefix “N”. specifies the associated signal as active low.\n8-bit NAND Flash\nt\nTable 130. 8-bit NAND Flash\nFSMC signal name\nI/O\nFunction\nA[17] O NAND Flash address latch enable (ALE) signal\nA[16] O NAND Flash command latch enable (CLE) signal\nD[7:0] I/O 8-bit multiplexed, bidirectional address/data bus\nNCE[x] O Chip select, x = 2, 3\nNOE(= NRE) O Output enable (memory signal name: read enable, NRE)\nNWE O Write enable\nNWAIT/INT[3:2] I NAND Flash ready/busy input signal to the FSMC\nThere is no theoretical capacity limitation as the FSMC can manage as many address\ncycles as needed.\nDoc ID 13902 Rev 14\n525/1096 Flexible static memory controller (FSMC)\nRM0008\n16-bit NAND Flash\nTable 131. 16-bit NAND Flash\nFSMC signal name\nI/O\nFunction\nA[17] O NAND Flash address latch enable (ALE) signal\nA[16] O NAND Flash command latch enable (CLE) signal\nD[15:0] I/O 16-bit multiplexed, bidirectional address/data bus\nNCE[x] O Chip select, x = 2, 3\nNOE(= NRE) O Output enable (memory signal name: read enable, NRE)\nNWE O Write enable\nNWAIT/INT[3:2] I NAND Flash ready/busy input signal to the FSMC\nThere is no theoretical capacity limitation as the FSMC can manage as many address\ncycles as needed.\nTable 132. 16-bit PC Card\n526/1096\nFSMC signal name I/O\nFunction\nA[10:0] O Address bus\nNIOS16 I Data transfer in I/O space. It must be shorted to GND (16-bit transfer\nonly)\nNIORD O Output enable for I/O space\nNIOWR O Write enable for I/O space\nNREG O Register signal indicating if access is in Common or Attribute space\nD[15:0] I/O Bidirectional databus\nNCE4_1 O Chip select 1\nNCE4_2 O Chip select 2 (indicates if access is 16-bit or 8-bit)\nNOE O Output enable in Common and in Attribute space\nNWE O Write enable in Common and in Attribute space\nNWAIT I PC Card wait input signal to the FSMC (memory signal name\nIORDY)\nINTR I PC Card interrupt to the FSMC (only for PC Cards that can generate\nan interrupt)\nCD I PC Card presence detection. Active high. If an access is performed\nto the PC Card banks while CD is low, an AHB error is generated.\nRefer to Section 21.3: AHB interface\nDoc ID 13902 Rev 14 RM0008\n21.6.2\nFlexible static memory controller (FSMC)\nNAND Flash / PC Card supported memories and transactions\nTable 133 below shows the supported devices, access modes and transactions.\nTransactions not allowed (or not supported) by the NAND Flash / PC Card controller appear\nin gray.\nTable 133. Supported memories and transactions\nDevice\nAHB\nMemory\nAllowed/\ndata size data size not allowed\nMode R/W\nComments\nAsynchronous R 8 8 Y Asynchronous W 8 8 Y Asynchronous R 16 8 Y Split into 2 FSMC accesses\nAsynchronous W 16 8 Y Split into 2 FSMC accesses\nAsynchronous R 32 8 Y Split into 4 FSMC accesses\nAsynchronous W 32 8 Y Split into 4 FSMC accesses\nAsynchronous R 8 16 Y Asynchronous W 8 16 N Asynchronous R 16 16 Y Asynchronous W 16 16 Y Asynchronous R 32 16 Y Split into 2 FSMC accesses\nAsynchronous W 32 16 Y Split into 2 FSMC accesses\nNAND 8-bit\nNAND 16-bit\n21.6.3\nTiming diagrams for NAND and PC Card\nEach PC Card/CompactFlash and NAND Flash memory bank is managed through a set of\nregisters:\n● Control register: FSMC_PCRx\n● Interrupt status register: FSMC_SRx\n● ECC register: FSMC_ECCRx\n● Timing register for Common memory space: FSMC_PMEMx\n● Timing register for Attribute memory space: FSMC_PATTx\n● Timing register for I/O space: FSMC_PIOx\nEach timing configuration register contains three parameters used to define number of\nHCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,\nplus one parameter that defines the timing for starting driving the databus in the case of a\nwrite. Figure 204 shows the timing parameter definitions for common memory accesses,\nknowing that Attribute and I/O (only for PC Card) memory space access timings are similar.\nDoc ID 13902 Rev 14\n527/1096 Flexible static memory controller (FSMC)\nRM0008\nFigure 204. NAND/PC Card controller timing for common memory access\nHCLK\nAddress\nNCEx (2)\nNREG, High\nNIOW,\nNIOR\nMEMxSET + 1\nMEMxWAIT + 1\nMEMxHOLD + 1\nNWE,\nNOE (1)\nMEMxHIZ\nwrite_data\nread_data\nValid\nai14732d\n1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access.\n2. NCEx goes low as soon as NAND access is requested and remains low until a different memory bank is accessed.\n21.6.4\nNAND Flash operations\nThe command latch enable (CLE) and address latch enable (ALE) signals of the NAND\nFlash device are driven by some address signals of the FSMC controller. This means that to\nsend a command or an address to the NAND Flash memory, the CPU has to perform a write\nto a certain address in its memory space.\nA typical page read operation from the NAND Flash device is as follows:\n528/1096\n1. Program and enable the corresponding memory bank by configuring the FSMC_PCRx\nand FSMC_PMEMx (and for some devices, FSMC_PATTx, see Section 21.6.5: NAND\nFlash pre-wait functionality on page 529) registers according to the characteristics of\nthe NAND Flash (PWID bits for the databus width of the NAND Flash, PTYP = 1,\nPWAITEN = 1, PBKEN = 1, see section Common memory space timing register 2..4\n(FSMC_PMEM2..4) on page 535 for timing configuration).\n2. The CPU performs a byte write in the common memory space, with data byte equal to\none Flash command byte (for example 0x00 for Samsung NAND Flash devices). The\nCLE input of the NAND Flash is active during the write strobe (low pulse on NWE), thus\nthe written byte is interpreted as a command by the NAND Flash. Once the command\nis latched by the NAND Flash device, it does not need to be written for the following\npage read operations.\n3. The CPU can send the start address (STARTAD) for a read operation by writing four\nbytes (or three for smaller capacity devices), STARTAD[7:0], then STARTAD[16:9],\nSTARTAD[24:17] and finally STARTAD[25] for 64 Mb x 8 bit NAND Flash) in the\ncommon memory or attribute space. The ALE input of the NAND Flash device is active\nduring the write strobe (low pulse on NWE), thus the written bytes are interpreted as\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nthe start address for read operations. Using the attribute memory space makes it\npossible to use a different timing configuration of the FSMC, which can be used to\nimplement the prewait functionality needed by some NAND Flash memories (see\ndetails in Section 21.6.5: NAND Flash pre-wait functionality on page 529).\n21.6.5\n4. The controller waits for the NAND Flash to be ready (R/NB signal high) to become\nactive, before starting a new access (to same or another memory bank). While waiting,\nthe controller maintains the NCE signal active (low).\n5. The CPU can then perform byte read operations in the common memory space to read\nthe NAND Flash page (data field + Spare field) byte by byte.\n6. The next NAND Flash page can be read without any CPU command or address write\noperation, in three different ways:\n– by simply performing the operation described in step 5\n– a new random address can be accessed by restarting the operation at step 3\n– a new command can be sent to the NAND Flash device by restarting at step 2\nNAND Flash pre-wait functionality\nSome NAND Flash devices require that, after writing the last part of the address, the\ncontroller wait for the R/NB signal to go low as shown in Figure 205.\nFigure 205. Access to non ‘CE don’t care’ NAND-Flash\nNCE must stay low\nNCE\nCLE\nALE\nNWE\nHigh\nNOE\ntR\nI/O[7:0]\n0x00\nA7-A0\nA16-A9 A24-A17 A25\ntWB\nR/NB\n(1)\n(2)\n(3)\n(4)\n(5)\nai14733\n1. CPU wrote byte 0x00 at address 0x7001 0000.\n2. CPU wrote byte A7~A0 at address 0x7002 0000.\n3. CPU wrote byte A16~A9 at address 0x7002 0000.\n4. CPU wrote byte A24~A17 at address 0x7002 0000.\n5. CPU wrote byte A25 at address 0x7802 0000: FSMC performs a write access using FSMC_PATT2 timing\ndefinition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > t WB max). This guarantees that\nNCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where\nNCE is not don’t care).\nDoc ID 13902 Rev 14\n529/1096 Flexible static memory controller (FSMC)\nRM0008\nWhen this functionality is needed, it can be guaranteed by programming the MEMHOLD\nvalue to meet the t WB timing, however any CPU read or write access to the NAND Flash\nthen has the hold delay of (MEMHOLD + 1) HCLK cycles inserted from the rising edge of\nthe NWE signal to the next access.\nTo overcome this timing constraint, the attribute memory space can be used by\nprogramming its timing register with an ATTHOLD value that meets the t WB timing, and\nleaving the MEMHOLD value at its minimum. Then, the CPU must use the common memory\nspace for all NAND Flash read and write accesses, except when writing the last address\nbyte to the NAND Flash device, where the CPU must write to the attribute memory space.\n21.6.6\nError correction code computation ECC (NAND Flash)\nThe FSMC PC-Card controller includes two error correction code computation hardware\nblocks, one per memory bank. They are used to reduce the host CPU workload when\nprocessing the error correction code by software in the system.\nThese two registers are identical and associated with bank 2 and bank 3, respectively. As a\nconsequence, no hardware ECC computation is available for memories connected to bank\n4.\nThe error correction code (ECC) algorithm implemented in the FSMC can perform 1-bit error\ncorrection and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read\nfrom or written to NAND Flash.\nThe ECC modules monitor the NAND Flash databus and read/write signals (NCE and NWE)\neach time the NAND Flash memory bank is active.\nThe functional operations are:\n● When access to NAND Flash is made to bank 2 or bank 3, the data present on the\nD[15:0] bus is latched and used for ECC computation.\n● When access to NAND Flash occurs at any other address, the ECC logic is idle, and\ndoes not perform any operation. Thus, write operations for defining commands or\naddresses to NAND Flash are not taken into account for ECC computation.\nOnce the desired number of bytes has been read from/written to the NAND Flash by the\nhost CPU, the FSMC_ECCR2/3 registers must be read in order to retrieve the computed\nvalue. Once read, they should be cleared by resetting the ECCEN bit to zero. To compute a\nnew data block, the ECCEN bit must be set to one in the FSMC_PCR2/3 registers.\n21.6.7\nPC Card/CompactFlash operations\nAddress spaces & memory accesses\nThe FSMC supports Compact Flash storage or PC Cards in Memory Mode and I/O Mode\n(True IDE mode is not supported).\nThe Compact Flash storage and PC Cards are made of 3 memory spaces:\n● Common Memory Space\n● Attribute Space\n● I/O Memory Space\nThe nCE2 and nCE1 pins (FSMC_NCE4_2 and FSMC_NCE4_1 respectively) select the\ncard and indicate whether a byte or a word operation is being performed: nCE2 accesses\n530/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nthe odd byte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on\nD7-0 if A0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.\nThe memory space is selected by asserting low nOE for read accesses or nWE for write\naccesses, combined with the low assertion of nCE2/nCE1 and nREG.\n● If pin nREG=1 during the memory access, the common memory space is selected\n● If pin nREG=0 during the memory access, the attribute memory space is selected\nThe I/O Space is selected by asserting low nIORD for read accesses or nIOWR for write\naccesses [instead of nOE/nWE for memory Space], combined with nCE2/nCE1. Note that\nnREG must also be asserted low during accesses to I/O Space.\nThree type of accesses are allowed for a 16-bit PC Card:\n●\nAccesses to Common Memory Space for data storage can be either 8-bit accesses at\neven addresses or 16 bit AHB accesses.\nNote that 8-bit accesses at odd addresses are not supported and will not lead to the\nlow assertion of nCE2. A 32-bit AHB request is translated into two 16-bit memory\naccesses.\n●\nAccesses to Attribute Memory Space where the PC Card stores configuration\ninformation are limited to 8-bit AHB accesses at even addresses.\nNote that a 16-bit AHB access will be converted into a single 8-bit memory transfer:\nnCE1 will be asserted low, NCE2 will be asserted high and only the even Byte on D7-\nD0 will be valid. Instead a 32-bit AHB access will be converted into two 8-bit memory\ntransfers at even addresses: nCE1 will be asserted low, NCE2 will be asserted high\nand only the even bytes will be valid.\n●\nAccesses to I/O Space must be limited to AHB 16 bit accesses.\nTable 134. 16-bit PC-Card signals and access type\n1 0 1 0 1 X X X-X X\nYES\n0 1 1 0 1 X X X-X X\n0 0 1 0 1 X X X-X X 0 0 0 1 0 1 X-X\nSpace\nAccess Type\nAllowed/not\nAllowed\nYES\nCommon\nMemory\nSpace\nRead/Write byte on D7-D0\nYES\nRead/Write byte on D15-D8 Not supported\n0 Read/Write word on D15-D0 YES\n0 Read or Write Configuration\nRegisters YES\nRead or Write CIS (Card\nInformation Structure) YES\nRead or Write (odd address) YES\nRead or Write (odd address) YES\nAttribute\nSpace\nX 0 0 0 1 0 0 X-X 0\n1 0 0 0 1 X X X-X 1\n0 1 0 0 1 X X X-X x\nInvalid\nAttribute\nSpace\nDoc ID 13902 Rev 14\n531/1096 Flexible static memory controller (FSMC)\nRM0008\nnOE/nWE nIORD\nTable 134. 16-bit PC-Card signals and access type (continued)\n1 0 0 1 0 X X X-X 0 Read Even Byte on D7-0 Not supported\n1 0 0 1 0 X X X-X 1 Read Odd Byte on D7-0 Not supported\n1 0 0 1 0 X X X-X 0 Write Even Byte on D7-0 Not supported\n1 0 0 1 0 X X X-X 1 Write Odd Byte on D7-0 Not supported\nSpace\nAccess Type\nAllowed/not\nAllowed\nI/O space\n0 0 0 1 0 X X X-X 0 Read Word on D15-0 YES\n0 0 0 1 0 X X X-X 0 Write word on D15-0 YES\n0 1 0 1 0 X X X-X X Read Odd Byte on D15-8 Not supported\n0 1 0 1 0 X X X-X X Write Odd Byte on D15-8 Not supported\nThe FSMC Bank 4 gives access to those 3 memory spaces as described in Section 21.4.2:\nNAND/PC Card address mapping - Table 102: Memory mapping and timing registers\nWait Feature\nThe CompactFlash Storage or PC Card may request the FSMC to extend the length of the\naccess phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT\nsignal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the\nPWAITEN bit in the FSMC_PCRx register. In order to detect the nWAIT assertion correctly,\nthe MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:\nxxWAITx >= 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once\nnOE/nWE or nIORD/nIOWR is low.\nAfter the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock\ncycles.\n532/1096\nDoc ID 13902 Rev 14 RM0008\n21.6.8\nFlexible static memory controller (FSMC)\nNAND Flash/PC Card controller registers\nThe peripheral registers have to be accessed by words (32-bit).\nPC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4)\nAddress offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4\nrw\nrw\nrw\nrw\nrw\n5\nrw\nrw\nrw\nrw\nrw\n4\nPWID Res. rw rw rw rw rw\nrw\n3\n2\n1\n0\n8\nTCLR\nReserved\nrw\n6\nTAR\n7\nECCPS\n9\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nReset value: 0x0000 0018\nBits 19:17 ECCPS: ECC page size.\nDefines the page size for the extended ECC:\n000: 256 bytes\n001: 512 bytes\n010: 1024 bytes\n011: 2048 bytes\n100: 4096 bytes\n101: 8192 bytes\nBits 16:13 TAR: ALE to RE delay.\nSets time from ALE low to RE low in number of AHB clock cycles (HCLK).\nTime is: t_ar = (TAR + SET + 4) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 12:9 TCLR: CLE to RE delay.\nSets time from CLE low to RE low in number of AHB clock cycles (HCLK).\nTime is t_clr = (TCLR + SET + 4) × THCLK where THCLK is the HCLK clock period\n0000: 1 HCLK cycle (default)\n1111: 16 HCLK cycles\nNote: SET is MEMSET or ATTSET according to the addressed space.\nBits 8:7\nReserved, must be kept at reset value..\nBits 6 ECCEN: ECC computation logic enable bit\n0: ECC logic is disabled and reset (default after reset),\n1: ECC logic is enabled.\nBits 5:4 PWID: Databus width.\nDefines the external memory device width.\n00: 8 bits (default after reset)\n01: 16 bits (mandatory for PC Card)\n10: reserved, do not use\n11: reserved, do not use\nBit 3 PTYP: Memory type.\nDefines the type of device attached to the corresponding memory bank:\n0: PC Card, CompactFlash, CF+ or PCMCIA\n1: NAND Flash (default after reset)\nDoc ID 13902 Rev 14\n533/1096 Flexible static memory controller (FSMC)\nRM0008\nBit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.\nEnables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB\nbus\n0: Corresponding memory bank is disabled (default after reset)\n1: Corresponding memory bank is enabled\nBit 1 PWAITEN: Wait feature enable bit.\nEnables the Wait feature for the PC Card/NAND Flash memory bank:\n0: disabled\n1: enabled\nNote: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx\nbits must be programmed to a value as follows:\nxxWAITx ≥ 4 + max_wait_assertion_time/HCLK\nWhere max_wait_assertion_time is the maximum time taken by NWAIT to go low once\nnOE/nWE or nIORD/nIOWR is low.\nBit 0\nReserved, must be kept at reset value..\nFIFO status and interrupt register 2..4 (FSMC_SR2..4)\nAddress offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4\nReset value: 0x0000 0040\nThis register contains information about FIFO status and interrupt. The FSMC has a FIFO\nthat is used when writing to memories to store up to16 words of data from the AHB.\nThis is used to quickly write to the AHB and free it for transactions to peripherals other than\nthe FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its\nbits that indicates the status of the FIFO, for ECC purposes.\nThe ECC is calculated while the data are written to the memory, so in order to read the\ncorrect ECC the software must wait until the FIFO is empty.\nBit 6 FEMPT: FIFO empty.\nRead-only bit that provides the status of the FIFO\n0: FIFO not empty\n1: FIFO empty\nBit 5 IFEN: Interrupt falling edge detection enable bit\n0: Interrupt falling edge detection request disabled\n1: Interrupt falling edge detection request enabled\nBit 4 ILEN: Interrupt high-level detection enable bit\n0: Interrupt high-level detection request disabled\n1: Interrupt high-level detection request enabled\nBit 3 IREN: Interrupt rising edge detection enable bit\n0: Interrupt rising edge detection request disabled\n1: Interrupt rising edge detection request enabled\n534/1096\nDoc ID 13902 Rev 14\nrw\n3\n2\n1\n0\nr\n4\n5\n6\n7\nIREN\n8\n9\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nrw rw rw rw rw RM0008\nFlexible static memory controller (FSMC)\nBit 2 IFS: Interrupt falling edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt falling edge occurred\n1: Interrupt falling edge occurred\nBit 1 ILS: Interrupt high-level status\nThe flag is set by hardware and reset by software.\n0: No Interrupt high-level occurred\n1: Interrupt high-level occurred\nBit 0 IRS: Interrupt rising edge status\nThe flag is set by hardware and reset by software.\n0: No interrupt rising edge occurred\n1: Interrupt rising edge occurred\nCommon memory space timing register 2..4 (FSMC_PMEM2..4)\nAddress offset: Address: 0xA000 0000 + 0x48 + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PMEMx (x = 2..4) read/write register contains the timing information for PC\nCard or NAND Flash memory bank x, used for access to the common memory space of the\n16-bit PC Card/CompactFlash, or to access the NAND Flash for command, address write\naccess and data read/write access.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nMEMHIZx\nrw\nrw\nrw\nrw\nrw\nMEMHOLDx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n9\n8\n7\n6\n5\nMEMWAITx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n4\n3\n2 1 0\nrw rw rw\nMEMSETx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nBits 31:24 MEMHIZx: Common memory x databus HiZ time\nDefines the number of HCLK (+1 only for NAND) clock cycles during which the databus is\nkept in HiZ after the start of a PC Card/NAND Flash write access to common memory space\non socket x. Only valid for write transaction:\n0000 0000: (0x00) 0 HCLK cycle (for PC Card)\n1111 1111: (0xFF) 255 HCLK cycles (for PC Card) - (default value after reset)\nBits 23:16 MEMHOLDx: Common memory x hold time\nDefines the number of HCLK clock cycles to hold address (and data for write access) after\nthe command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to\ncommon memory space on socket x:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 15:8 MEMWAITx: Common memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,\nNOE), for PC Card/NAND Flash read or write access to common memory space on socket\nx. The duration for command assertion is extended if the wait signal (NWAIT) is active (low)\nat the end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)\n(default value after reset)\nDoc ID 13902 Rev 14\n535/1096 Flexible static memory controller (FSMC)\nRM0008\nBits 7:0 MEMSETx: Common memory x setup time\nDefines the number of HCLK (+1 for PC Card, +2 for NAND) clock cycles to set up the\naddress before the command assertion (NWE, NOE), for PC Card/NAND Flash read or write\naccess to common memory space on socket x:\n0000 0000: 1 HCLK cycle (for PC Card) / HCLK cycles (for NAND Flash)\n1111 1111: 256 HCLK cycles (for PC Card) / 257 HCLK cycles (for NAND Flash) - (default\nvalue after reset)\nAttribute memory space timing registers 2..4 (FSMC_PATT2..4)\nAddress offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4\nReset value: 0xFCFC FCFC\nEach FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC\nCard/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the\nattribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the\nlast address write access if the timing must differ from that of previous accesses (for\nReady/Busy management, refer to Section 21.6.5: NAND Flash pre-wait functionality).\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nATTHIZx\nrw\nrw\nrw\nrw\nrw\nATTHOLDx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n9 8 7 6 5\nrw rw rw rw rw\nATTWAITx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n4\n3\n2 1 0\nrw rw rw\nATTSETx\nrw\nrw\nrw\nBits 31:24 ATTHIZx: Attribute memory x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the\nstart of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only\nvalid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 23:16 ATTHOLDx: Attribute memory x hold time\nDefines the number of HCLK clock cycles to hold address (and data for write access) after\nthe command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to\nattribute memory space on socket x\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 15:8 ATTWAITx: Attribute memory x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,\nNOE), for PC Card/NAND Flash read or write access to attribute memory space on socket x.\nThe duration for command assertion is extended if the wait signal (NWAIT) is active (low) at\nthe end of the programmed value of HCLK:\n0000 0000: reserved\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)\n(default value after reset)\n536/1096\nDoc ID 13902 Rev 14 RM0008\nFlexible static memory controller (FSMC)\nBits 7:0 ATTSETx: Attribute memory x setup time\nDefines the number of HCLK (+1) clock cycles to set up address before the command\nassertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory\nspace on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles (default value after reset)\nI/O space timing register 4 (FSMC_PIO4)\nAddress offset: 0xA000 0000 + 0xB0\nReset value: 0xFCFCFCFC\nThe FSMC_PIO4 read/write registers contain the timing information used to gain access to\nthe I/O space of the 16-bit PC Card/CompactFlash.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\nIOHIZx\nrw\nrw\nrw\nrw\nrw\nIOHOLDx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n9 8 7 6 5\nrw rw rw rw rw\nIOWAITx\nrw\nrw\nrw\nrw\nrw\nrw\nrw\nrw\n4\n3\n2 1 0\nrw rw rw\nIOSETx\nrw\nrw\nrw\nBits 31:24 IOHIZx: I/O x databus HiZ time\nDefines the number of HCLK clock cycles during which the databus is kept in HiZ after the\nstart of a PC Card write access to I/O space on socket x. Only valid for write transaction:\n0000 0000: 0 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 23:16 IOHOLDx: I/O x hold time\nDefines the number of HCLK clock cycles to hold address (and data for write access) after\nthe command deassertion (NWE, NOE), for PC Card read or write access to I/O space on\nsocket x:\n0000 0000: reserved\n0000 0001: 1 HCLK cycle\n1111 1111: 255 HCLK cycles (default value after reset)\nBits 15:8 IOWAITx: I/O x wait time\nDefines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,\nSMNOE), for PC Card read or write access to I/O space on socket x. The duration for\ncommand assertion is extended if the wait signal (NWAIT) is active (low) at the end of the\nprogrammed value of HCLK:\n0000 0000: reserved, do not use this value\n0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)\n1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)\n(default value after reset)\nBits 7:0 IOSETx: I/O x setup time\nDefines the number of HCLK (+1) clock cycles to set up the address before the command\nassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:\n0000 0000: 1 HCLK cycle\n1111 1111: 256 HCLK cycles (default value after reset)\nDoc ID 13902 Rev 14\n537/1096 Flexible static memory controller (FSMC)\nRM0008\nECC result registers 2/3 (FSMC_ECCR2/3)\nAddress offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3\nReset value: 0x0000 0000\nThese registers contain the current error correction code value computed by the ECC\ncomputation modules of the FSMC controller (one module per NAND Flash memory bank).\nWhen the CPU reads the data from a NAND Flash memory page at the correct address\n(refer to Section 21.6.6: Error correction code computation ECC (NAND Flash)), the data\nread from or written to the NAND Flash are processed automatically by ECC computation\nmodule. At the end of X bytes read (according to the ECCPS field in the FSMC_PCRx\nregisters), the CPU must read the computed ECC value from the FSMC_ECCx registers,\nand then verify whether these computed parity data are the same as the parity value\nrecorded in the spare area, to determine whether a page is valid, and, to correct it if\napplicable. The FSMC_ECCRx registers should be cleared after being read by setting the\nECCEN bit to zero. For computing a new data block, the ECCEN bit must be set to one.\n31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10\n9\n8\n7\n6\n5\n4\n3\n2\n1\nECCx\nr\nBits 31:0 ECCx: ECC result\nThis field provides the value computed by the ECC computation logic. Table 135 hereafter\ndescribes the contents of these bit fields.\nTable 135. ECC result relevant bits\nECCPS[2:0]\n538/1096\nPage size in bytes\nECC bits\n000 256 ECC[21:0]\n001 512 ECC[23:0]\n010 1024 ECC[25:0]\n011 2048 ECC[27:0]\n100 4096 ECC[29:0]\n101 8192 ECC[31:0]\nDoc ID 13902 Rev 14\n0 RM0008\n21.6.9\nFlexible static memory controller (FSMC)\nFSMC register map\nThe following table summarizes the FSMC registers.\nReserved\nReserved\nFSMC_BCR1\n0xA000\n0000 Register\nOffset\n31\nTable 136. FSMC register map\nBUSTURN DATAST ADDHLD ADDSET\n0xA000\n0014 FSMC_BTR3 Res. ACCM\nOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET\n0xA000\n001C FSMC_BTR4 Res. ACCM\nOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET\nACCM\n0xA000\nFSMC_BWTR1 Res.\nOD\n0104 DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET\nACCM\n0xA000\nFSMC_BWTR2 Res.\nOD\n010C DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET\nACCM\n0xA000\nFSMC_BWTR3 Res.\nOD\n0114 DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET\nACCM\n0xA000\nFSMC_BWTR4 Res.\nOD\n011C DATLAT CLKDIV Reserved DATAST ADDHLD ADDSET\n0xA000\n0060 FSMC_PCR2 Reserved ECCPS TAR TCLR Res. PWID 0xA000\n0080 FSMC_PCR3 Reserved ECCPS TAR TCLR Res. PWID 0xA000\n00A0 FSMC_PCR4 Reserved ECCPS TAR TCLR Res. 0xA000\n0064 FSMC_SR2 Reserved 0xA000\n0084 FSMC_SR3 Reserved 0xA000\n00A4 FSMC_SR4 Reserved\nReserved\nPWAITEN\n0xA000\nFSMC_PMEM2\n0068 MEMHIZx MEMHOLDx MEMWAITx MEMSETx\n0xA000\nFSMC_PMEM3\n0088 MEMHIZx MEMHOLDx MEMWAITx MEMSETx\nDoc ID 13902 Rev 14\nPWID\nCLKDIV DATLAT ACCM\nOD Res. FSMC_BTR2 0xA000\n000C ADDSET\nADDHLD DATAST BUSTURN CLKDIV DATLAT ACCM\nOD Res. FSMC_BTR1 0xA000\n0004\nReserved\nReserved FSMC_BCR4 0xA000\n0018\nReserved\nReserved FSMC_BCR3 0xA000\n0010\nReserved\nReserved FSMC_BCR2 0xA000\n0008\nASYNCWAIT\nCBURSTRW\nReset value\n539/1096 Flexible static memory controller (FSMC)\nRM0008\nOffset\nRegister\nTable 136. FSMC register map (continued)\n0xA000\nFSMC_PMEM4\n00A8 MEMHIZx MEMHOLDx MEMWAITx MEMSETx\n0xA000\nFSMC_PATT2\n006C ATTHIZx ATTHOLDx ATTWAITx ATTSETx\n0xA000\nFSMC_PATT3\n008C ATTHIZx ATTHOLDx ATTWAITx ATTSETx\n0xA000\nFSMC_PATT4\n00AC ATTHIZx ATTHOLDx ATTWAITx ATTSETx\nIOHIZx IOHOLDx IOWAITx IOSETx\n0xA000\n00B0\nFSMC_PIO4\n0xA000\nFSMC_ECCR2\n0074 ECCx\n0xA000\nFSMC_ECCR3\n0094 ECCx\nRefer to Table 3 on page 50 for the register boundary addresses.\n540/1096\nDoc ID 13902 Rev 14 RM0008\n22\nSecure digital input/output interface (SDIO)\nSecure digital input/output interface (SDIO)\nLow-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 16 and 32 Kbytes.\nMedium-density devices are STM32F101xx, STM32F102xx and STM32F103xx\nmicrocontrollers where the Flash memory density ranges between 64 and 128 Kbytes.\nHigh-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 256 and 512 Kbytes.\nXL-density devices are STM32F101xx and STM32F103xx microcontrollers where the\nFlash memory density ranges between 768 Kbytes and 1 Mbyte.\nConnectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\nThis section applies to high-density and XL-density performance line devices only.\n22.1\nSDIO main features\nThe SD/SDIO MMC card host interface (SDIO) provides an interface between the AHB\nperipheral bus and MultiMediaCards (MMCs), SD memory cards, SDIO cards and CE-ATA\ndevices.\nThe MultiMediaCard system specifications are available through the MultiMediaCard\nAssociation website at www.mmca.org, published by the MMCA technical committee.\nSD memory card and SD I/O card system specifications are available through the SD card\nAssociation website at www.sdcard.org.\nCE-ATA system specifications are available through the CE-ATA workgroup website at\nwww.ce-ata.org.\nThe SDIO features include the following:\nNote:\n● Full compliance with MultiMediaCard System Specification Version 4.2. Card support\nfor three different databus modes: 1-bit (default), 4-bit and 8-bit\n● Full compatibility with previous versions of MultiMediaCards (forward compatibility)\n● Full compliance with SD Memory Card Specifications Version 2.0\n● Full compliance with SD I/O Card Specification Version 2.0: card support for two\ndifferent databus modes: 1-bit (default) and 4-bit\n● Full support of the CE-ATA features (full compliance with CE-ATA digital protocol\nRev1.1)\n● Data transfer up to 48 MHz for the 8 bit mode\n● Data and command output enable signals to control external bidirectional drivers.\n1 The SDIO does not have an SPI-compatible communication mode.\n2 The SD memory card protocol is a superset of the MultiMediaCard protocol as defined in the\nMultiMediaCard system specification V2.11. Several commands required for SD memory\ndevices are not supported by either SD I/O-only cards or the I/O portion of combo cards.\nSome of these commands have no use in SD I/O devices, such as erase commands, and\nthus are not supported in the SDIO. In addition, several commands are different between SD\nmemory cards and SD I/O cards and thus are not supported in the SDIO. For details refer to\nSD I/O card Specification Version 1.0. CE-ATA is supported over the MMC electrical\nDoc ID 13902 Rev 14\n541/1096 Secure digital input/output interface (SDIO)\nRM0008\ninterface using a protocol that utilizes the existing MMC access primitives. The interface\nelectrical and signaling definition is as defined in the MMC reference.\nThe MultiMediaCard/SD bus connects cards to the controller.\nThe current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time\nand a stack of MMC4.1 or previous.\n22.2\nSDIO bus topology\nCommunication over the bus is based on command and data transfers.\nThe basic transaction on the MultiMediaCard/SD/SD I/O bus is the command/response\ntransaction. These types of bus transaction transfer their information directly within the\ncommand or response structure. In addition, some operations have a data token.\nData transfers to/from SD/SDIO memory cards are done in data blocks. Data transfers\nto/from MMC are done data blocks or streams. Data transfers to/from the CE-ATA Devices\nare done in data blocks.\nFigure 206. SDIO “no response” and “no data” operations\nSDIO_CMD\nFrom host to card(s) From host to card From card to host\nCommand Command Response\nSDIO_D\nOperation (no response)\nOperation (no data)\nai14734\nFigure 207. SDIO (multiple) block read operation\nFrom host to card From card to host\ndata from card to host\nSDIO_CMD\nSDIO_D\nCommand\nResponse\nData block crc\nStop command\nstops data transfer\nCommand\nData block crc\nResponse\nData block crc\nBlock read operation\nMultiple block read operation\nData stop operation\nai14735\n542/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nFigure 208. SDIO (multiple) block write operation\nFrom host to card\nFrom card to host\nData from host to card\nCommand\nSDIO_CMD\nSDIO_D\nResponse\nBusy\nOptional cards Busy.\nNeeded for CE-ATA\nData block crc\nBusy\nBlock write operation\nStop command\nstops data transfer\nCommand Response\nData block crc Busy\nData stop operation\nMultiple block write operation\nai14737\nNote:\nThe SDIO will not send any data as long as the Busy signal is asserted (SDIO_D0 pulled\nlow).\nFigure 209. SDIO sequential read operation\nFrom host to\ncard(s)\nFrom card to host\nData from card to host\nSDIO_CMD\nCommand\nResponse\nStop command\nstops data transfer\nCommand\nSDIO_D\nResponse\nData stream\nData transfer operation\nData stop operation\nai14738\nFigure 210. SDIO sequential write operation\nFrom host to\ncard(s)\nFrom card to host\nData from host to card\nSDIO_CMD\nSDIO_D\nCommand\nResponse\nStop command\nstops data transfer\nCommand\nResponse\nData stream\nData transfer operation\nData stop operation\nai14739\nDoc ID 13902 Rev 14\n543/1096 Secure digital input/output interface (SDIO)\n22.3\nRM0008\nSDIO functional description\nThe SDIO consists of two parts:\n● The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card\nsuch as the clock generation unit, command and data transfer.\n● The AHB interface accesses the SDIO adapter registers, and generates interrupt and\nDMA request signals.\nFigure 211. SDIO block diagram\nSDIO\nSDIO_CK\nInterrupts and\nDMA request\nSDIO_CMD\nAHB SDIO\ninterface adapter\nSDIO_D[7:0]\nAHB bus\nHCLK/2\nSDIOCLK\nai14740\nBy default SDIO_D0 is used for data transfer. After initialization, the host can change the\ndatabus width.\nIf a MultiMediaCard is connected to the bus, SDIO_D0, SDIO_D[3:0] or SDIO_D[7:0] can be\nused for data transfer. MMC V3.31 or previous, supports only 1 bit of data so only SDIO_D0\ncan be used.\nIf an SD or SD I/O card is connected to the bus, data transfer can be configured by the host\nto use SDIO_D0 or SDIO_D[3:0]. All data lines are operating in push-pull mode.\nSDIO_CMD has two operational modes:\n● Open-drain for initialization (only for MMCV3.31 or previous)\n● Push-pull for command transfer (SD/SD I/O card MMC4.2 use push-pull drivers also for\ninitialization)\nSDIO_CK is the clock to the card: one bit is transferred on both command and data lines\nwith each clock cycle. The clock frequency can vary between 0 MHz and 20 MHz (for a\nMultiMediaCard V3.31), between 0 and 48 MHz for a MultiMediaCard V4.0/4.2, or between\n0 and 25 MHz (for an SD/SD I/O card).\nThe SDIO uses two clock signals:\n● SDIO adapter clock (SDIOCLK = HCLK)\n● AHB bus clock (HCLK/2)\nPCLK2 and SDIO_CK clock frequencies must respect the following condition:\nFrequenc ( PCLK2 ) = 3 ⁄ 8 × Frequency ( SDIO_CK )\nThe signals shown in Table 137 are used on the MultiMediaCard/SD/SD I/O card bus.\n544/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nTable 137. SDIO I/O definitions\nPin\n22.3.1\nDirection\nDescription\nSDIO_CK Output MultiMediaCard/SD/SDIO card clock. This pin is the clock from\nhost to card.\nSDIO_CMD Bidirectional MultiMediaCard/SD/SDIO card command. This pin is the\nbidirectional command/response signal.\nSDIO_D[7:0] Bidirectional MultiMediaCard/SD/SDIO card data. These pins are the\nbidirectional databus.\nSDIO adapter\nFigure 212 shows a simplified block diagram of an SDIO adapter.\nFigure 212. SDIO adapter\nSDIO adapter\nCommand\npath\nAdapter\nregisters\nTo AHB\ninterface\nData path\nFIFO\nHCLK/2\nSDIO_CK\nSDIO_CMD\nControl unit\nSDIO_D[7:0]\nSDIOCLK\nai14740\nThe SDIO adapter is a multimedia/secure digital memory card bus master that provides an\ninterface to a multimedia card stack or to a secure digital memory card. It consists of five\nsubunits:\nNote:\n● Adapter register block\n● Control unit\n● Command path\n● Data path\n● Data FIFO\nThe adapter registers and FIFO use the AHB bus clock domain (HCLK/2). The control unit,\ncommand path and data path use the SDIO adapter clock domain (SDIOCLK).\nAdapter register block\nThe adapter register block contains all system registers. This block also generates the\nsignals that clear the static flags in the multimedia card. The clear signals are generated\nwhen 1 is written into the corresponding bit location in the SDIO Clear register.\nDoc ID 13902 Rev 14\n545/1096 Secure digital input/output interface (SDIO)\nRM0008\nControl unit\nThe control unit contains the power management functions and the clock divider for the\nmemory card clock.\nThere are three power phases:\n● power-off\n● power-up\n● power-on\nFigure 213. Control unit\nControl unit\nPower management\nClock\nmanagement\nAdapter\nregisters\nSDIO_CK\nTo command and data path\nai14804\nThe control unit is illustrated in Figure 213. It consists of a power management subunit and\na clock management subunit.\nThe power management subunit disables the card bus output signals during the power-off\nand power-up phases.\nThe clock management subunit generates and controls the SDIO_CK signal. The SDIO_CK\noutput can use either the clock divide or the clock bypass mode. The clock output is inactive:\n● after reset\n● during the power-off or power-up phases\n● if the power saving mode is enabled and the card bus is in the Idle state (eight clock\nperiods after both the command and data path subunits enter the Idle phase)\nCommand path\nThe command path unit sends commands to and receives responses from the cards.\n546/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nFigure 214. SDIO adapter command path\nTo control unit\nStatus\nflag\nControl\nlogic\nCommand\ntimer\nAdapter registers\nSDIO_CMDin\nCMD\nArgument\nCRC\nCMD\nTo AHB interface\nSDIO_CMDout\nShift\nregister\nResponse\nregisters\nai14805\n●\nCommand path state machine (CPSM)\n–\nWhen the command register is written to and the enable bit is set, command\ntransfer starts. When the command has been sent, the command path state\nmachine (CPSM) sets the status flags and enters the Idle state if a response is not\nrequired. If a response is required, it waits for the response (see Figure 215 on\npage 548). When the response is received, the received CRC code and the\ninternally generated code are compared, and the appropriate status flags are set.\nDoc ID 13902 Rev 14\n547/1096 Secure digital input/output interface (SDIO)\nRM0008\nFigure 215. Command path state machine (CPSM)\nOn reset\nCPSM Enabled and\npending command\nCE-ATA Command\nCompletion signal\nreceived or\nCPSM disabled or\nCommand CRC failed\nIdle\nWait_CPL\nResponse received or\ndisabled or command\nCRC failed\nCPSM\ndisabled\nResponse Received in CE-ATA\nmode and no interrupt and\nwait for CE-ATA Command\nCompletion signal enabled\nPend\nEnabled and\ncommand start\nLast Data\nCPSM disabled or\nno response\nCPSM Disabled or\ncommand timeout\nReceive\nResponse\nstarted\nSend\nWait for response\nWait\nResponse Received in CE-ATA mode and\nno interrupt and wait for CE-ATA\nCommand Completion signal disabled\nai14806b\nWhen the Wait state is entered, the command timer starts running. If the timeout is reached\nbefore the CPSM moves to the Receive state, the timeout flag is set and the Idle state is\nentered.\nNote:\nThe command timeout has a fixed value of 64 SDIO_CK clock periods.\nIf the interrupt bit is set in the command register, the timer is disabled and the CPSM waits\nfor an interrupt request from one of the cards. If a pending bit is set in the command register,\nthe CPSM enters the Pend state, and waits for a CmdPend signal from the data path\nsubunit. When CmdPend is detected, the CPSM moves to the Send state. This enables the\ndata counter to trigger the stop command transmission.\nNote:\n548/1096\nThe CPSM remains in the Idle state for at least eight SDIO_CK periods to meet the N CC and\nN RC timing constraints. N CC is the minimum delay between two host commands, and N RC is\nthe minimum delay between the host command and the card response.\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nFigure 216. SDIO command transfer\nat least 8 SDIO_CK cycles\nCommand\nSDIO_CK\nCommand\nResponse\nState Idle Send Wait Receive Idle Send\nSDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives\nai14707\n●\nCommand format\n–\nCommand: a command is a token that starts an operation. Command are sent\nfrom the host either to a single card (addressed command) or to all connected\ncards (broadcast command are available for MMC V3.31 or previous). Commands\nare transferred serially on the CMD line. All commands have a fixed length of 48\nbits. The general format for a command token for MultiMediaCards, SD-Memory\ncards and SDIO-Cards is shown in Table 138. CE-ATA commands are an\nextension of MMC commands V4.2, and so have the same format.\nThe command path operates in a half-duplex mode, so that commands and\nresponses can either be sent or received. If the CPSM is not in the Send state, the\nSDIO_CMD output is in the Hi-Z state, as shown in Figure 216 on page 549. Data\non SDIO_CMD are synchronous with the rising edge of SDIO_CK. Table shows\nthe command format.\nTable 138. Command format\nBit position\nWidth\nValue\nDescription\n47 1 0 Start bit\n46 1 1 Transmission bit\n[45:40] 6 - Command index\n[39:8] 32 - Argument\n[7:1] 7 - CRC7\n0 1 1 End bit\n–\nResponse: a response is a token that is sent from an addressed card (or\nsynchronously from all connected cards for MMC V3.31 or previous), to the host\nas an answer to a previously received command. Responses are transferred\nserially on the CMD line.\nThe SDIO supports two response types. Both use CRC error checking:\nNote:\n● 48 bit short response\n● 136 bit long response\nIf the response does not contain a CRC (CMD1 response), the device driver must ignore the\nCRC failed status.\nDoc ID 13902 Rev 14\n549/1096 Secure digital input/output interface (SDIO)\nRM0008\nTable 139. Short response format\nBit position\nWidth\nValue\nDescription\n47 1 0 Start bit\n46 1 0 Transmission bit\n[45:40] 6 - Command index\n[39:8] 32 - Argument\n[7:1] 7 - CRC7(or 1111111)\n0 1 1 End bit\nTable 140. Long response format\nBit position\nWidth\nValue\nDescription\n135 1 0 Start bit\n134 1 0 Transmission bit\n[133:128] 6 111111 Reserved\n[127:1] 127 - CID or CSD (including internal CRC7)\n0 1 1 End bit\nThe command register contains the command index (six bits sent to a card) and the\ncommand type. These determine whether the command requires a response, and whether\nthe response is 48 or 136 bits long (see Section 22.9.4 on page 584). The command path\nimplements the status flags shown in Table 141:\nTable 141. Command path status flags\nFlag Description\nCMDREND Set if response CRC is OK.\nCCRCFAIL Set if response CRC fails.\nCMDSENT Set when command (that does not require response) is sent\nCTIMEOUT Response timeout.\nCMDACT Command transfer in progress.\nThe CRC generator calculates the CRC checksum for all bits before the CRC code. This\nincludes the start bit, transmitter bit, command index, and command argument (or card\nstatus). The CRC checksum is calculated for the first 120 bits of CID or CSD for the long\nresponse format. Note that the start bit, transmitter bit and the six reserved bits are not used\nin the CRC calculation.\nThe CRC checksum is a 7-bit value:\nCRC[6:0] = Remainder [(M(x) * x 7 ) / G(x)]\nG(x) = x 7 + x 3 + 1\nM(x) = (start bit) * x 39 + ... + (last bit before CRC) * x 0 , or\nM(x) = (start bit) * x 119 + ... + (last bit before CRC) * x 0\n550/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nData path\nThe data path subunit transfers data to and from cards. Figure 217 shows a block diagram\nof the data path.\nFigure 217. Data path\nData path\nTo control unit\nStatus\nflag\nControl\nlogic\nData\ntimer\nData FIFO\nSDIO_Din[7:0]\nTransmit\nCRC\nSDIO_Dout[7:0]\nShift\nregister\nReceive\nai14808\nThe card databus width can be programmed using the clock control register. If the 4-bit wide\nbus mode is enabled, data is transferred at four bits per clock cycle over all four data signals\n(SDIO_D[3:0]). If the 8-bit wide bus mode is enabled, data is transferred at eight bits per\nclock cycle over all eight data signals (SDIO_D[7:0]). If the wide bus mode is not enabled,\nonly one bit per clock cycle is transferred over SDIO_D0.\nDepending on the transfer direction (send or receive), the data path state machine (DPSM)\nmoves to the Wait_S or Wait_R state when it is enabled:\n● Send: the DPSM moves to the Wait_S state. If there is data in the transmit FIFO, the\nDPSM moves to the Send state, and the data path subunit starts sending data to a\ncard.\n● Receive: the DPSM moves to the Wait_R state and waits for a start bit. When it\nreceives a start bit, the DPSM moves to the Receive state, and the data path subunit\nstarts receiving data from a card.\nData path state machine (DPSM)\nThe DPSM operates at SDIO_CK frequency. Data on the card bus signals is synchronous to\nthe rising edge of SDIO_CK. The DPSM has six states, as shown in Figure 218: Data path\nstate machine (DPSM).\nDoc ID 13902 Rev 14\n551/1096 Secure digital input/output interface (SDIO)\nRM0008\nFigure 218. Data path state machine (DPSM)\nOn reset\nDPSM disabled\nRead Wait\nDPSM enabled and\nRead Wait Started\nand SD I/O mode enabled\nDisabled or FIFO underrun or\nend of data or CRC fail\nIdle\nDisabled or CRC fail\nor timeout\nEnable and not send\nReadWait Stop\nDisabled or\nend of data\nDisabled or\nRx FIFO empty or timeout or\nstart bit error\nBusy\nNot busy\nEnable and send\nWait_R\nData received and\nRead Wait Started and\nSD I/O mode enabled\nEnd of packet\nWait_S\nEnd of packet or\nend of data or\nFIFO overrun\nDisabled or CRC fail\nStart bit\nData ready\nSend\nReceive\nai14809b\n● Idle: the data path is inactive, and the SDIO_D[7:0] outputs are in Hi-Z. When the data\ncontrol register is written and the enable bit is set, the DPSM loads the data counter\nwith a new value and, depending on the data direction bit, moves to either the Wait_S\nor the Wait_R state.\n● Wait_R: if the data counter equals zero, the DPSM moves to the Idle state when the\nreceive FIFO is empty. If the data counter is not zero, the DPSM waits for a start bit on\nSDIO_D. The DPSM moves to the Receive state if it receives a start bit before a\ntimeout, and loads the data block counter. If it reaches a timeout before it detects a\nstart bit, or a start bit error occurs, it moves to the Idle state and sets the timeout status\nflag.\n● Receive: serial data received from a card is packed in bytes and written to the data\nFIFO. Depending on the transfer mode bit in the data control register, the data transfer\nmode can be either block or stream:\n– In block mode, when the data block counter reaches zero, the DPSM waits until it\nreceives the CRC code. If the received code matches the internally generated\nCRC code, the DPSM moves to the Wait_R state. If not, the CRC fail status flag is\nset and the DPSM moves to the Idle state.\n– In stream mode, the DPSM receives data while the data counter is not zero. When\nthe counter is zero, the remaining data in the shift register is written to the data\nFIFO, and the DPSM moves to the Wait_R state.\nIf a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the Idle\nstate:\n●\n552/1096\nWait_S: the DPSM moves to the Idle state if the data counter is zero. If not, it waits until\nthe data FIFO empty flag is deasserted, and moves to the Send state.\nDoc ID 13902 Rev 14 RM0008\nNote:\nSecure digital input/output interface (SDIO)\nThe DPSM remains in the Wait_S state for at least two clock periods to meet the N WR timing\nrequirements, where N WR is the number of clock cycles between the reception of the card\nresponse and the start of the data transfer from the host.\n●\nSend: the DPSM starts sending data to a card. Depending on the transfer mode bit in\nthe data control register, the data transfer mode can be either block or stream:\n– In block mode, when the data block counter reaches zero, the DPSM sends an\ninternally generated CRC code and end bit, and moves to the Busy state.\n– In stream mode, the DPSM sends data to a card while the enable bit is high and\nthe data counter is not zero. It then moves to the Idle state.\nIf a FIFO underrun error occurs, the DPSM sets the FIFO error flag and moves to the\nIdle state.\n●\nBusy: the DPSM waits for the CRC status flag:\n– If it does not receive a positive CRC status, it moves to the Idle state and sets the\nCRC fail status flag.\n– If it receives a positive CRC status, it moves to the Wait_S state if SDIO_D0 is not\nlow (the card is not busy).\nIf a timeout occurs while the DPSM is in the Busy state, it sets the data timeout flag and\nmoves to the Idle state.\nThe data timer is enabled when the DPSM is in the Wait_R or Busy state, and\ngenerates the data timeout error:\n●\n– When transmitting data, the timeout occurs if the DPSM stays in the Busy state for\nlonger than the programmed timeout period\n– When receiving data, the timeout occurs if the end of the data is not true, and if the\nDPSM stays in the Wait_R state for longer than the programmed timeout period.\nData: data can be transferred from the card to the host or vice versa. Data is\ntransferred via the data lines . They are stored in a FIFO of 32 words , each word is 32\nbits wide.\nTable 142. Data token format\nDescription\nStart bit\nData\nCRC16\nEnd bit\nBlock Data 0 - yes 1\nStream Data 0 - no 1\nData FIFO\nThe data FIFO (first-in-first-out) subunit is a data buffer with a transmit and receive unit.\nThe FIFO contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic.\nBecause the data FIFO operates in the AHB clock domain (HCLK/2), all signals from the\nsubunits in the SDIO clock domain (SDIOCLK) are resynchronized.\nDoc ID 13902 Rev 14\n553/1096 Secure digital input/output interface (SDIO)\nRM0008\nDepending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or\nreceive enabled. TXACT and RXACT are driven by the data path subunit and are mutually\nexclusive:\n●\n– The transmit FIFO refers to the transmit logic and data buffer when TXACT is\nasserted\n– The receive FIFO refers to the receive logic and data buffer when RXACT is\nasserted\nTransmit FIFO:\nData can be written to the transmit FIFO through the AHB interface when the SDIO is\nenabled for transmission.\nThe transmit FIFO is accessible via 32 sequential addresses. The transmit FIFO\ncontains a data output register that holds the data word pointed to by the read pointer.\nWhen the data path subunit has loaded its shift register, it increments the read pointer\nand drives new data out.\nIf the transmit FIFO is disabled, all status flags are deasserted. The data path subunit\nasserts TXACT when it transmits data.\nTable 143. Transmit FIFO status flags\nFlag\nDescription\nTXFIFOF Set to high when all 32 transmit FIFO words contain valid data.\nTXFIFOE Set to high when the transmit FIFO does not contain valid data.\nTXFIFOHE Set to high when 8 or more transmit FIFO words are empty. This flag can be used\nas a DMA request.\nTXDAVL Set to high when the transmit FIFO contains valid data. This flag is the inverse of\nthe TXFIFOE flag.\nTXUNDERR Set to high when an underrun error occurs. This flag is cleared by writing to the\nSDIO Clear register.\n●\nReceive FIFO\nWhen the data path subunit receives a word of data, it drives the data on the write\ndatabus. The write pointer is incremented after the write operation completes. On the\nread side, the contents of the FIFO word pointed to by the current value of the read\npointer is driven onto the read databus. If the receive FIFO is disabled, all status flags\nare deasserted, and the read and write pointers are reset. The data path subunit\nasserts RXACT when it receives data. Table 144 lists the receive FIFO status flags.\nThe receive FIFO is accessible via 32 sequential addresses.\n554/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nTable 144. Receive FIFO status flags\nFlag\n22.3.2\nDescription\nRXFIFOF Set to high when all 32 receive FIFO words contain valid data\nRXFIFOE Set to high when the receive FIFO does not contain valid data.\nRXFIFOHF Set to high when 8 or more receive FIFO words contain valid data. This flag can be\nused as a DMA request.\nRXDAVL Set to high when the receive FIFO is not empty. This flag is the inverse of the\nRXFIFOE flag.\nRXOVERR Set to high when an overrun error occurs. This flag is cleared by writing to the SDIO\nClear register.\nSDIO AHB interface\nThe AHB interface generates the interrupt and DMA requests, and accesses the SDIO\nadapter registers and the data FIFO. It consists of a data path, register decoder, and\ninterrupt/DMA logic.\nSDIO interrupts\nThe interrupt logic generates an interrupt request signal that is asserted when at least one\nof the selected status flags is high. A mask register is provided to allow selection of the\nconditions that will generate an interrupt. A status flag generates the interrupt request if a\ncorresponding mask flag is set.\nSDIO/DMA interface: procedure for data transfers between the SDIO and\nmemory\nIn the example shown, the transfer is from the SDIO host controller to an MMC (512 bytes\nusing CMD24 (WRITE_BLOCK). The SDIO FIFO is filled by data stored in a memory using\nthe DMA controller.\n1. Do the card identification process\n2. Increase the SDIO_CK frequency\n3. Select the card by sending CMD7\n4. Configure the DMA2 as follows:\na) Enable DMA2 controller and clear any pending interrupts\nb) Program the DMA2_Channel4 source address register with the memory location’s\nbase address and DMA2_Channel4 destination address register with the\nSDIO_FIFO register address\nc) Program DMA2_Channel4 control register (memory increment, not peripheral\nincrement, peripheral and source width is word size)\nd) Enable DMA2_Channel4\nDoc ID 13902 Rev 14\n555/1096 Secure digital input/output interface (SDIO)\n5.\n6.\nRM0008\nSend CMD24 (WRITE_BLOCK) as follows:\na) Program the SDIO data length register (SDIO data timer register should be\nalready programmed before the card identification process)\nb) Program the SDIO argument register with the address location of the card where\ndata is to be transferred\nc) Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK);\nWaitResp with ‘1’ (SDIO card host waits for a response); CPSMEN with ‘1’ (SDIO\ncard host enabled to send a command). Other fields are at their reset value.\nd) Wait for SDIO_STA[6] = CMDREND interrupt, then program the SDIO data control\nregister: DTEN with ‘1’ (SDIO card host enabled to send data); DTDIR with ‘0’\n(from controller to card); DTMODE with ‘0’ (block data transfer); DMAEN with ‘1’\n(DMA enabled); DBLOCKSIZE with 0x9 (512 bytes). Other fields are don’t care.\ne) Wait for SDIO_STA[10] = DBCKEND\nCheck that no channels are still enabled by polling the DMA Enabled Channel Status\nregister.\n22.4 Card functional description\n22.4.1 Card identification mode\nWhile in card identification mode the host resets all cards, validates the operation voltage\nrange, identifies cards and sets a relative card address (RCA) for each card on the bus. All\ndata communications in the card identification mode use the command line (CMD) only.\n22.4.2\nCard reset\nThe GO_IDLE_STATE command (CMD0) is the software reset command and it puts the\nMultiMediaCard and SD memory in the Idle state. The IO_RW_DIRECT command (CMD52)\nresets the SD I/O card. After power-up or CMD0, all cards output bus drivers are in the high-\nimpedance state and the cards are initialized with a default relative card address\n(RCA=0x0001) and with a default driver stage register setting (lowest speed, highest driving\ncurrent capability).\n22.4.3\nOperating voltage range validation\nAll cards can communicate with the SDIO card host using any operating voltage within the\nspecification range. The supported minimum and maximum V DD values are defined in the\noperation conditions register (OCR) on the card.\nCards that store the card identification number (CID) and card specific data (CSD) in the\npayload memory are able to communicate this information only under data-transfer V DD\nconditions. When the SDIO card host module and the card have incompatible V DD ranges,\nthe card is not able to complete the identification cycle and cannot send CSD data. For this\npurpose, the special commands, SEND_OP_COND (CMD1), SD_APP_OP_COND (ACMD41\nfor SD Memory), and IO_SEND_OP_COND (CMD5 for SD I/O), are designed to provide a\nmechanism to identify and reject cards that do not match the V DD range desired by the\nSDIO card host. The SDIO card host sends the required V DD voltage window as the\noperand of these commands. Cards that cannot perform data transfer in the specified range\ndisconnect from the bus and go to the inactive state.\n556/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nBy using these commands without including the voltage range as the operand, the SDIO\ncard host can query each card and determine the common voltage range before placing out-\nof-range cards in the inactive state. This query is used when the SDIO card host is able to\nselect a common voltage range or when the user requires notification that cards are not\nusable.\n22.4.4\nCard identification process\nThe card identification process differs for MultiMediaCards and SD cards. For\nMultiMediaCard cards, the identification process starts at clock rate F od . The SDIO_CMD\nline output drivers are open-drain and allow parallel card operation during this process. The\nregistration process is accomplished as follows:\n1. The bus is activated.\n2. The SDIO card host broadcasts SEND_OP_COND (CMD1) to receive operation\nconditions.\n3. The response is the wired AND operation of the operation condition registers from all\ncards.\n4. Incompatible cards are placed in the inactive state.\n5. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. The active cards simultaneously send their CID numbers serially. Cards with outgoing\nCID bits that do not match the bits on the command line stop transmitting and must wait\nfor the next identification cycle. One card successfully transmits a full CID to the SDIO\ncard host and enters the Identification state.\n7. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to that card. This new\naddress is called the relative card address (RCA); it is shorter than the CID and\naddresses the card. The assigned card changes to the Standby state, it does not react\nto further identification cycles, and its output switches from open-drain to push-pull.\n8. The SDIO card host repeats steps 5 through 7 until it receives a timeout condition.\nFor the SD card, the identification process starts at clock rate F od , and the SDIO_CMD line\noutput drives are push-pull drivers instead of open-drain. The registration process is\naccomplished as follows:\n1. The bus is activated.\n2. The SDIO card host broadcasts SD_APP_OP_COND (ACMD41).\n3. The cards respond with the contents of their operation condition registers.\n4. The incompatible cards are placed in the inactive state.\n5. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards.\n6. The cards send back their unique card identification numbers (CIDs) and enter the\nIdentification state.\n7. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an\naddress. This new address is called the relative card address (RCA); it is shorter than\nthe CID and addresses the card. The assigned card changes to the Standby state. The\nSDIO card host can reissue this command to change the RCA. The RCA of the card is\nthe last assigned value.\n8. The SDIO card host repeats steps 5 through 7 with all active cards.\nFor the SD I/O card, the registration process is accomplished as follows:\nDoc ID 13902 Rev 14\n557/1096 Secure digital input/output interface (SDIO)\n22.4.5\nRM0008\n1. The bus is activated.\n2. The SDIO card host sends IO_SEND_OP_COND (CMD5).\n3. The cards respond with the contents of their operation condition registers.\n4. The incompatible cards are set to the inactive state.\n5. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an\naddress. This new address is called the relative card address (RCA); it is shorter than\nthe CID and addresses the card. The assigned card changes to the Standby state. The\nSDIO card host can reissue this command to change the RCA. The RCA of the card is\nthe last assigned value.\nBlock write\nDuring block write (CMD24 - 27) one or more blocks of data are transferred from the host to\nthe card with a CRC appended to the end of each block by the host. A card supporting block\nwrite is always able to accept a block of data defined by WRITE_BL_LEN. If the CRC fails,\nthe card indicates the failure on the SDIO_D line and the transferred data are discarded and\nnot written, and all further transmitted blocks (in multiple block write mode) are ignored.\nIf the host uses partial blocks whose accumulated length is not block aligned and, block\nmisalignment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card\nwill detect the block misalignment error before the beginning of the first misaligned block.\n(ADDRESS_ERROR error bit is set in the status register). The write operation will also be\naborted if the host tries to write over a write-protected area. In this case, however, the card\nwill set the WP_VIOLATION bit.\nProgramming of the CID and CSD registers does not require a previous block length setting.\nThe transferred data is also CRC protected. If a part of the CSD or CID register is stored in\nROM, then this unchangeable part must match the corresponding part of the receive buffer.\nIf this match fails, then the card reports an error and does not change any register contents.\nSome cards may require long and unpredictable times to write a block of data. After\nreceiving a block of data and completing the CRC check, the card begins writing and holds\nthe SDIO_D line low if its write buffer is full and unable to accept new data from a new\nWRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS\ncommand (CMD13) at any time, and the card will respond with its status. The\nREADY_FOR_DATA status bit indicates whether the card can accept new data or whether\nthe write process is still in progress. The host may deselect the card by issuing CMD7 (to\nselect a different card), which will place the card in the Disconnect state and release the\nSDIO_D line(s) without interrupting the write operation. When reselecting the card, it will\nreactivate busy indication by pulling SDIO_D to low if programming is still in progress and\nthe write buffer is unavailable.\n22.4.6\nBlock read\nIn Block read mode the basic unit of data transfer is a block whose maximum size is defined\nin the CSD (READ_BL_LEN). If READ_BL_PARTIAL is set, smaller blocks whose start and\nend addresses are entirely contained within one physical block (as defined by\nREAD_BL_LEN) may also be transmitted. A CRC is appended to the end of each block,\nensuring data transfer integrity. CMD17 (READ_SINGLE_BLOCK) initiates a block read and\nafter completing the transfer, the card returns to the Transfer state.\nCMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks.\n558/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nThe host can abort reading at any time, within a multiple block operation, regardless of its\ntype. Transaction abort is done by sending the stop transmission command.\nIf the card detects an error (for example, out of range, address misalignment or internal\nerror) during a multiple block read operation (both types) it stops the data transmission and\nremains in the data state. The host must than abort the operation by sending the stop\ntransmission command. The read error is reported in the response to the stop transmission\ncommand.\nIf the host sends a stop transmission command after the card transmits the last block of a\nmultiple block operation with a predefined number of blocks, it is responded to as an illegal\ncommand, since the card is no longer in the data state. If the host uses partial blocks whose\naccumulated length is not block-aligned and block misalignment is not allowed, the card\ndetects a block misalignment error condition at the beginning of the first misaligned block\n(ADDRESS_ERROR error bit is set in the status register).\n22.4.7\nStream access, stream write and stream read (MultiMediaCard only)\nIn stream mode, data is transferred in bytes and no CRC is appended at the end of each\nblock.\nStream write (MultiMediaCard only)\nWRITE_DAT_UNTIL_STOP (CMD20) starts the data transfer from the SDIO card host to the\ncard, beginning at the specified address and continuing until the SDIO card host issues a\nstop command. When partial blocks are allowed (CSD parameter WRITE_BL_PARTIAL is\nset), the data stream can start and stop at any address within the card address space,\notherwise it can only start and stop at block boundaries. Because the amount of data to be\ntransferred is not determined in advance, a CRC cannot be used. When the end of the\nmemory range is reached while sending data and no stop command is sent by the SD card\nhost, any additional transferred data are discarded.\nThe maximum clock frequency for a stream write operation is given by the following\nequation fields of the card-specific data register:\n8 × 2 writebllen ) ( – NSAC ) )\nMaximumspeed = MIN ( TRANSPEED , ( ------------------------------------------------------------------------\nTAAC × R2WFACTOR\n● Maximumspeed = maximum write frequency\n● TRANSPEED = maximum data transfer rate\n● writebllen = maximum write data block length\n● NSAC = data read access time 2 in CLK cycles\n● TAAC = data read access time 1\n● R2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card may not be able to process the data\nand stop programming, set the OVERRUN error bit in the status register, and while ignoring\nall further data transfer, wait (in the receive data state) for a stop command. The write\noperation is also aborted if the host tries to write over a write-protected area. In this case,\nhowever, the card sets the WP_VIOLATION bit.\nDoc ID 13902 Rev 14\n559/1096 Secure digital input/output interface (SDIO)\nRM0008\nStream read (MultiMediaCard only)\nREAD_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer.\nThis command instructs the card to send its data, starting at a specified address, until the\nSDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an\nexecution delay due to the serial command transmission and the data transfer stops after\nthe end bit of the stop command. When the end of the memory range is reached while\nsending data and no stop command is sent by the SDIO card host, any subsequent data\nsent are considered undefined.\nThe maximum clock frequency for a stream read operation is given by the following equation\nand uses fields of the card specific data register.\n8 × 2 readbllen ) ( – NSAC ) )\nMaximumspeed = MIN ( TRANSPEED , ( -----------------------------------------------------------------------\nTAAC × R2WFACTOR\n● Maximumspeed = maximum read frequency\n● TRANSPEED = maximum data transfer rate\n● readbllen = maximum read data block length\n● writebllen = maximum write data block length\n● NSAC = data read access time 2 in CLK cycles\n● TAAC = data read access time 1\n● R2WFACTOR = write speed factor\nIf the host attempts to use a higher frequency, the card is not able to sustain data transfer. If\nthis happens, the card sets the UNDERRUN error bit in the status register, aborts the\ntransmission and waits in the data state for a stop command.\n22.4.8\nErase: group erase and sector erase\nThe erasable unit of the MultiMediaCard is the erase group. The erase group is measured in\nwrite blocks, which are the basic writable units of the card. The size of the erase group is a\ncard-specific parameter and defined in the CSD.\nThe host can erase a contiguous range of Erase Groups. Starting the erase process is a\nthree-step sequence.\nFirst the host defines the start address of the range using the ERASE_GROUP_START\n(CMD35) command, next it defines the last address of the range using the\nERASE_GROUP_END (CMD36) command and, finally, it starts the erase process by issuing\nthe ERASE (CMD38) command. The address field in the erase commands is an Erase\nGroup address in byte units. The card ignores all LSBs below the Erase Group size,\neffectively rounding the address down to the Erase Group boundary.\nIf an erase command is received out of sequence, the card sets the ERASE_SEQ_ERROR\nbit in the status register and resets the whole sequence.\nIf an out-of-sequence (neither of the erase commands, except SEND_STATUS) command\nreceived, the card sets the ERASE_RESET status bit in the status register, resets the erase\nsequence and executes the last command.\nIf the erase range includes write protected blocks, they are left intact and only nonprotected\nblocks are erased. The WP_ERASE_SKIP status bit in the status register is set.\n560/1096\nDoc ID 13902 Rev 14 RM0008\nSecure digital input/output interface (SDIO)\nThe card indicates that an erase is in progress by holding SDIO_D low. The actual erase\ntime may be quite long, and the host may issue CMD7 to deselect the card.\n22.4.9\nWide bus selection or deselection\nWide bus (4-bit bus width) operation mode is selected or deselected using\nSET_BUS_WIDTH (ACMD6). The default bus width after power-up or GO_IDLE_STATE\n(CMD0) is 1 bit. SET_BUS_WIDTH (ACMD6) is only v " ;
	 nfo:tableOfContents "Contents List of tables List of figures 1 Overview of the manual 2 Documentation conventions 2.1 List of abbreviations for registers 2.2 Glossary 2.3 Peripheral availability 3 Memory and bus architecture 3.1 System architecture ICode bus DCode bus System bus DMA bus BusMatrix AHB/APB bridges (APB) 3.2 Memory organization 3.3 Memory map 3.3.1 Embedded SRAM 3.3.2 Bit banding 3.3.3 Embedded Flash memory Reading the Flash memory Programming and erasing the Flash memory Flash access control register (FLASH_ACR) 3.4 Boot configuration Embedded boot loader 4 CRC calculation unit 4.1 CRC introduction 4.2 CRC main features 4.3 CRC functional description 4.4 CRC registers 4.4.1 Data register (CRC_DR) 4.4.2 Independent data register (CRC_IDR) 4.4.3 Control register (CRC_CR) 4.4.4 CRC register map 5 Power control (PWR) 5.1 Power supplies 5.1.1 Independent A/D and D/A converter supply and reference voltage On 100-pin and 144-pin packages On 64-pin packages and packages with less pins 5.1.2 Battery backup domain 5.1.3 Voltage regulator 5.2 Power supply supervisor 5.2.1 Power on reset (POR)/power down reset (PDR) 5.2.2 Programmable voltage detector (PVD) 5.3 Low-power modes 5.3.1 Slowing down system clocks 5.3.2 Peripheral clock gating 5.3.3 Sleep mode Entering Sleep mode Exiting Sleep mode 5.3.4 Stop mode Entering Stop mode 5.3.5 Standby mode Entering Standby mode Exiting Standby mode I/O states in Standby mode Debug mode 5.3.6 Auto-wakeup (AWU) from low-power mode 5.4 Power control registers 5.4.1 Power control register (PWR_CR) 5.4.2 Power control/status register (PWR_CSR) 5.4.3 PWR register map 6 Backup registers (BKP) 6.1 BKP introduction 6.2 BKP main features 6.3 BKP functional description 6.3.1 Tamper detection 6.3.2 RTC calibration 6.4 BKP registers 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) 6.4.2 RTC clock calibration register (BKP_RTCCR) 6.4.3 Backup control register (BKP_CR) 6.4.4 Backup control/status register (BKP_CSR) 6.4.5 BKP register map 7 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.1 Reset 7.1.1 System reset Software reset Low-power management reset 7.1.2 Power reset 7.1.3 Backup domain reset 7.2 Clocks 7.2.1 HSE clock External source (HSE bypass) External crystal/ceramic resonator (HSE crystal) 7.2.2 HSI clock Calibration 7.2.3 PLL 7.2.4 LSE clock External source (LSE bypass) 7.2.5 LSI clock LSI calibration 7.2.6 System clock (SYSCLK) selection 7.2.7 Clock security system (CSS) 7.2.8 RTC clock 7.2.9 Watchdog clock 7.2.10 Clock-out capability 7.3 RCC registers 7.3.1 Clock control register (RCC_CR) 7.3.2 Clock configuration register (RCC_CFGR) 7.3.3 Clock interrupt register (RCC_CIR) 7.3.4 APB2 peripheral reset register (RCC_APB2RSTR) 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) 7.3.6 AHB peripheral clock enable register (RCC_AHBENR) 7.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) 7.3.9 Backup domain control register (RCC_BDCR) 7.3.10 Control/status register (RCC_CSR) 7.3.11 RCC register map 8 Connectivity line devices: reset and clock control (RCC) 8.1 Reset 8.1.1 System reset Software reset Low-power management reset 8.1.2 Power reset 8.1.3 Backup domain reset 8.2 Clocks 8.2.1 HSE clock External source (HSE bypass) External crystal/ceramic resonator (HSE crystal) 8.2.2 HSI clock Calibration 8.2.3 PLLs 8.2.4 LSE clock External source (LSE bypass) 8.2.5 LSI clock LSI calibration 8.2.6 System clock (SYSCLK) selection 8.2.7 Clock security system (CSS) 8.2.8 RTC clock 8.2.9 Watchdog clock 8.2.10 Clock-out capability 8.3 RCC registers 8.3.1 Clock control register (RCC_CR) 8.3.2 Clock configuration register (RCC_CFGR) 8.3.3 Clock interrupt register (RCC_CIR) 8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) 8.3.5 APB1 peripheral reset register (RCC_APB1RSTR) 8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) 8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) 8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) 8.3.9 Backup domain control register (RCC_BDCR) 8.3.10 Control/status register (RCC_CSR) 8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR) 8.3.12 Clock configuration register2 (RCC_CFGR2) 8.3.13 RCC register map 9 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1 GPIO functional description 9.1.1 General-purpose I/O (GPIO) 9.1.2 Atomic bit set or reset 9.1.3 External interrupt/wakeup lines 9.1.4 Alternate functions (AF) 9.1.5 Software remapping of I/O alternate functions 9.1.6 GPIO locking mechanism 9.1.7 Input configuration 9.1.8 Output configuration 9.1.9 Alternate function configuration 9.1.10 Analog configuration 9.1.11 GPIO configurations for device peripherals 9.2 GPIO registers 9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) 9.2.3 Port input data register (GPIOx_IDR) (x=A..G) 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) 9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G) 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) 9.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G) 9.3 Alternate function I/O and debug configuration (AFIO) 9.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 9.3.3 CAN1 alternate function remapping 9.3.4 CAN2 alternate function remapping 9.3.5 JTAG/SWD alternate function remapping 9.3.6 ADC alternate function remapping 9.3.7 Timer alternate function remapping 9.3.8 USART alternate function remapping 9.3.9 I2C1 alternate function remapping 9.3.10 SPI1 alternate function remapping 9.3.11 SPI3/I2S3 alternate function remapping 9.3.12 Ethernet alternate function remapping 9.4 AFIO registers 9.4.1 Event control register (AFIO_EVCR) 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Memory map and bit definitions for low-, medium- high- and XL-density devices: Memory map and bit definitions for connectivity line devices: 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) 9.4.4 External interrupt configuration register 2 (AFIO_EXTICR2) 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) 9.4.6 External interrupt configuration register 4 (AFIO_EXTICR4) 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) 9.5 GPIO and AFIO register maps 10 Interrupts and events 10.1 Nested vectored interrupt controller (NVIC) Features 10.1.1 SysTick calibration value register 10.1.2 Interrupt and exception vectors 10.2 External interrupt/event controller (EXTI) 10.2.1 Main features 10.2.2 Block diagram 10.2.3 Wakeup event management 10.2.4 Functional description Hardware interrupt selection Hardware event selection Software interrupt/event selection 10.2.5 External interrupt/event line mapping 10.3 EXTI registers 10.3.1 Interrupt mask register (EXTI_IMR) 10.3.2 Event mask register (EXTI_EMR) 10.3.3 Rising trigger selection register (EXTI_RTSR) 10.3.4 Falling trigger selection register (EXTI_FTSR) 10.3.5 Software interrupt event register (EXTI_SWIER) 10.3.6 Pending register (EXTI_PR) 10.3.7 EXTI register map 11 Analog-to-digital converter (ADC) 11.1 ADC introduction 11.2 ADC main features 11.3 ADC functional description 11.3.1 ADC on-off control 11.3.2 ADC clock 11.3.3 Channel selection Temperature sensor/VREFINT internal channels 11.3.4 Single conversion mode 11.3.5 Continuous conversion mode 11.3.6 Timing diagram 11.3.7 Analog watchdog 11.3.8 Scan mode 11.3.9 Injected channel management Triggered injection Auto-injection 11.3.10 Discontinuous mode Regular group Injected group 11.4 Calibration 11.5 Data alignment 11.6 Channel-by-channel programmable sample time 11.7 Conversion on external trigger 11.8 DMA request 11.9 Dual ADC mode 11.9.1 Injected simultaneous mode 11.9.2 Regular simultaneous mode 11.9.3 Fast interleaved mode 11.9.4 Slow interleaved mode 11.9.5 Alternate trigger mode 11.9.6 Independent mode 11.9.7 Combined regular/injected simultaneous mode 11.9.8 Combined regular simultaneous + alternate trigger mode 11.9.9 Combined injected simultaneous + interleaved 11.10 Temperature sensor Reading the temperature 11.11 ADC interrupts 11.12 ADC registers 11.12.1 ADC status register (ADC_SR) 11.12.2 ADC control register 1 (ADC_CR1) 11.12.3 ADC control register 2 (ADC_CR2) 11.12.4 ADC sample time register 1 (ADC_SMPR1) 11.12.5 ADC sample time register 2 (ADC_SMPR2) 11.12.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) 11.12.7 ADC watchdog high threshold register (ADC_HTR) 11.12.8 ADC watchdog low threshold register (ADC_LTR) 11.12.9 ADC regular sequence register 1 (ADC_SQR1) 11.12.10 ADC regular sequence register 2 (ADC_SQR2) 11.12.11 ADC regular sequence register 3 (ADC_SQR3) 11.12.12 ADC injected sequence register (ADC_JSQR) 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) 11.12.14 ADC regular data register (ADC_DR) 11.12.15 ADC register map 12 Digital-to-analog converter (DAC) 12.1 DAC introduction 12.2 DAC main features 12.3 DAC functional description 12.3.1 DAC channel enable 12.3.2 DAC output buffer enable 12.3.3 DAC data format 12.3.4 DAC conversion 12.3.5 DAC output voltage 12.3.6 DAC trigger selection 12.3.7 DMA request 12.3.8 Noise generation 12.3.9 Triangle-wave generation 12.4 Dual DAC channel conversion 12.4.1 Independent trigger without wave generation 12.4.2 Independent trigger with same LFSR generation 12.4.3 Independent trigger with different LFSR generation 12.4.4 Independent trigger with same triangle generation 12.4.5 Independent trigger with different triangle generation 12.4.6 Simultaneous software start 12.4.7 Simultaneous trigger without wave generation 12.4.8 Simultaneous trigger with same LFSR generation 12.4.9 Simultaneous trigger with different LFSR generation 12.4.10 Simultaneous trigger with same triangle generation 12.4.11 Simultaneous trigger with different triangle generation 12.5 DAC registers 12.5.1 DAC control register (DAC_CR) 12.5.2 DAC software trigger register (DAC_SWTRIGR) 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) 12.5.5 DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) 12.5.8 DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) 12.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) 12.5.12 DAC channel1 data output register (DAC_DOR1) 12.5.13 DAC channel2 data output register (DAC_DOR2) 12.5.14 DAC register map 13 Direct memory access controller (DMA) 13.1 DMA introduction 13.2 DMA main features 13.3 DMA functional description 13.3.1 DMA transactions 13.3.2 Arbiter 13.3.3 DMA channels Programmable data sizes Pointer incrementation Channel configuration procedure Circular mode Memory-to-memory mode 13.3.4 Programmable data width, data alignment and endians Addressing an AHB peripheral that does not support byte or halfword write operations 13.3.5 Error management 13.3.6 Interrupts 13.3.7 DMA request mapping DMA1 controller DMA2 controller 13.4 DMA registers 13.4.1 DMA interrupt status register (DMA_ISR) 13.4.2 DMA interrupt flag clear register (DMA_IFCR) 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) 13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7), where x = channel number) 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7), where x = channel number) 13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7), where x = channel number) 13.4.7 DMA register map 14 Advanced-control timers (TIM1&TIM8) 14.1 TIM1&TIM8 introduction 14.2 TIM1&TIM8 main features 14.3 TIM1&TIM8 functional description 14.3.1 Time-base unit Prescaler description 14.3.2 Counter modes Upcounting mode Downcounting mode Center-aligned mode (up/down counting) 14.3.3 Repetition counter 14.3.4 Clock selection Internal clock source (CK_INT) External clock source mode 1 External clock source mode 2 14.3.5 Capture/compare channels 14.3.6 Input capture mode 14.3.7 PWM input mode 14.3.8 Forced output mode 14.3.9 Output compare mode 14.3.10 PWM mode PWM edge-aligned mode PWM center-aligned mode 14.3.11 Complementary outputs and dead-time insertion Re-directing OCxREF to OCx or OCxN 14.3.12 Using the break function 14.3.13 Clearing the OCxREF signal on an external event 14.3.14 6-step PWM generation 14.3.15 One-pulse mode 14.3.16 Encoder interface mode 14.3.17 Timer input XOR function 14.3.18 Interfacing with Hall sensors 14.3.19 TIMx and external trigger synchronization Slave mode: Reset mode Slave mode: Gated mode Slave mode: Trigger mode Slave mode: external clock mode 2 + trigger mode 14.3.20 Timer synchronization 14.3.21 Debug mode 14.4 TIM1&TIM8 registers 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) 14.4.2 TIM1&TIM8 control register 2 (TIMx_CR2) 14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) 14.4.4 TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) 14.4.5 TIM1&TIM8 status register (TIMx_SR) 14.4.6 TIM1&TIM8 event generation register (TIMx_EGR) 14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Output compare mode: Input capture mode 14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) Output compare mode Input capture mode 14.4.9 TIM1&TIM8 capture/compare enable register (TIMx_CCER) 14.4.10 TIM1&TIM8 counter (TIMx_CNT) 14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) 14.4.12 TIM1&TIM8 auto-reload register (TIMx_ARR) 14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) 14.4.14 TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) 14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) 14.4.16 TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) 14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) 14.4.18 TIM1&TIM8 break and dead-time register (TIMx_BDTR) 14.4.19 TIM1&TIM8 DMA control register (TIMx_DCR) 14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Example of how to use the DMA burst feature 14.4.21 TIM1&TIM8 register map 15 General-purpose timers (TIM2 to TIM5) 15.1 TIM2 to TIM5 introduction 15.2 TIMx main features 15.3 TIMx functional description 15.3.1 Time-base unit Prescaler description 15.3.2 Counter modes Upcounting mode Downcounting mode Center-aligned mode (up/down counting) 15.3.3 Clock selection Internal clock source (CK_INT) External clock source mode 1 External clock source mode 2 15.3.4 Capture/compare channels 15.3.5 Input capture mode 15.3.6 PWM input mode 15.3.7 Forced output mode 15.3.8 Output compare mode 15.3.9 PWM mode PWM edge-aligned mode Downcounting configuration PWM center-aligned mode 15.3.10 One-pulse mode Particular case: OCx fast enable: 15.3.11 Clearing the OCxREF signal on an external event 15.3.12 Encoder interface mode 15.3.13 Timer input XOR function 15.3.14 Timers and external trigger synchronization Slave mode: Reset mode Slave mode: Gated mode Slave mode: Trigger mode Slave mode: External Clock mode 2 + trigger mode 15.3.15 Timer synchronization Using one timer as prescaler for another Using one timer to enable another timer Using one timer to start another timer Using one timer as prescaler for another timer Starting 2 timers synchronously in response to an external trigger 15.3.16 Debug mode 15.4 TIMx2 to TIM5 registers 15.4.1 TIMx control register 1 (TIMx_CR1) 15.4.2 TIMx control register 2 (TIMx_CR2) 15.4.3 TIMx slave mode control register (TIMx_SMCR) 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) 15.4.5 TIMx status register (TIMx_SR) 15.4.6 TIMx event generation register (TIMx_EGR) 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Output compare mode Input capture mode 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Output compare mode Input capture mode 15.4.9 TIMx capture/compare enable register (TIMx_CCER) 15.4.10 TIMx counter (TIMx_CNT) 15.4.11 TIMx prescaler (TIMx_PSC) 15.4.12 TIMx auto-reload register (TIMx_ARR) 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) 15.4.16 TIMx capture/compare register 4 (TIMx_CCR4) 15.4.17 TIMx DMA control register (TIMx_DCR) 15.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Example of how to use the DMA burst feature 15.4.19 TIMx register map 16 General-purpose timers (TIM9 to TIM14) 16.1 TIM9 to TIM14 introduction 16.2 TIM9 to TIM14 main features 16.2.1 TIM9/TIM12 main features 16.3 TIM10/TIM11 and TIM13/TIM14 main features 16.4 TIM9 to TIM14 functional description 16.4.1 Time-base unit Prescaler description 16.4.2 Counter modes Upcounting mode 16.4.3 Clock selection Internal clock source (CK_INT) External clock source mode 1(TIM9 and TIM12) 16.4.4 Capture/compare channels 16.4.5 Input capture mode 16.4.6 PWM input mode (only for TIM9/12) 16.4.7 Forced output mode 16.4.8 Output compare mode 16.4.9 PWM mode PWM edge-aligned mode 16.4.10 One-pulse mode (only for TIM9/12) 16.4.11 TIM9/12 external trigger synchronization Slave mode: Reset mode Slave mode: Gated mode Slave mode: Trigger mode 16.4.12 Timer synchronization (TIM9/12) 16.4.13 Debug mode 16.5 TIM9 and TIM12 registers 16.5.1 TIM9/12 control register 1 (TIMx_CR1) 16.5.2 TIM9/12 slave mode control register (TIMx_SMCR) 16.5.3 TIM9/12 Interrupt enable register (TIMx_DIER) 16.5.4 TIM9/12 status register (TIMx_SR) 16.5.5 TIM9/12 event generation register (TIMx_EGR) 16.5.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) Output compare mode Input capture mode 16.5.7 TIM9/12 capture/compare enable register (TIMx_CCER) 16.5.8 TIM9/12 counter (TIMx_CNT) 16.5.9 TIM9/12 prescaler (TIMx_PSC) 16.5.10 TIM9/12 auto-reload register (TIMx_ARR) 16.5.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) 16.5.12 TIM9/12 capture/compare register 2 (TIMx_CCR2) 16.5.13 TIM9/12 register map 16.6 TIM10/11/13/14 registers 16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1) 16.6.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) 16.6.3 TIM10/11/13/14 status register (TIMx_SR) 16.6.4 TIM10/11/13/14 event generation register (TIMx_EGR) 16.6.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Output compare mode Input capture mode 16.6.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) 16.6.7 TIM10/11/13/14 counter (TIMx_CNT) 16.6.8 TIM10/11/13/14 prescaler (TIMx_PSC) 16.6.9 TIM10/11/13/14 auto-reload register (TIMx_ARR) 16.6.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) 16.6.11 TIM10/11/13/14 register map 17 Basic timers (TIM6&TIM7) 17.1 TIM6&TIM7 introduction 17.2 TIM6&TIM7 main features 17.3 TIM6&TIM7 functional description 17.3.1 Time-base unit Prescaler description 17.3.2 Counting mode 17.3.3 Clock source 17.3.4 Debug mode 17.4 TIM6&TIM7 registers 17.4.1 TIM6&TIM7 control register 1 (TIMx_CR1) 17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) 17.4.3 TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) 17.4.4 TIM6&TIM7 status register (TIMx_SR) 17.4.5 TIM6&TIM7 event generation register (TIMx_EGR) 17.4.6 TIM6&TIM7 counter (TIMx_CNT) 17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) 17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) 17.4.9 TIM6&TIM7 register map 18 Real-time clock (RTC) 18.1 RTC introduction 18.2 RTC main features 18.3 RTC functional description 18.3.1 Overview 18.3.2 Resetting RTC registers 18.3.3 Reading RTC registers 18.3.4 Configuring RTC registers Configuration procedure: 18.3.5 RTC flag assertion 18.4 RTC registers 18.4.1 RTC control register high (RTC_CRH) 18.4.2 RTC control register low (RTC_CRL) 18.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) RTC prescaler load register high (RTC_PRLH) RTC prescaler load register low (RTC_PRLL) 18.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) RTC prescaler divider register high (RTC_DIVH) RTC prescaler divider register low (RTC_DIVL) 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) RTC counter register high (RTC_CNTH) RTC counter register low (RTC_CNTL) 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) RTC alarm register high (RTC_ALRH) RTC alarm register low (RTC_ALRL) 18.4.7 RTC register map 19 Independent watchdog (IWDG) 19.1 IWDG introduction 19.2 IWDG main features 19.3 IWDG functional description 19.3.1 Hardware watchdog 19.3.2 Register access protection 19.3.3 Debug mode 19.4 IWDG registers 19.4.1 Key register (IWDG_KR) 19.4.2 Prescaler register (IWDG_PR) 19.4.3 Reload register (IWDG_RLR) 19.4.4 Status register (IWDG_SR) 19.4.5 IWDG register map 20 Window watchdog (WWDG) 20.1 WWDG introduction 20.2 WWDG main features 20.3 WWDG functional description Enabling the watchdog Controlling the downcounter Advanced watchdog interrupt feature 20.4 How to program the watchdog timeout 20.5 Debug mode 20.6 WWDG registers 20.6.1 Control register (WWDG_CR) 20.6.2 Configuration register (WWDG_CFR) 20.6.3 Status register (WWDG_SR) 20.6.4 WWDG register map 21 Flexible static memory controller (FSMC) 21.1 FSMC main features 21.2 Block diagram 21.3 AHB interface 21.3.1 Supported memories and transactions General transaction rules Configuration registers 21.4 External device address mapping 21.4.1 NOR/PSRAM address mapping Wrap support for NOR Flash/PSRAM 21.4.2 NAND/PC Card address mapping 21.5 NOR Flash/PSRAM controller 21.5.1 External memory interface signals NOR Flash, nonmultiplexed I/Os NOR Flash, multiplexed I/Os PSRAM/SRAM 21.5.2 Supported memories and transactions 21.5.3 General timing rules Signals synchronization 21.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, SRAM) Mode 1 - SRAM/CRAM Mode A - SRAM/PSRAM (CRAM) OE toggling Mode 2/B - NOR Flash Mode C - NOR Flash - OE toggling Mode D - asynchronous access with extended address Mode muxed - asynchronous access muxed NOR Flash WAIT management in asynchronous accesses 21.5.5 Synchronous burst transactions Data latency versus NOR Flash latency Single-burst transfer Wait management 21.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) 21.6 NAND Flash/PC Card controller 21.6.1 External memory interface signals 8-bit NAND Flash 16-bit NAND Flash 21.6.2 NAND Flash / PC Card supported memories and transactions 21.6.3 Timing diagrams for NAND and PC Card 21.6.4 NAND Flash operations 21.6.5 NAND Flash pre-wait functionality 21.6.6 Error correction code computation ECC (NAND Flash) 21.6.7 PC Card/CompactFlash operations Address spaces & memory accesses Wait Feature 21.6.8 NAND Flash/PC Card controller registers PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) FIFO status and interrupt register 2..4 (FSMC_SR2..4) Common memory space timing register 2..4 (FSMC_PMEM2..4) Attribute memory space timing registers 2..4 (FSMC_PATT2..4) I/O space timing register 4 (FSMC_PIO4) ECC result registers 2/3 (FSMC_ECCR2/3) 21.6.9 FSMC register map 22 Secure digital input/output interface (SDIO) 22.1 SDIO main features 22.2 SDIO bus topology 22.3 SDIO functional description 22.3.1 SDIO adapter Adapter register block Control unit Command path Data path Data FIFO 22.3.2 SDIO AHB interface SDIO interrupts SDIO/DMA interface: procedure for data transfers between the SDIO and memory 22.4 Card functional description 22.4.1 Card identification mode 22.4.2 Card reset 22.4.3 Operating voltage range validation 22.4.4 Card identification process 22.4.5 Block write 22.4.6 Block read 22.4.7 Stream access, stream write and stream read (MultiMediaCard only) Stream write (MultiMediaCard only) Stream read (MultiMediaCard only) 22.4.8 Erase: group erase and sector erase 22.4.9 Wide bus selection or deselection 22.4.10 Protection management Internal card write protection Mechanical write protect switch Password protect Setting the password Resetting the password Locking a card Unlocking the card Forcing erase 22.4.11 Card status register 22.4.12 SD status register SIZE_OF_PROTECTED_AREA SPEED_CLASS PERFORMANCE_MOVE AU_SIZE ERASE_SIZE ERASE_TIMEOUT ERASE_OFFSET 22.4.13 SD I/O mode SD I/O interrupts SD I/O suspend and resume SD I/O ReadWait 22.4.14 Commands and responses Application-specific and general commands Command types Command formats Commands for the MultiMediaCard/SD module 22.5 Response formats 22.5.1 R1 (normal response command) 22.5.2 R1b 22.5.3 R2 (CID, CSD register) 22.5.4 R3 (OCR register) 22.5.5 R4 (Fast I/O) 22.5.6 R4b 22.5.7 R5 (interrupt request) 22.5.8 R6 22.6 SDIO I/O card-specific operations 22.6.1 SDIO I/O read wait operation by SDIO_D2 signalling 22.6.2 SDIO read wait operation by stopping SDIO_CK 22.6.3 SDIO suspend/resume operation 22.6.4 SDIO interrupts 22.7 CE-ATA specific operations 22.7.1 Command completion signal disable 22.7.2 Command completion signal enable 22.7.3 CE-ATA interrupt 22.7.4 Aborting CMD61 22.8 HW flow control 22.9 SDIO registers 22.9.1 SDIO power control register (SDIO_POWER) 22.9.2 SDI clock control register (SDIO_CLKCR) 22.9.3 SDIO argument register (SDIO_ARG) 22.9.4 SDIO command register (SDIO_CMD) 22.9.5 SDIO command response register (SDIO_RESPCMD) 22.9.6 SDIO response 1..4 register (SDIO_RESPx) 22.9.7 SDIO data timer register (SDIO_DTIMER) 22.9.8 SDIO data length register (SDIO_DLEN) 22.9.9 SDIO data control register (SDIO_DCTRL) 22.9.10 SDIO data counter register (SDIO_DCOUNT) 22.9.11 SDIO status register (SDIO_STA) 22.9.12 SDIO interrupt clear register (SDIO_ICR) 22.9.13 SDIO mask register (SDIO_MASK) 22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) 22.9.15 SDIO data FIFO register (SDIO_FIFO) 22.9.16 SDIO register map 23 Universal serial bus full-speed device interface (USB) 23.1 USB introduction 23.2 USB main features 23.3 USB functional description 23.3.1 Description of USB blocks 23.4 Programming considerations 23.4.1 Generic USB device programming 23.4.2 System and power-on reset USB reset (RESET interrupt) Structure and usage of packet buffers Endpoint initialization IN packets (data transmission) OUT and SETUP packets (data reception) Control transfers 23.4.3 Double-buffered endpoints 23.4.4 Isochronous transfers 23.4.5 Suspend/Resume events 23.5 USB registers 23.5.1 Common registers USB control register (USB_CNTR) USB interrupt status register (USB_ISTR) USB frame number register (USB_FNR) USB device address (USB_DADDR) Buffer table address (USB_BTABLE) 23.5.2 Endpoint-specific registers USB endpoint n register (USB_EPnR), n=[0..7] 23.5.3 Buffer descriptor table Transmission buffer address n (USB_ADDRn_TX) Transmission byte count n (USB_COUNTn_TX) Reception buffer address n (USB_ADDRn_RX) Reception byte count n (USB_COUNTn_RX) 23.5.4 USB register map 24 Controller area network (bxCAN) 24.1 bxCAN introduction 24.2 bxCAN main features 24.3 bxCAN general description 24.3.1 CAN 2.0B active core 24.3.2 Control, status and configuration registers 24.3.3 Tx mailboxes 24.3.4 Acceptance filters Receive FIFO 24.4 bxCAN operating modes 24.4.1 Initialization mode 24.4.2 Normal mode 24.4.3 Sleep mode (low power) 24.5 Test mode 24.5.1 Silent mode 24.5.2 Loop back mode 24.5.3 Loop back combined with silent mode 24.6 STM32F10xxx in Debug mode 24.7 bxCAN functional description 24.7.1 Transmission handling Transmit priority Abort Nonautomatic retransmission mode 24.7.2 Time triggered communication mode 24.7.3 Reception handling Valid message FIFO management Overrun Reception related interrupts 24.7.4 Identifier filtering Scalable width Mask mode Identifier list mode Filter bank scale and mode configuration Filter match index Filter priority rules 24.7.5 Message storage Transmit mailbox Receive mailbox 24.7.6 Error management Bus-Off recovery 24.7.7 Bit timing 24.8 bxCAN interrupts 24.9 CAN registers 24.9.1 Register access protection 24.9.2 CAN control and status registers CAN master control register (CAN_MCR) CAN master status register (CAN_MSR) CAN transmit status register (CAN_TSR) CAN receive FIFO 0 register (CAN_RF0R) CAN receive FIFO 1 register (CAN_RF1R) CAN interrupt enable register (CAN_IER) CAN error status register (CAN_ESR) CAN bit timing register (CAN_BTR) 24.9.3 CAN mailbox registers CAN TX mailbox identifier register (CAN_TIxR) (x=0..2) CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) CAN mailbox data low register (CAN_TDLxR) (x=0..2) CAN mailbox data high register (CAN_TDHxR) (x=0..2) CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1) CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) CAN receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1) 24.9.4 CAN filter registers CAN filter master register (CAN_FMR) CAN filter mode register (CAN_FM1R) CAN filter scale register (CAN_FS1R) CAN filter FIFO assignment register (CAN_FFA1R) CAN filter activation register (CAN_FA1R) Filter bank i register x (CAN_FiRx) (i=0..27, x=1, 2) 24.9.5 bxCAN register map 25 Serial peripheral interface (SPI) 25.1 SPI introduction 25.2 SPI and I2S main features 25.2.1 SPI features 25.2.2 I2S features 25.3 SPI functional description 25.3.1 General description Slave select (NSS) pin management Clock phase and clock polarity Data frame format 25.3.2 Configuring the SPI in slave mode Procedure Transmit sequence Receive sequence 25.3.3 Configuring the SPI in master mode Procedure Transmit sequence Receive sequence 25.3.4 Configuring the SPI for simplex communication 1 clock and 1 bidirectional data wire (BIDIMODE=1) 1 clock and 1 unidirectional data wire (BIDIMODE=0) 25.3.5 Data transmission and reception procedures Rx and Tx buffers Start sequence in slave mode Handling data transmission and reception Transmit-only procedure (BIDIMODE=0 RXONLY=0) Bidirectional transmit procedure (BIDIMODE=1 and BIDIOE=1) Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1) Bidirectional receive procedure (BIDIMODE=1 and BIDIOE=0) Continuous and discontinuous transfers 25.3.6 CRC calculation 25.3.7 Status flags Tx buffer empty flag (TXE) Rx buffer not empty (RXNE) BUSY flag 25.3.8 Disabling the SPI In master or slave full-duplex mode (BIDIMODE=0, RXONLY=0) In master or slave unidirectional transmit-only mode (BIDIMODE=0, RXONLY=0) or bidirectional transmit mode (BIDIMODE=1, BIDIOE=1) In master unidirectional receive-only mode (MSTR=1, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0) In slave receive-only mode (MSTR=0, BIDIMODE=0, RXONLY=1) or bidirectional receive mode (MSTR=0, BIDIMODE=1, BIDOE=0) 25.3.9 SPI communication using DMA (direct memory addressing) DMA capability with CRC 25.3.10 Error flags Master mode fault (MODF) Overrun condition CRC error 25.3.11 SPI interrupts 25.4 I2S functional description 25.4.1 The I2S audio protocol is not available in low- and medium-density devices. This section concerns only high-density, XL-density and connectivity line devices. I2S general description 25.4.2 Supported audio protocols I2S Phillips standard MSB justified standard LSB justified standard PCM standard 25.4.3 Clock generator 25.4.4 I2S master mode Procedure Transmission sequence Reception sequence 25.4.5 I2S slave mode Transmission sequence Reception sequence 25.4.6 Status flags Busy flag (BSY) Tx buffer empty flag (TXE) RX buffer not empty (RXNE) Channel Side flag (CHSIDE) 25.4.7 Error flags Underrun flag (UDR) Overrun flag (OVR) 25.4.8 I2S interrupts 25.4.9 DMA features 25.5 SPI and I2S registers 25.5.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) 25.5.2 SPI control register 2 (SPI_CR2) 25.5.3 SPI status register (SPI_SR) 25.5.4 SPI data register (SPI_DR) 25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode) 25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) 25.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) 25.5.8 SPI_I2S configuration register (SPI_I2SCFGR) 25.5.9 SPI_I2S prescaler register (SPI_I2SPR) 25.5.10 SPI register map 26 Inter-integrated circuit (I2C) interface 26.1 I2C introduction 26.2 I2C main features 26.3 I2C functional description 26.3.1 Mode selection Communication flow 26.3.2 I2C slave mode Slave transmitter Slave receiver Closing slave communication 26.3.3 I2C master mode Start condition Slave address transmission Master transmitter Master receiver 26.3.4 Error conditions Bus error (BERR) Acknowledge failure (AF) Arbitration lost (ARLO) Overrun/underrun error (OVR) 26.3.5 SDA/SCL line control 26.3.6 SMBus Introduction Similarities between SMBus and I2C Differences between SMBus and I2C SMBus application usage Device identification Bus protocols Address resolution protocol (ARP) Unique device identifier (UDID) SMBus alert mode Timeout error How to use the interface in SMBus mode 26.3.7 DMA requests Transmission using DMA Reception using DMA 26.3.8 Packet error checking 26.4 I2C interrupts 26.5 I2C debug mode 26.6 I2C registers 26.6.1 I2C Control register 1 (I2C_CR1) 26.6.2 I2C Control register 2 (I2C_CR2) 26.6.3 I2C Own address register 1 (I2C_OAR1) 26.6.4 I2C Own address register 2 (I2C_OAR2) 26.6.5 I2C Data register (I2C_DR) 26.6.6 I2C Status register 1 (I2C_SR1) 26.6.7 I2C Status register 2 (I2C_SR2) 26.6.8 I2C Clock control register (I2C_CCR) 26.6.9 I2C TRISE register (I2C_TRISE) 26.6.10 I2C register map 27 Universal synchronous asynchronous receiver transmitter (USART) 27.1 USART introduction 27.2 USART main features 27.3 USART functional description 27.3.1 USART character description 27.3.2 Transmitter Character transmission Configurable stop bits Single byte communication Break characters Idle characters 27.3.3 Receiver Start bit detection Character reception Break character Idle character Overrun error Noise error Framing error Configurable stop bits during reception 27.3.4 Fractional baud rate generation How to derive USARTDIV from USART_BRR register values 27.3.5 USART receiver’s tolerance to clock deviation 27.3.6 Multiprocessor communication Idle line detection (WAKE=0) Address mark detection (WAKE=1) 27.3.7 Parity control 27.3.8 LIN (local interconnection network) mode LIN transmission LIN reception 27.3.9 USART synchronous mode 27.3.10 Single-wire half-duplex communication 27.3.11 Smartcard 27.3.12 IrDA SIR ENDEC block IrDA low-power mode 27.3.13 Continuous communication using DMA Transmission using DMA Reception using DMA Error flagging and interrupt generation in multibuffer communication 27.3.14 Hardware flow control RTS flow control CTS flow control 27.4 USART interrupts 27.5 USART mode configuration 27.6 USART registers 27.6.1 Status register (USART_SR) 27.6.2 Data register (USART_DR) 27.6.3 Baud rate register (USART_BRR) 27.6.4 Control register 1 (USART_CR1) 27.6.5 Control register 2 (USART_CR2) 27.6.6 Control register 3 (USART_CR3) 27.6.7 Guard time and prescaler register (USART_GTPR) 27.6.8 USART register map 28 USB on-the-go full-speed (OTG_FS) 28.1 OTG_FS introduction 28.2 OTG_FS main features 28.2.1 General features 28.2.2 Host-mode features 28.2.3 Peripheral-mode features 28.3 OTG_FS functional description 28.3.1 OTG full-speed core 28.3.2 Full-speed OTG PHY 28.4 OTG dual role device (DRD) 28.4.1 ID line detection 28.4.2 HNP dual role device 28.4.3 SRP dual role device 28.5 USB peripheral 28.5.1 SRP-capable peripheral 28.5.2 Peripheral states Powered state Soft disconnect Default state Suspended state 28.5.3 Peripheral endpoints Endpoint control Endpoint transfer Endpoint status/interrupt 28.6 USB host 28.6.1 SRP-capable host 28.6.2 USB host states Host port power VBUS valid Host detection of a peripheral connection Host detection of peripheral a disconnection Host enumeration Host suspend 28.6.3 Host channels Host channel control Host channel transfer Host channel status/interrupt 28.6.4 Host scheduler 28.7 SOF trigger 28.7.1 Host SOFs 28.7.2 Peripheral SOFs 28.8 Power options 28.9 Dynamic update of the OTG_FS_HFIR register 28.10 USB data FIFOs 28.11 Peripheral FIFO architecture 28.11.1 Peripheral Rx FIFO 28.11.2 Peripheral Tx FIFOs 28.12 Host FIFO architecture 28.12.1 Host Rx FIFO 28.12.2 Host Tx FIFOs 28.13 FIFO RAM allocation 28.13.1 Device mode 28.13.2 Host mode Receive FIFO RAM allocation Transmit FIFO RAM allocation 28.14 USB system performance 28.15 OTG_FS interrupts 28.16 OTG_FS control and status registers 28.16.1 CSR memory map Global CSR map Host-mode CSR map Device-mode CSR map Data FIFO (DFIFO) access register map Power and clock gating CSR map 28.16.2 OTG_FS global registers OTG_FS control and status register (OTG_FS_GOTGCTL) OTG_FS interrupt register (OTG_FS_GOTGINT) OTG_FS AHB configuration register (OTG_FS_GAHBCFG) OTG_FS USB configuration register (OTG_FS_GUSBCFG) OTG_FS reset register (OTG_FS_GRSTCTL) OTG_FS core interrupt register (OTG_FS_GINTSTS) OTG_FS interrupt mask register (OTG_FS_GINTMSK) OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) Host mode: Device mode: OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0) OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_HNPTXSTS) OTG_FS general core configuration register (OTG_FS_GCCFG) OTG_FS core ID register (OTG_FS_CID) OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) 28.16.3 Host-mode registers OTG_FS Host configuration register (OTG_FS_HCFG) OTG_FS Host frame interval register (OTG_FS_HFIR) OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM) OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) OTG_FS Host all channels interrupt register (OTG_FS_HAINT) OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) OTG_FS Host port control and status register (OTG_FS_HPRT) OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number) OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, where x = Channel_number) OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number) OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number) 28.16.4 Device-mode registers OTG_FS device configuration register (OTG_FS_DCFG) OTG_FS device control register (OTG_FS_DCTL) OTG_FS device status register (OTG_FS_DSTS) OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) OTG_FS device VBUS discharge time register (OTG_FS_DVBUSDIS) OTG_FS device VBUS pulsing time register (OTG_FS_DVBUSPULSE) OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK) OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number) OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0) OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3, where x = Endpoint_number) OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number) OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number) OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0) OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0) OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number) OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) OTG_FS device OUT endpoint-x transfer size register (OTG_FS_DOEPTSIZx) (x = 1..3, where x = Endpoint_number) 28.16.5 OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) 28.16.6 OTG_FS register map 28.17 OTG_FS programming model 28.17.1 Core initialization 28.17.2 Host initialization 28.17.3 Device initialization 28.17.4 Host programming model Channel initialization Halting a channel Operational model 28.17.5 Device programming model Endpoint initialization on USB reset Endpoint initialization on enumeration completion Endpoint initialization on SetAddress command Endpoint initialization on SetConfiguration/SetInterface command Endpoint activation Endpoint deactivation 28.17.6 Operational model SETUP and OUT data transfers Examples IN data transfers 28.17.7 Worst case response time Choosing the value of TRDT in OTG_FS_GUSBCFG 28.17.8 OTG programming model A-device session request protocol B-device session request protocol A-device host negotiation protocol B-device host negotiation protocol 29 Ethernet (ETH): media access control (MAC) with DMA controller 29.1 Ethernet introduction 29.2 Ethernet main features 29.2.1 MAC core features 29.2.2 DMA features 29.2.3 PTP features 29.3 Ethernet pins 29.4 Ethernet functional description: SMI, MII and RMII 29.4.1 Station management interface: SMI SMI frame format SMI write operation SMI read operation SMI clock selection 29.4.2 Media-independent interface: MII MII clock sources 29.4.3 Reduced media-independent interface: RMII RMII clock sources 29.4.4 MII/RMII selection MII/RMII internal clock scheme 29.5 Ethernet functional description: MAC 802.3 29.5.1 MAC 802.3 frame format 29.5.2 MAC frame transmission Automatic CRC and pad generation Transmit protocol Transmit scheduler Transmit flow control Retransmission during collision Transmit FIFO flush operation Transmit status word Transmit checksum offload MII/RMII transmit bit order MII/RMII transmit timing diagrams 29.5.3 MAC frame reception Receive protocol Receive CRC: automatic CRC and pad stripping Receive checksum offload Receive frame controller Receive flow control Receive operation multiframe handling Error handling Receive status word Frame length interface MII/RMII receive bit order 29.5.4 MAC interrupts 29.5.5 MAC filtering Address filtering Unicast destination address filter Multicast destination address filter Hash or perfect address filter Broadcast address filter Unicast source address filter Inverse filtering operation 29.5.6 MAC loopback mode 29.5.7 MAC management counters: MMC Good transmitted and received frames 29.5.8 Power management: PMT Remote wakeup frame filter register Remote wakeup frame detection Magic packet detection System consideration during power-down 29.5.9 Precision time protocol (IEEE1588 PTP) Reference timing source Transmission of frames with the PTP feature Reception of frames with the PTP feature System Time correction methods Programming steps for system time generation initialization Programming steps for system time update in the Coarse correction method Programming steps for system time update in the Fine correction method PTP trigger internal connection with TIM2 PTP pulse-per-second output signal 29.6 Ethernet functional description: DMA controller operation 29.6.1 Initialization of a transfer using DMA 29.6.2 Host bus burst access 29.6.3 Host data buffer alignment 29.6.4 Buffer size calculations 29.6.5 DMA arbiter 29.6.6 Error response to DMA 29.6.7 Tx DMA configuration TxDMA operation: default (non-OSF) mode TxDMA operation: OSF mode Transmit frame processing Transmit polling suspended Tx DMA descriptors 29.6.8 Rx DMA configuration Receive descriptor acquisition Receive frame processing Receive process suspended Rx DMA descriptors 29.6.9 DMA interrupts 29.7 Ethernet interrupts 29.8 Ethernet register descriptions 29.8.1 MAC register description Ethernet MAC configuration register (ETH_MACCR) Ethernet MAC frame filter register (ETH_MACFFR) Ethernet MAC hash table high register (ETH_MACHTHR) Ethernet MAC hash table low register (ETH_MACHTLR) Ethernet MAC MII address register (ETH_MACMIIAR) Ethernet MAC MII data register (ETH_MACMIIDR) Ethernet MAC flow control register (ETH_MACFCR) Ethernet MAC VLAN tag register (ETH_MACVLANTR) Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) Ethernet MAC PMT control and status register (ETH_MACPMTCSR) Ethernet MAC interrupt status register (ETH_MACSR) Ethernet MAC interrupt mask register (ETH_MACIMR) Ethernet MAC address 0 high register (ETH_MACA0HR) Ethernet MAC address 0 low register (ETH_MACA0LR) Ethernet MAC address 1 high register (ETH_MACA1HR) Ethernet MAC address1 low register (ETH_MACA1LR) Ethernet MAC address 2 high register (ETH_MACA2HR) Ethernet MAC address 2 low register (ETH_MACA2LR) Ethernet MAC address 3 high register (ETH_MACA3HR) Ethernet MAC address 3 low register (ETH_MACA3LR) 29.8.2 MMC register description Ethernet MMC control register (ETH_MMCCR) Ethernet MMC receive interrupt register (ETH_MMCRIR) Ethernet MMC transmit interrupt register (ETH_MMCTIR) Ethernet MMC receive interrupt mask register (ETH_MMCRIMR) Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR) Ethernet MMC transmitted good frames after a single collision counter register (ETH_MMCTGFSCCR) Ethernet MMC transmitted good frames after more than a single collision counter register (ETH_MMCTGFMSCCR) Ethernet MMC transmitted good frames counter register (ETH_MMCTGFCR) Ethernet MMC received frames with CRC error counter register (ETH_MMCRFCECR) Ethernet MMC received frames with alignment error counter register (ETH_MMCRFAECR) MMC received good unicast frames counter register (ETH_MMCRGUFCR) 29.8.3 IEEE 1588 time stamp registers Ethernet PTP time stamp control register (ETH_PTPTSCR) Ethernet PTP subsecond increment register (ETH_PTPSSIR) Ethernet PTP time stamp high register (ETH_PTPTSHR) Ethernet PTP time stamp low register (ETH_PTPTSLR) Ethernet PTP time stamp high update register (ETH_PTPTSHUR) Ethernet PTP time stamp low update register (ETH_PTPTSLUR) Ethernet PTP time stamp addend register (ETH_PTPTSAR) Ethernet PTP target time high register (ETH_PTPTTHR) Ethernet PTP target time low register (ETH_PTPTTLR) 29.8.4 DMA register description Ethernet DMA bus mode register (ETH_DMABMR) Ethernet DMA transmit poll demand register (ETH_DMATPDR) EHERNET DMA receive poll demand register (ETH_DMARPDR) Ethernet DMA receive descriptor list address register (ETH_DMARDLAR) Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR) Ethernet DMA status register (ETH_DMASR) Ethernet DMA operation mode register (ETH_DMAOMR) Ethernet DMA interrupt enable register (ETH_DMAIER) Ethernet DMA missed frame and buffer overflow counter register (ETH_DMAMFBOCR) Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR) Ethernet DMA current host receive descriptor register (ETH_DMACHRDR) Ethernet DMA current host transmit buffer address register (ETH_DMACHTBAR) Ethernet DMA current host receive buffer address register (ETH_DMACHRBAR) 29.8.5 Ethernet register maps 30 Device electronic signature 30.1 Memory size registers 30.1.1 Flash size register 30.2 Unique device ID register (96 bits) Base address: 0x1FFF F7E8 31 Debug support (DBG) 31.1 Overview 31.2 Reference ARM documentation 31.3 SWJ debug port (serial wire and JTAG) 31.3.1 Mechanism to select the JTAG-DP or the SW-DP 31.4 Pinout and debug port pins 31.4.1 SWJ debug port pins 31.4.2 Flexible SWJ-DP pin assignment 31.4.3 Internal pull-up and pull-down on JTAG pins 31.4.4 Using serial wire and releasing the unused debug pins as GPIOs 31.5 STM32F10xxx JTAG TAP connection 31.6 ID codes and locking mechanism 31.6.1 MCU device ID code DBGMCU_IDCODE 31.6.2 Boundary scan TAP JTAG ID code 31.6.3 Cortex™-M3 TAP 31.6.4 Cortex™-M3 JEDEC-106 ID code 31.7 JTAG debug port 31.8 SW debug port 31.8.1 SW protocol introduction 31.8.2 SW protocol sequence 31.8.3 SW-DP state machine (reset, idle states, ID code) 31.8.4 DP and AP read/write accesses 31.8.5 SW-DP registers 31.8.6 SW-AP registers 31.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP Features: 31.10 Core debug 31.11 Capability of the debugger host to connect under system reset 31.12 FPB (Flash patch breakpoint) 31.13 DWT (data watchpoint trigger) 31.14 ITM (instrumentation trace macrocell) 31.14.1 General description 31.14.2 Time stamp packets, synchronization and overflow packets Example of configuration 31.15 ETM (Embedded trace macrocell) 31.15.1 General description 31.15.2 Signal protocol, packet types 31.15.3 Main ETM registers 31.15.4 Configuration example 31.16 MCU debug component (DBGMCU) 31.16.1 Debug support for low-power modes 31.16.2 Debug support for timers, watchdog, bxCAN and I2C 31.16.3 Debug MCU configuration register DBGMCU_CR 31.17 TPIU (trace port interface unit) 31.17.1 Introduction 31.17.2 TRACE pin assignment TPUI TRACE pin assignment 31.17.3 TPUI formatter 31.17.4 TPUI frame synchronization packets 31.17.5 Transmission of the synchronization frame packet 31.17.6 Synchronous mode 31.17.7 Asynchronous mode 31.17.8 TRACECLKIN connection inside the STM32F10xxx 31.17.9 TPIU registers 31.17.10 Example of configuration 31.18 DBG register map 32 Revision history Index " .
}
}
WHERE {
?tag1 a nao:Tag ; nao:prefLabel "Technical Literature" .
?tag2 a nao:Tag ; nao:prefLabel "13902" .
?tag3 a nao:Tag ; nao:prefLabel "Product Development" .
?tag4 a nao:Tag ; nao:prefLabel "Specification" .
?tag5 a nao:Tag ; nao:prefLabel "Reference manual" .
?tag6 a nao:Tag ; nao:prefLabel "STM32F103ZG" .
?tag7 a nao:Tag ; nao:prefLabel "STM32F103ZF" .
?tag8 a nao:Tag ; nao:prefLabel "STM32F103ZE" .
?tag9 a nao:Tag ; nao:prefLabel "STM32F103ZD" .
?tag10 a nao:Tag ; nao:prefLabel "STM32F103ZC" .
?tag11 a nao:Tag ; nao:prefLabel "STM32F103VG" .
?tag12 a nao:Tag ; nao:prefLabel "STM32F103VF" .
?tag13 a nao:Tag ; nao:prefLabel "STM32F103VE" .
?tag14 a nao:Tag ; nao:prefLabel "STM32F103VD" .
?tag15 a nao:Tag ; nao:prefLabel "STM32F103VC" .
?tag16 a nao:Tag ; nao:prefLabel "STM32F103VB" .
?tag17 a nao:Tag ; nao:prefLabel "STM32F103V8" .
?tag18 a nao:Tag ; nao:prefLabel "STM32F103TC" .
?tag19 a nao:Tag ; nao:prefLabel "STM32F103TB" .
?tag20 a nao:Tag ; nao:prefLabel "STM32F103T8" .
?tag21 a nao:Tag ; nao:prefLabel "STM32F103T6" .
?tag22 a nao:Tag ; nao:prefLabel "STM32F103T4" .
?tag23 a nao:Tag ; nao:prefLabel "STM32F103S6" .
?tag24 a nao:Tag ; nao:prefLabel "STM32F103RG" .
?tag25 a nao:Tag ; nao:prefLabel "STM32F103RF" .
?tag26 a nao:Tag ; nao:prefLabel "STM32F103RE" .
?tag27 a nao:Tag ; nao:prefLabel "STM32F103RD" .
?tag28 a nao:Tag ; nao:prefLabel "STM32F103RC" .
?tag29 a nao:Tag ; nao:prefLabel "STM32F103RB" .
?tag30 a nao:Tag ; nao:prefLabel "STM32F103R8" .
?tag31 a nao:Tag ; nao:prefLabel "STM32F103R6" .
?tag32 a nao:Tag ; nao:prefLabel "STM32F103R4" .
?tag33 a nao:Tag ; nao:prefLabel "STM32F103EDIE" .
?tag34 a nao:Tag ; nao:prefLabel "STM32F103CB" .
?tag35 a nao:Tag ; nao:prefLabel "STM32F103C8" .
?tag36 a nao:Tag ; nao:prefLabel "STM32F103C6" .
?tag37 a nao:Tag ; nao:prefLabel "STM32F103C4" .
?tag38 a nao:Tag ; nao:prefLabel "STM32F103BDIE" .
?tag39 a nao:Tag ; nao:prefLabel "STM32F1036DIE" .
?tag40 a nao:Tag ; nao:prefLabel "STM32F102T8" .
?tag41 a nao:Tag ; nao:prefLabel "STM32F102RC" .
?tag42 a nao:Tag ; nao:prefLabel "STM32F102RB" .
?tag43 a nao:Tag ; nao:prefLabel "STM32F102R8" .
?tag44 a nao:Tag ; nao:prefLabel "STM32F102R6" .
?tag45 a nao:Tag ; nao:prefLabel "STM32F102R4" .
?tag46 a nao:Tag ; nao:prefLabel "STM32F102CB" .
?tag47 a nao:Tag ; nao:prefLabel "STM32F102C8" .
?tag48 a nao:Tag ; nao:prefLabel "STM32F102C6" .
?tag49 a nao:Tag ; nao:prefLabel "STM32F102C4" .
?tag50 a nao:Tag ; nao:prefLabel "STM32F101ZG" .
?tag51 a nao:Tag ; nao:prefLabel "STM32F101C4" .
?tag52 a nao:Tag ; nao:prefLabel "STM32F101C6" .
?tag53 a nao:Tag ; nao:prefLabel "STM32F101C8" .
?tag54 a nao:Tag ; nao:prefLabel "STM32F101CB" .
?tag55 a nao:Tag ; nao:prefLabel "STM32F101R4" .
?tag56 a nao:Tag ; nao:prefLabel "STM32F101R6" .
?tag57 a nao:Tag ; nao:prefLabel "STM32F101R8" .
?tag58 a nao:Tag ; nao:prefLabel "STM32F101RB" .
?tag59 a nao:Tag ; nao:prefLabel "STM32F101RC" .
?tag60 a nao:Tag ; nao:prefLabel "STM32F101RD" .
?tag61 a nao:Tag ; nao:prefLabel "STM32F101RE" .
?tag62 a nao:Tag ; nao:prefLabel "STM32F101T4" .
?tag63 a nao:Tag ; nao:prefLabel "STM32F101T6" .
?tag64 a nao:Tag ; nao:prefLabel "STM32F101T8" .
?tag65 a nao:Tag ; nao:prefLabel "STM32F101TB" .
?tag66 a nao:Tag ; nao:prefLabel "STM32F101V8" .
?tag67 a nao:Tag ; nao:prefLabel "STM32F101VB" .
?tag68 a nao:Tag ; nao:prefLabel "STM32F101VC" .
?tag69 a nao:Tag ; nao:prefLabel "STM32F101VD" .
?tag70 a nao:Tag ; nao:prefLabel "STM32F101VE" .
?tag71 a nao:Tag ; nao:prefLabel "STM32F101ZC" .
?tag72 a nao:Tag ; nao:prefLabel "STM32F101ZD" .
?tag73 a nao:Tag ; nao:prefLabel "STM32F101ZE" .
?tag74 a nao:Tag ; nao:prefLabel "STM32F107VC" .
?tag75 a nao:Tag ; nao:prefLabel "STM32F107VB" .
?tag76 a nao:Tag ; nao:prefLabel "STM32F107RC" .
?tag77 a nao:Tag ; nao:prefLabel "STM32F107RB" .
?tag78 a nao:Tag ; nao:prefLabel "STM32F105VC" .
?tag79 a nao:Tag ; nao:prefLabel "STM32F105VB" .
?tag80 a nao:Tag ; nao:prefLabel "STM32F105V8" .
?tag81 a nao:Tag ; nao:prefLabel "STM32F105RC" .
?tag82 a nao:Tag ; nao:prefLabel "STM32F105RB" .
?tag83 a nao:Tag ; nao:prefLabel "STM32F105R8" .
?tag84 a nao:Tag ; nao:prefLabel "STM32F101RF" .
?tag85 a nao:Tag ; nao:prefLabel "STM32F101RG" .
?tag86 a nao:Tag ; nao:prefLabel "STM32F101VF" .
?tag87 a nao:Tag ; nao:prefLabel "STM32F101VG" .
}



Received signal:2->'Interrupt'
Tracker-Message: --------------------------------------------------
Tracker-Message: Statistics:
Tracker-Message:     Module:'libextract-pdf.so', extracted:1, failures:0
Tracker-Message: Unhandled files: 0
Tracker-Message: --------------------------------------------------
Tracker-Message: Closed sqlite3 database:'/home/zach/.cache/tracker/meta.db'
Tracker-Message: Stopping tracker-extract 1.2.5
