--! \file
--! Abstract: \brief  short_abstract
--! 
--! Test module 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
Library UNIMACRO;
use unimacro.vcomponents.all;


entity receiver is
	port(
		rst     : in  std_logic;
		clk     : in  std_logic;
		dat_in  : in  std_logic;
		dat_out : out std_logic
	);
end entity receiver;

architecture rtl of receiver is
	
	signal toggle    : std_logic_vector(7 downto 0); --! toggles between 0 and 1
	
	signal count : integer range 0 to 2047; --! byte counter
	
begin
	
--! \brief Test process 1
--!
--! Long description
	first_process: process (clk, rst) is
	begin
		if rst = '1' then
			dat_out <= (others => '0');
		elsif rising_edge(clk) then
			dat_out <= dat_in;
		end if;
	end process first_process;
	
	
--! \brief Test process 2
--!
--! Long description
	second_process: process (rst, clk) is
	begin
		if rst = '1' then
			count <= 0;
		elsif rising_edge(clk) then
			count <= count + 1;
		end if;
	end process second_process;
	
	
--! \brief Test process 3
--!
--! Long description
	third_process: process (clk, rst) is
	begin
		if rst = '1' then
			toggle <= '0';
		elsif rising_edge(clk) then
			toggle <= not toggle;
		end if;
	end process third_process;
	
	
end architecture rtl;
