--! @file
--!
--! Example component for Doxygen debugging (Bugzilla ref 701919).
--! Demonstrates failing aliased xref lines when unpaired apostrophe is used in preceding code.
--! Remove the commented apostrophe from line 52 to enable the failure condition.
--! Note that only this section and the process headers have been converted to Doxygen style comments.
--!

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------

entity doxy_test is

    port (clk       : in  std_logic;                      --system clock input
          reset     : in  std_logic;                      --reset input (active low)
          data_in   : in  std_logic_vector(7 downto 0);   --data bus input
          ctrl_in   : in  std_logic_vector(3 downto 0);   --data control bus input
          enable_in : in  std_logic;                      --enable input
          data_out  : out std_logic_vector(7 downto 0);   --data bus output
          ctrl_out  : out std_logic_vector(3 downto 0));  --data control bus output

end entity doxy_test;

--------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------

architecture rtl of doxy_test is

    signal data_in_reg   : std_logic_vector(7 downto 0);  --data bus input (registered)
    signal ctrl_in_reg   : std_logic_vector(3 downto 0);  --data control bus input (registered)
    signal enable_in_reg : std_logic;                     --enable input (registered)

begin

    --! This process implements input registers for the data and control buses.
    --!
    --! @MY_XREF_1
    --! @MY_XREF_2
    --!
    reg_in: process(clk, reset) is
    begin
        if (reset = '1') then

            data_in_reg <= (others => '0');
            ctrl_in_reg <= (others => '0');

        elsif rising_edge(clk) then

            data_in_reg <= data_in(data_in'high downto 0);  --'  <-- REMOVE THIS EXTRA APOSTROPHE FOR FAILURE!
            ctrl_in_reg <= ctrl_in;

        end if;
    end process reg_in;

    --------------------------------------------------------------------------------------------

    --! This process implements selective output registering for the data and control buses.
    --! The aliased xrefs here cause Doxywizard warnings and are missed in the generated HTML documentation when line 52 is modified
    --!
    --! @MY_XREF_3
    --! @MY_XREF_4
    --!
    reg_out: process(clk, reset) is
    begin
        if (reset = '1') then

            enable_in_reg <= '0';
            data_out      <= (others => '0');
            ctrl_out      <= (others => '0');

        elsif rising_edge(clk) then

            enable_in_reg <= enable_in;

            if (enable_in_reg = '1') then
                data_out <= data_in_reg;
                ctrl_out <= ctrl_in_reg;
            else
                data_out <= (others => '0');
                ctrl_out <= (others => '0');
            end if;

        end if;
    end process reg_out;

end architecture rtl;
