/*========================================================================*//*!
\mainpage Doxygen VHDL Example

\section mainpage_introduction Introduction

This project contains to libraries, my_design_lib and my_project_lib.

my_design_lib contains a single, reusable component, %addressable_shift_register,
a components package and a package containing utility functions.

my_project_lib contains a single entity that instantiates %addressable_shift_register
and uses a function from the utilities package.

With EXTRACT_PACKAGE set to its default value (false), the two packages are
listed on the Packages page.  However, they do not appear hyperlinked under
Modules -> VHDL Libraries -> my_design_lib.  (Setting EXTRACT_PACKAGE to true
does appear to fix this problem (although this behaviour is not very intuitive).)

In all cases, eg, detailed description of addressable_shift_register, example_design
and design_components_pkg, the detailed description text appears to have been lost.
Moreover, in the case of the package headers, the tool appears to have incorrectly
taken the brief for the first item \e inside the package header as the brief for
the package header itself.  (This then causes a warning to be generated stating
that the first item is not documented!)

The process and component instantiation inside example_design do not appear to
have been documented.  Presumably this is why there is no design hierarchy shown?

*//*=========================================================================*/

/*========================================================================*//*!
\defgroup vhdl_libraries VHDL Libraries
@{
    \defgroup my_design_lib my_design_lib
    \brief Library of reusable components and functions for synthesis

    \defgroup my_project_lib my_project_lib
    \brief Library containing project files
@}
*//*=========================================================================*/
